Currently when building mxsboot on certain machines it reports:
HOSTCC tools/mxsboot
tools/mxsboot.c: In function 'mx28_create_sd_image':
tools/mxsboot.c:560: warning: implicit declaration of function 'htole32'
/tmp/cchLIV6q.o: In function 'main':
mxsboot.c:(.text+0x6d8): undefined reference to 'htole32'
mxsboot.c:(.text+0x6e7): undefined reference to 'htole32'
mxsboot.c:(.text+0x6f6): undefined reference to 'htole32'
mxsboot.c:(.text+0x705): undefined reference to 'htole32'
mxsboot.c:(.text+0x711): undefined reference to 'htole32'
/tmp/cchLIV6q.o:mxsboot.c:(.text+0x71d): more undefined references to
'htole32' follow
collect2: ld returned 1 exit status
make[1]: *** [tools/mxsboot] Error 1
make: *** [tools] Error 2
The solution is to use cpu_to_le32() instead which is more portable,
just like other U-Boot tools [1] do.
[1] http://lists.denx.de/pipermail/u-boot/2014-October/192919.html
Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
All boards that support PXE booting use the pxefile_addr_r variable. Standardise
wandboard with this variable as pxe_addr_r isn't used anywhere else so it's a
typo.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
Enable the DDR calibration functionality on Novena to deal with the
memory SoDIMM on this board. Moreover, tweak the initial DDR DRAM
parameters so the calibration works properly.
Signed-off-by: Marek Vasut <marex@denx.de>
Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
fine-tunes the behavior of the MMDC controller in order to improve
the signal integrity and memory stability.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
The sama5d2 Xplained SPL supports the boot medias: spi flash
and SD Card.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
To remove the unnecessary #ifdef-endif, use the mpddrc IP version
to check whether or not the interleaved decoding type is supported.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
The DDR3-SDRAM initialization sequence is implemented in
accordance with the DDR3-SRAM/DDR3L-SDRAM initialization section
described in the SAMA5D2 datasheet.
Add registers and definitions of mpddrc controller, which is used
to support DDR3 devices.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Add struct atmel_mpddrc_config to accommodate the mpddrc register
configurations, not using the mpddrc register map structure,
struct atmel_mpddrc, in order to increase readability and reduce
run-time memory use.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Also if minimum ecc requirment is bigger then what we support, then just
use our maxium pmecc support.
But it is not safe, so we'll output a warning about this.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
1. add the pmecc register mapping for sama5d2.
2. add the pmecc error location register mapping for sama5d2.
3. add some new field that is different from old ip.
4. add sama5d2 pmecc ip version number.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
When OF_CONTROL is enabled, u-boot-dtb.* files are the same as u-boot.*
files. So we can use the latter for simplicity.
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Create u-boot.img even when OF_CONTROL is enabled, so that this file can be
used in both cases.
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Adjust the Makefile to build u-boot-tegra.bin which contains a device tree
if OF_SEPARATE is enabled, and does not if not. This mirrors U-Boot's new
approach of using u-boot.bin to handle both cases.
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
At present u-boot-spl.bin holds the plain SPL binary without the device
tree. This is somewhat annoying since you need either u-boot-spl.bin or
u-boot-spl-dtb.bin depending on whether device tree is used.
Adjust the build such that u-boot-spl.bin includes a device tree
(if enabled), and the plain binary is in u-boot-spl-nodtb.bin. For now
u-boot-spl-dtb.bin remains the same.
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
At present u-boot.bin holds the plain U-Boot binary without the device tree.
This is somewhat annoying since you need either u-boot.bin or u-boot-dtb.bin
depending on whether device tree is used.
Adjust the build such that u-boot.bin includes a device tree (if enabled),
and the plain binary is in u-boot-nodtb.bin. For now u-boot-dtb.bin remains
the same.
This should be acceptable since:
- without OF_CONTROL, u-boot.bin still does not include a device tree
- with OF_CONTROL, u-boot-dtb.bin does not change
The main impact is build systems which are set up to use u-boot.bin as
the output file and then add a device tree. These will have to change to use
u-boot-nodtb.bin instead.
Adjust tegra rules so it continues to produce the correct files.
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Fix the ALL-y logic in the Makefile so that is clear that we always want
the -nodtb file.
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Commit df48b23428 (".mailmap: Add all the mail alias for Ricardo
Ribalda") assigned two different proper names for the email address
"ricardo.ribalda@uam.es". This is a completely wrong usage as the
mailmap feature exists for coalescing together commits by the same
person whose name is sometimes spelled differently.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This is a follow-up patch to e92029c0f4 and adds a prototype for
the weak mmc_get_env_dev function.
Cc: Tom Rini <trini@konsulko.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Use of memalign can trigger fragmentation issues such as:
// Internally, this needs to find a free block quite bit larger than s.
// Once the free region is found, any unaligned "padding" immediately
// before and after the block is marked free, so that the allocation
// takes only s bytes (plus malloc header overhead).
p = memalign(a, s);
// If there's little fragmentation so far, this allocation is likely
// located immediately after p.
p2 = malloc(x);
free(p);
// In theory, this should return the same value for p. However, the hole
// left by the free() call is only s in size (plus malloc header overhead)
// whereas memalign searches for a larger block in order to guarantee it
// can adjust the returned pointer to the alignment requirements. Hence,
// the pointer returned, if any, won't be p. If there's little or no space
// left after p2, this allocation will fail.
p = memalign(a, s);
In practice, this issue occurs when running the "dfu" command repeatedly
on NVIDIA Tegra boards, since DFU allocates a large 32M data buffer, and
then initializes the USB controller. If this is the first time USB has
been used in the U-Boot session, this causes a probe of the USB driver,
which causes various allocations, including a strdup() of a GPIO name
when requesting the VBUS GPIO. When DFU is torn down, the USB driver
is left probed, and hence its memory is left allocated. If "dfu" is
executed again, allocation of the 32M data buffer fails as described
above.
In practice, there is a memory hole exactly large enough to hold the 32M
data buffer than DFU needs. However, memalign() can't know that in a
general way. Given that, it's particularly annoying that the allocation
fails!
The issue is that memalign() tries to allocate something larger to
guarantee the ability to align the returned pointer. This patch modifies
memalign() so that if the "general case" over-sized allocation fails,
another allocation is attempted, of the exact size the user desired. If
that allocation just happens to be aligned in the way the user wants,
(and in the case described above, it will be, since the free memory
region is located where a previous identical allocation was located),
the pointer can be returned.
This patch is somewhat related to 806bd245b1 "dfu: don't keep
freeing/reallocating". That patch worked around the issue by removing
repeated free/memalign within a single execution of "dfu". However,
the same technique can't be applied across multiple invocations, since
there's no reason to keep the DFU buffer allocated while DFU isn't
running. This patch addresses the root-cause a bit more directly.
This problem highlights some of the disadvantages of dynamic allocation
and deferred probing of devices.
This patch isn't checkpatch-clean, since it conforms to the existing
coding style in dlmalloc.c, which is different to the rest of U-Boot.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
829520: Code bounded by indirect conditional branch might corrupt
instruction stream.
Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect
Predictor.
833471: VMSR FPSCR functional failure or deadlock.
Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This adds ethernet, TFTP support for PIC32MZ[DA] Starter Kit. Also
custom environment variables/scripts are added to help boot from network.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
This driver implements MAC and MII layer of the ethernet controller.
Network data transfer is handled by controller internal DMA engine.
Ethernet controller is configurable through device-tree file.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Enable MMC, SDHCI, FAT_FS support for PIC32MZ[DA] StarterKit.
Also add custom scripts, rules to boot Linux from microSD card.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
This driver implements platform specific glue and fixups for
PIC32 internal SDHCI controller.
Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com>
Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This adds support for Microchip PIC32MZ[DA] StarterKit board
based on a PIC32MZ[DA] family of microcontroller.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This adds PIC32 UART controller support based on driver model.
Signed-off-by: Paul Thacker <paul.thacker@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In PIC32 GPIO controller is part of PIC32 pin controller.
PIC32 has ten independently programmable ports and each with multiple pins.
Each of these pins can be configured and used as GPIO, provided they
are not in use for other peripherals.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
In PIC32 pin-controller is a combined gpio-controller, pin-mux and
pin-config module. Remappable peripherals are assigned pins through
per-pin based muxing logic. And pin configuration are performed on
specific port registers which are shared along with gpio controller.
Note, non-remappable peripherals have default pins assigned thus
require no muxing.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers
and dividers capable of supplying clock to various controllers
on or off-chip.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Rather than passing the I/O port base address to the Super I/O code,
switch it to using outb such that it makes use of the I/O port base
address automatically.
Drop the extern keyword to satisfy checkpatch whilst here.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Set the I/O port base earlier, from board_early_init_f, in preparation
for it being used by the serial driver.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
The existing mips_io_port_base variable isn't suitable for use early
during boot since it will be stored in the .data section which may not
be writable pre-relocation. Fix this by moving the I/O port base address
into struct arch_global_data. In order to avoid adding this field for
all targets, make this dependant upon a new Kconfig entry
CONFIG_DYNAMIC_IO_PORT_BASE. Malta is the only board which sets a
non-zero I/O port base, so select this option only for Malta.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
CONF_SLOWDOWN_IO is never set for any target, so remove the dead code in
the SLOW_DOWN_IO macro. This is done in preparation for changes to
mips_io_port_base which can be avoided in this path by removing it
entirely.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
This patch makes sure that the flush/invalidate_dcache_range() functions
can handle corner-case calls like this -- invalidate_dcache_range(0, 0, 0);
This call is valid and is happily produced by USB EHCI code for example.
The expected behavior of the cache function(s) in this case is that they
will do no operation, since the size is zero.
The current implementation though has a problem where such invocation will
result in a hard CPU hang. This is because under such conditions, where the
start_addr = 0 and stop = 0, the addr = 0 and aend = 0xffffffe0 . The loop
will then try to iterate over the entire address space, which in itself is
wrong. But iterating over the entire address space might also hit some odd
address which will cause bus hang. The later happens on the Atheros MIPS.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Fix 32 vs 64 bit load/store instructions. Access CP0_WATCHHI as
32 Bit register. Use 64 Bit register access for clearing gd_data
and copying U-Boot.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Argument boot_flags of board_init_f() should be set to 0 as
$a0 may be utilized in lowlevel_init() or mips_cache_reset()
or previous stage boot-loader.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Fix the lost dts info when merging patches.
Fix DSPI node for 'commit e0579a5852 ("armv8/ls1043aqds: add DSPI
support")' and QSPI node for 'commit 166ef1e90c ("armv8/ls1043aqds:
add QSPI support in SD boot")'.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Update printf with dpbp_exit to match with previous function call.
Signed-off-by: Itai Katz <itai.katz@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
All fields of struct dprc_cfg are not being configured while creating
child container. "Not" configured fields are assumed to be 0.
So memset dprc_cfg before configuring the fields.
Signed-off-by: Itai Katz <itai.katz@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
