Commit graph

13 commits

Author SHA1 Message Date
Peng Fan
adc0fabfd9 imx:mx6sxsabresd support qspi AHB read
Add CONFIG_SYS_FSL_QSPI_AHB in header file to enable AHB in driver.
In order to count the time, add CONFIG_CMD_TIME.

Using AHB read can improve the the read speed about 30%.

AHB read:
=> time sf read 0x8f800000 0 100000
SF: 1048576 bytes @ 0x0 Read: OK
time: 0.174 seconds

=> time sf read 0x8f800000 1000000 100000
SF: 1048576 bytes @ 0x1000000 Read: OK
time: 0.174 seconds

IP read:
=> time sf read 0x8f800000 0 100000
SF: 1048576 bytes @ 0x0 Read: OK
time: 0.227 seconds

=> time sf read 0x8f800000 1000000 100000
SF: 1048576 bytes @ 0x1000000 Read: OK
time: 0.227 seconds

Note:
Quad read is not supported in driver, now. In my side, using AHB and Quad read
can achieve about 16MB/s. Anyway, I have plan to reimplement the driver using
DTB and DM, then make the code cleaner and more feature can be added.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-09 00:03:28 +05:30
Peng Fan
d87cbeccc5 mx6sxsabresd: support qspi flash bigger than 16MB
mx6sxsabresd revb board uses 32MB qspi flash, reva board uses 16MB qspi
flash. Currently, the default supported platform is revb board.

If want to configure for reva board, just define CONFIG_MX6SX_SABRESD_REVA
in mx6sxsabresd.h to support reva qspi flashes whose size is 16MB.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-07 12:25:05 +05:30
Peng Fan
fad7d735a0 imx:mx6sxsabresd add qspi support
Configure the pad setting and enable qspi clock to support qspi
flashes access.

Add QSPI related macro in configuration header file.

Note:
mx6sxsabresd Revb board, 32M flash is used, but in header file,
CONFIG_SPI_FLASH_BAR is not defined, and we still use SZ_16M.
The LUT initialization qspi_set_lut function uses 32BIT addr,
however CONFIG_SPI_FLASH_BAR  and 24BIT addr should be used to
access bigger than 16MB size flash, and BRRD/BRWR should also
be supported. Future patches will fix this.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-31 14:52:32 +05:30
Tom Rini
fc9b0b8043 Merge branch 'master' of git://git.denx.de/u-boot-usb
Conflicts:
	board/freescale/mx6sxsabresd/mx6sxsabresd.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-12-11 18:40:49 -05:00
Fabio Estevam
4b16fd2286 mx6sxsabresd: Add thermal support
Add thermal support so that the temperature of the chip can be displayed on
boot:

U-Boot 2015.01-rc1-18268-g1366c05-dirty (Nov 25 2014 - 13:02:42)

CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
CPU:   Temperature 50 C

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-12-01 10:20:18 +01:00
Ye.Li
d0fbca2a3a imx: mx6sxsabresd: Add board support for USDHC2 and USDHC3
Add full support for USDHC2, USDHC3, USDHC4 on mx6sx sabresd board.
The default boot socket is USDHC4, so the MMC environment device and
mmcdev variable are set to this device.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-11-20 10:45:14 +01:00
Peng Fan
a511a3e0e8 imx:mx6sxsabresd add board level support for usb
Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode

There are two usb port on mx6sxsabresd board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core <---> board otg port
otg2 core <---> board host port
In order to make host port work, board_usb_phy_mode return USB_INIT_HOST
to make host port work in HOST mode.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye Li <B37916@freescale.com>
2014-11-14 20:58:19 +01:00
Fabio Estevam
fb6f86c411 mx6sxsabresd: Fix PCI reset and power GPIO assignments
PERST_GPIO and POWER_GPIO are currently swapped.

Fix the GPIO assignments as per the board schematics.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-10-06 17:06:23 +02:00
Peng Fan
152adee1b6 imx:mx6sxsabresd: change CONFIG_SYS_FSL_ESDHC_ADDR
Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC4_BASE_ADDR which is used
in board_mmc_init.

If board_mmc_init failed, cpu_mmc_init->fsl_esdhc_mmc_init will use
CONFIG_SYS_FSL_ESDHC_ADDR to initialize sdhc. So set this macro to
correct value.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2014-09-16 13:33:46 +02:00
Fabio Estevam
c860eed176 mx6sxsabresd: Add PCI support
Tested with an Intel Wireless PCI 7260HMW card:

U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)

CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
Reset cause: WDOG
Board: MX6SX SABRE SDB
I2C:   ready
DRAM:  1 GiB
MMC:   FSL_SDHC: 0
  00:01.0     - 16c3:abcd - Bridge device
   01:00.0    - 8086:08b1 - Network controller

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-09-09 17:24:49 +02:00
Fabio Estevam
d145878d59 mx6sxsabresd: Add Ethernet support
mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031.

Add support for one FEC port initially.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20 13:15:23 +02:00
Fabio Estevam
fa8cf3176c mx6sxsabresd: Add PFUZE100 PMIC support
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-23 12:25:40 +02:00
Fabio Estevam
14a1613140 mx6sx: Add initial support for mx6sxsabresd board
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-10 15:29:16 +02:00