Commit graph

334 commits

Author SHA1 Message Date
Tom Rini
82d72a1b99 Merge branch 'master' of git://git.denx.de/u-boot-net 2016-01-28 18:42:10 -05:00
Shaohui Xie
d8877e6f8c net: phy: implements probe for Cortina phy
Cortina phy cannot support soft reset, this commit implements probe
for Cortina PHY to tell phylib to skip phy soft reset by setting
PHY_FLAG_BROKEN_RESET in flags.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 13:20:31 -06:00
Shaohui Xie
ddcd1f3084 net: phy: introduce a quirk PHY_FLAG_BROKEN_RESET
Current driver always performs a phy soft reset when connecting the phy
device, but soft reset is not always supported by a phy device, so
introduce a quirk PHY_FLAG_BROKEN_RESET to let such a phy device to skip
soft reset. This commit uses 'flags' of phy device structure to store the
quirk.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 13:20:30 -06:00
Dinh Nguyen
ff7bd212cb net: phy: micrel: fix divisor value for KSZ9031 phy skew
The picoseconds to register value divisor(ps_to_regval) should be 60 and not
200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct
divisor because the 4-bit skew values are defined from 0x0000(-420ps) to
0xffff(480ps), increments of 60.

For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7.
With the previous divisor of 200, it would result in 0x2, which represents a
-300ps delay.

With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with
1Gb ethernet.

References:
http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 13:20:30 -06:00
Alexandre Messier
1f9e672c79 net: phy: Use 'autoneg' flag from phydev
Use the 'autoneg' flag available in phydev when checking if
autoneg is in use.

The previous implementation was checking directly in the PHY
if autoneg was supported. Some PHYs will report that autoneg
is supported, even when it is disabled. Thus it is not possible
to use that bit to determine if autoneg is currently in use or
not.

Signed-off-by: Alexandre Messier <amessier@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 13:20:29 -06:00
Alexandre Messier
53b0c38c7a net: phy: Set ANRESTART in setup_forced
When configuring a PHY in fixed (forced) link mode, in order for
the changes to be applied, either one of these conditions must
be triggered:
	1- PHY is reset
	2- Autoneg is restarted
	3- PHY transitions from power-down to power-up

Neither of these is currently done, so effectively the fixed link
configuration is not applied in the PHY.

Fix this by setting the Autoneg restart bit.

Signed-off-by: Alexandre Messier <amessier@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 13:20:28 -06:00
Alexandre Messier
79e3efd5e5 net: phy: micrel: Disable B_CAST on config
Micrel PHYs KSZ8021/31 and KSZ8081 have a feature where MDIO address 0
is considered as a broadcast address; the PHY will respond even if it
is not its configured (pinstrapped) address. This feature is enabled
by default.

The Linux kernel disables that feature at initialisation, but not
before it probes the MDIO bus. This causes an issue, because a PHY
at address 3 will be discovered at addresses 0 and 3, but will then
only respond at address 3. Because Linux attaches the first PHY it
discovers on 'eth0', it will attach the PHY from address 0, which
will never answer again.

Fix the issue by disabling the broadcast feature in U-Boot, before
Linux is started.

Signed-off-by: Alexandre Messier <amessier@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 13:20:21 -06:00
Alexey Brodkin
b18acb0a11 drivers/net/phy: introduce phy_set_supported()
This new function will allow MAC drivers to override supported
capabilities of the phy. It is required when MAC cannot handle all
speeds supported by phy.

For example phy supports up-to 1Gb connections while MAC may only work
in modes up to 100 or even 10 Mbit/sec.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:32:42 -06:00
Sascha Hauer
44bc317487 net: phy: genphy: Allow overwriting features
of_set_phy_supported allows overwiting hardware capabilities of
a phy with values from the devicetree. This does not work with
the genphy driver though because the genphys config_init function
will overwrite all values adjusted by of_set_phy_supported. Fix
this by initialising the genphy features in the phy_driver struct
and in config_init just limit the features to the ones the hardware
can actually support. The resulting features are a subset of the
devicetree specified features and the hardware features.

This is a copy of the patch from Linux kernel, see
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=c242a47238fa2a6a54af8a16e62b54e6e031d4bc

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:32:41 -06:00
Florian Fainelli
bbdcaff12a net: phy: ensure Gigabit features are masked off if requested
When a Gigabit PHY device is connected to a 10/100Mbits capable Ethernet
MAC, the driver will restrict the phydev->supported modes to mask off
Gigabit. If the Gigabit PHY comes out of reset with the Gigabit features
set by default in MII_CTRL1000, it will keep advertising these feature,
so by the time we call genphy_config_advert(), the condition on
phydev->supported having the Gigabit features on is false, and we do not
update MII_CTRL1000 with updated values, and we keep advertising Gigabit
features, eventually configuring the PHY for Gigabit whilst the Ethernet
MAC does not support that.

This patches fixes the problem by ensuring that the Gigabit feature bits
are always cleared in MII_CTRL1000, if the PHY happens to be a Gigabit
PHY, and then, if Gigabit features are supported, setting those and
updating MII_CTRL1000 accordingly.

This is a copy of patch from Linux kernel, see
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=5273e3a5ca94fbeb8e07d31203069220d5e682aa

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:31:30 -06:00
Stefan Agner
a058052c35 net: phy: do not read configuration register on reset
When doing a software reset, the reset flag should be written without
other bits set. Writing the current state will lead to restoring the
state of the PHY (e.g. Powerdown), which is not what is expected from
a software reset.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Michael Welling <mwelling@ieee.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:22:00 -06:00
Michal Simek
0179063273 net: phy: ti: Enable automatic crossover mode
Enable automatic crossover cable detection.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-27 15:55:54 +01:00
Stephen Warren
7c4213f6a5 block: pass block dev not num to read/write/erase()
This will allow the implementation to make use of data in the block_dev
structure beyond the base device number. This will be useful so that eMMC
block devices can encompass the HW partition ID rather than treating this
out-of-band. Equally, the existence of the priv field is crying out for
this patch to exist.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-13 21:05:18 -05:00
Fabio Estevam
d584c68ce0 phy: atheros: Use ar8035_config for AR8031
Commit 08ad9b068a (" ar8031: modify the config func of ar8031 to
ar8021_config") selected 'ar8021_config' as the configuration function
for AR8031.

The correct would be to use 'ar8035_config' instead as AR8031/AR8035
have the same programming model and even share the same phy driver
in the linux kernel: drivers/net/phy/at803x.c.

Tested on a mx6qsabresd and wandboard, which now can work without
any PHY setup code in the board files.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-07 17:46:47 +01:00
Marek Vasut
22854bda80 net: phy: micrel: Configure KSZ9021/KSZ9031 skew from OF
Add code to process the KSZ9021/KSZ9031 OF props if they are present
and configure skew registers based on the information from the OF.
This code is only enabled if the DM support for ethernet is also
enabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

V2: - Implement struct ksz90x1_reg_field to describe the skew register
      fields more accurately.
    - Fix RXDV/TXEN skew register default value and offset.
2015-12-20 03:36:49 +01:00
Shaohui Xie
f8642ba6dd net: phy: added aquantia PHY AQR405 support
The phy can share driver with other aquantia PHYs, so we only
add PHY ID.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:13 -08:00
Simon Glass
24b852a7a2 Move console definitions into a new console.h file
The console includes a global variable and several functions that are only
used by a small subset of U-Boot files. Before adding more functions, move
the definitions into their own header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:50 -07:00
Edgar E. Iglesias
721aed7912 net: phy: Add support for Texas Instruments DP83867
Code is taken from Linux kernel driver (v4.2).

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-11-19 13:09:21 +01:00
Vincent BENOIT
5ea667ea2f pengwyn: nand and ethernet fixes
-> Add National instrument ethernet transceiver configuration used (DP83848)
-> Change cpsw slave phy address
-> modify nand configuration to use the correct ECC and correct nand features
2015-11-12 18:13:19 -05:00
Bin Meng
17ecfa9b45 net: phy: Test previous phydev->dev against new mac dev
In phy_connect_dev(), if the phy device has an accociated mac device
before, a warning message will be printed. But we should test the
old device against the new one, if they are actually the same one,
don't print the warning message.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-10-29 14:05:49 -05:00
Bin Meng
3e1949d774 net: phy: Change to print all phys that are not found
In get_phy_device_by_mask(), when no phy is found, currently we only
print a message to show the first phy address that is not found. But
this is not always the case as multiple phys can be specified by
phy_mask. Change to print all phys that are not found, and to reduce
the console boot log, change to use 'debug' instead of 'printf'.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-10-29 14:05:49 -05:00
Bin Meng
0132b9ab6e net: phy: Don't create phy device when there is no phy
In get_phy_device_by_mask(), when no phy is found, we should not
create any phy device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-10-29 14:05:48 -05:00
Sylvain Rochet
4f485150cf net: phy: micrel: disable NAND-tree for KSZ8051
NAND-tree is used to check wiring between MAC and PHY using NAND gates
on the PHY side, hence the name.

NAND-tree initial status is latched at reset by probing the IRQ pin.
However some devices are sharing the PHY IRQ pin with other peripherals
such as Atmel SAMA5D[34]x-EK boards when using the optional TM7000
display module, therefore they are switching the PHY in NAND-tree test
mode depending on the current IRQ line status at reset.

This patch ensure PHY is not in NAND-tree test mode only for the Micrel
KSZ8051 PHY used by Atmel. There are other Micrel PHY affected but I
doubt they are used on such weird hardware design.

Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-10-29 14:05:48 -05:00
Sylvain Lemieux
6617f87668 net: phy: micrel: add support for KSZ8021RNL & KSZ8031RNL
This patch adds support for Micrel KSZ8021RNL & KSZ8031RNL.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-10-29 14:05:46 -05:00
Mugunthan V N
26d3acdab8 net: phy: on phy device create do not initialize link to 1
Currently when phy device is created the link variable is
initialized to 1 which denoted phy link is already up. On a power
reset there is no issue as phy status register link status will
not be set, so phy auto negotiate will be started. But when a cpu
reset is issued (ex: dra72x-evm) phy's link status bit is already
set which leads to assume that link is already setup in
genphy_update_link() initial check which results in ehternet not
working. So do not assume that link is already up and on phy
device create set link to zero. This is verified on dra72x-evm.

Reported-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-09-29 16:01:29 -05:00
Prabhakar Kushwaha
4c2620dd71 net: phy/vitesse: Add support for VSC8584 phy
Add support of VSC8584 phy placed on new QSGMII/SGMII ethernet riser cards
used on LS2085QDS platforms.

Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 21:38:39 -05:00
Jiandong Zheng
1b564cecc3 net: phy: broadcom: Add BCM Cygnus PHY
Add Ethernet PHY for BCM Cygnus SoC

Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-08-11 13:49:17 -05:00
Jörg Krause
59370f3fcd net: phy: delay only if reset handler is registered
With commit e3a77218a2 the MII bus is only
reset if a reset handler is registered. If there is no reset handler there
is no need to wait for a device to come out of the reset.

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
2015-08-11 13:48:25 -05:00
Jörg Krause
2c171a2a5f net: phy: fix data type of phy_id
phy_id is declared as u32 in create_phy_by_mask and in struct phy_device.

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
2015-08-11 13:47:15 -05:00
Clemens Gruber
8396d0ab8b net: Add support for Marvell 88E1510 PHY
Support the 88E1510 PHY which is very similar to the 88E1518.
I also set the INTn output and configured the LEDs.

Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Hao Zhang <hzhang@ti.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-08-11 13:29:01 -05:00
Clemens Gruber
90a94ef652 net: Improve 88E151x PHY initialization
- The EEE fixup magic should also be enabled for RGMII
- Improved comments

Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Hao Zhang <hzhang@ti.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-08-11 13:28:59 -05:00
Shengzhou Liu
90712741c9 net/phy: set led for rtl8211f phy
Initialize LCR rigister to configure
green LED for Link, yellow LED for Active.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2015-08-11 13:20:34 -05:00
Michal Simek
abbfcbe58e net: phy: Add support for all targets which requires MANUAL_RELOC
Targets with CONFIG_NEEDS_MANUAL_RELOC do not use REL/RELA
relocation (mostly only GOT) where functions aray are not
updated. This patch is fixing function pointers passed to phy_register
function.
This patch was tested on Microblaze architecture.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-05-19 13:33:21 -05:00
Shengzhou Liu
793ea94770 net/phy: refactor RTL8211F initialization
RTL8211F needs to enalbe TXDLY for RGMII during
phy initialization, so move it to rtl8211f_config
for early initialization.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-05-19 13:33:21 -05:00
Shengzhou Liu
3d6af748eb net/phy: Add support for realtek RTL8211F
RTL8211F has different registers from RTL8211E.
This patch adds support for RTL8211F PHY which
can be found on Freescale's T1023 RDB board.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-05-19 13:33:20 -05:00
pankaj chauhan
8bb065630f net/phy/cortina: Fix compilation warning
Fix comilation warning which is emitted when
firmware address is more than 32 bit.

Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 08:55:57 -07:00
Shengzhou Liu
5707d5ffd4 net/phy: fixup for get_phy_id
commit 3c6928fd7b "net: phy: fix warnings with W=1" caused
some PHYs(e.g. CS4315/CS4340) not working. This patch fixes the
warning and make those special PHYs working as well.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2015-04-20 17:57:13 -05:00
Luca Ellero
c6a40f6e51 net: phy: micrel: add support for KSZ8081MNX
This patch adds a support for KSZ8081MNX in MII mode.

Signed-off-by: Luca Ellero <luca.ellero@brickedbrain.com>
Acked-by: Pavel Machek <pavel@denx.de>
2015-04-20 17:57:12 -05:00
Codrin Ciubotariu
3cee138892 net: phy: realtek: Disable interrupt on Realtek Ethernet PHY drivers
Some Realtek Ethernet PHYs, like RTL8211D(G/N) and RTL8211E(G), have
interrupts enabled by default. If the interrupt is not treated later by
the OS and the PHY's interrupt line is enabled and shared with other
interrupts, the system will get an interrupt storm. This patch disables
the interrupt for PHY devices that use one of the current Realtek
Ethernet PHY drivers. Some of Realtek Ethernet PHYs, such as RTL8211B(L)
have the interrupt masked. In this case, the functionality of the PHY
should not be afected since this patch brings INER and INSR registers to
their default values.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-04-20 17:57:11 -05:00
Simon Glass
c74c8e6651 dm: net: Adjust PHY interface to work with CONFIG_DM_ETH
When driver model is used for Ethernet a few functions are passed a udevice
instead of an eth_device. Also add a function to find a PHY type given its
name. This will be used to decode the device tree node.

Finally, put a phy_interface field in struct eth_pdata since this is an
important part of the platform data for Ethernet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-04-18 11:11:36 -06:00
Philippe De Muyter
b7a5b08438 net: phy: micrel: add support for KSZ8895 switch in SMI mode
This patch adds a phy driver for the Micrel KSZ8895 switch.  As the SoC MAC
is directly connected to the switch MAC the link to the switch is always up.

But the KSZ8895 switch can be hardwired in three configuration modes :
- not configurable with eventually an eeprom-stored configuration
- configurable by the mdio/mdc connection (SMI protocol)
- configurable by a SPI connection.

In not configurable mode, the switch starts automatically, but in the
other modes, it must be started programmatically, by writing 1 in
configuration register 1.
We only support the not configurable and mdio/mdc (aka SMI) modes here.

Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2015-01-30 15:55:00 -06:00
Shaohui Xie
f7c38cf827 phylib: add support for aquantia PHYs
This patch supports AQ1202, AQ2104, AQR105 PHY.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-16 09:32:11 -08:00
Shengzhou Liu
c18fc2c960 net/phy: enable serdes auto-negotiation for vsc8514 phy
VSC8514 QSGMII PHY requires enabling auto-negotiation,
otherwise it wouldn't work.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
9b18e5199e net/phy: Add support for CS4315/CS4340 PHY
Add support for Cortina CS4315/CS4340 10G PHY.
- This driver loads CS43xx firmware from NOR/NAND/SPI/SD device
  to initialize Cortina PHY.
- Cortina PHY has non-standard offset of PHY ID registers, thus
  we define own get_phy_id() to override default get_phy_id().
- To define macro CONFIG_PHY_CORTINA will enable this driver.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:11 -08:00
Hao Zhang
35fa0dda0c net: phy: marvell: add errata w/a for 88E151* chips
As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/88E1514
Rev A0, Errata Section 3.1 Marvell PHY has an errata which requires
that certain registers get written in order to restart
autonegotiation.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2014-11-06 11:04:38 -05:00
Tom Rini
5aa7bece10 Merge branch 'master' of git://git.denx.de/u-boot-ti 2014-10-27 09:05:43 -04:00
Jeroen Hofstee
3c6928fd7b net: phy: fix warnings with W=1
get_phy_id is marked weak but has no protype nor a
strong version, just make it static. Use __weak for
board_phy_config.

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-10-25 07:01:59 -04:00
Khoronzhuk, Ivan
adc9a79f3f net: phy: print a number of phy that is not found
In case when several Ethernet ports are supported it's
convenient to see the number of phy that is not found.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:28 -04:00
Pavel Machek
58ec63d6bc net: phy: Cleanup drivers/net/phy/micrel.c
Old saying says that more than three exclamation marks in a row are
sign of mental disease. Cleanup micrel.c.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Chin Liang See <clsee@altera.com>
2014-10-06 17:36:40 +02:00
Masahiro Yamada
368b4d2b49 drivers: net: remove dead drivers
The following configs are not defined at all:

 - CONFIG_INCA_IP_SWITCH
 - CONFIG_PBL2800_ETHER
 - CONFIG_PHY_ICPLUS

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21 12:01:11 -04:00
maxin.john@enea.com
79e86ccb37 vitesse: remove duplicated argument to ||
Remove the duplicated argument to || check

Signed-off-by: Maxin B. John <maxin.john@enea.com>
2014-08-09 11:17:02 -04:00
Cormier, Jonathan
08be2836df phy: fix create_phy_by_mask for when its given an actual search mask
get_phy_id returns -EIO when it can't read from a phy at a given addr.  This would cause
create_phy_by_mask to return prematurely before it had tested the other addresses in the provided mask.

Example usage:
Replace
    phydev = phy_connect(bus, phy_addr, dev, phy_if)
with
    phydev = phy_find_by_mask(bus, phy_mask, phy_if)
    if (phydev)
	phy_connect_dev(phydev, dev);

Signed-off-by: Cormier, Jonathan <jcormier@criticallink.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
2014-06-05 14:44:56 -04:00
Chunhe Lan
ffc8667acf net: phy/vitesse: Add support for VSC8664 phy module
This patch adds support for VSC8664 PHY module which can
be found on Freescale's T4240RDB boards.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:05 -05:00
Shengzhou Liu
597fe041a8 net/phy: enable get_phy_id redefinable
As some PHYs have non-standard PHY ID registers, PHY Id can't
be read correctly by current get_phy_id function, so we enable
get_phy_id redefinable to permit specific PHY driver having own
specific get_phy_id function.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-05-12 15:19:45 -04:00
Xiaobo Xie
02aa4c5388 AR8035/phy: Enable autonegotiation function for ar8035
Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before,
but used "if (phydev->supported & SUPPORTED_Autoneg)" now.
So assign "phydev->supported" to "phydev->drv->features" for ar8035
to enable autonegotiation. Then removed the genphy_config_aneg() function.

Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
2014-05-12 15:19:45 -04:00
Zhao Qiang
08ad9b068a ar8031: modify the config func of ar8031 to ar8021_config
ar8031 has the same config steps with ar8021, so change its
config func to ar8021_config instead of genphy_config.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:53 -07:00
Codrin Ciubotariu
44afbbc0f0 net/phy: Fix PHY id for VSC8514
In the current Datasheet for VSC8514 there is a mistake, saying that
the PHY id is 0x70570. The real value in the identifier registers is
0x70670. Linux PHY driver uses 0x70670 also.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Haijun.Zhang
dc116bd6c4 net/phy: Correct AR8021 phy_mask
There was wrong phy_mask for AR8021 device,
so the AR8021 can't be probed correctly.
Changed it from 0x4fffff to 0x4ffff0.

Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
2014-03-07 10:59:06 -05:00
Tom Rini
a7e8c15f71 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
With this, fixup a trivial build error of get_effective_memsize needing
to be updated in the new board/freescale/p1010rdb/spl.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-02-25 13:55:49 -05:00
Zhao Qiang
e0d809647f ar8031/8033/phy:enable autonegotiation for ar8031/8033
Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before
while "if (phydev->supported & SUPPORTED_Autoneg)" now.
So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033
to enable autonegotiation.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-02-24 15:23:41 -08:00
Heiko Schocher
9137d19bdd net, phy: atheros ar803x bug
commit 626ee1e3 "phylib: update atheros ar803x phy"

leads in failing ethernet on the pxm2 board.

Calling genphy_config() instead of ar8021_config(),
which seems for ar8021 phys not ar803x phys, make
it working again.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
2014-02-19 10:47:33 -05:00
Fabio Estevam
f66e3ded61 net: phy: atheros: Fix the masks for AR8031/8035
Use the same masks as used in the kernel:
https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/drivers/net/phy/at803x.c?id=refs/tags/v3.12.6

With such changes Ethernet is functional on hummingboard solo.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Marek Vasut <marex@denx.de>
Patch: 306640
2014-01-14 14:00:41 -06:00
David Dueck
f27f3b5266 phy: Use general phy code for smsc lan8720a
Signed-off-by: David Dueck <davidcdueck@googlemail.com>
2013-11-22 17:03:20 -06:00
David Dueck
3a530d1b3e phy: Use supported field during autonegotiation
The current code incorrectly detects gigabit capabilities for some
100Mbit/s phys. (lan8720a)

Signed-off-by: David Dueck <davidcdueck@googlemail.com>
2013-11-22 17:03:20 -06:00
Fabio Estevam
e003ba5bfc net: phy: atheros: Fix masks for AR8035 and AR8021
The masks were ignoring the last 4 bits which didn't allow detection differences
between the ar8031 and ar8035.

Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Patch: 288018
2013-11-22 17:03:18 -06:00
Chunhe Lan
3177457853 net/phy: Fix the phy id mask of AR8031
The both AR8031 and AR8035 belong to Atheros 803x serial PHY.
So the phy id mask of AR8031 is the same to the phy id mask
of AR8035. The right mask value is 0x4fffff.

This patch has been tested on the P1010 and P1023.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Patch: 287748
2013-11-22 17:03:18 -06:00
Heiko Schocher
dfcaa61c33 net, phy: fix AR8031 phy_mask
AR8035 driver will be never applied because of wrong mask for
AR8031 driver. Fix this.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Patch: 276944
2013-11-22 16:50:54 -06:00
Stefano Babic
9ced16fefa net: add function to read/write extended registers in Micrel Phy
Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-11-22 16:50:52 -06:00
Stefano Babic
e8194d58bd net: fix mask for phy Micrel KSZ9031
Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-11-22 16:50:51 -06:00
Bhupesh Sharma
4220504767 net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected
The 'get_phy_driver' code in 'drivers/net/phy/phy.c' uses the following
method to determine which driver is to be loaded for a particular PHY
module:

list_for_each(entry, &phy_drivers) {
	drv = list_entry(entry, struct phy_driver, list);
	if ((drv->uid & drv->mask) == (phy_id & drv->mask))
		return drv;
}

This means that a drv->mask of 0xfffff0 will return incorrect phy driver
for the logic above, even if the drv->uid is anything other than
something ending with a 0x0.

For e.g. if the RTL8211E drv->uid is 0x1cc915 and drv->mask is 0xffffff
and the RTL8211B drv->uid is 0x1cc910 and drv->mask is 0xffffff0, then
the phy driver selected will always be RTL8211B even though the
underlying phy connected on the board is a 8211E module.

This patch fixes this issue.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
2013-11-22 16:50:51 -06:00
Arpit Goel
e97a78cfed net: phy/vitesse: Add support for VSC8514 phy module
This patch adds support for VSC8514 PHY module which can be
found on Freescale's T1040RDB boards.

Signed-off-by: Arpit Goel <B44344@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
2013-11-22 16:50:50 -06:00
Shengzhou Liu
626ee1e32e phylib: update atheros ar803x phy
As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the
common driver. Currently AR8031_driver didn't work for AR8033,
hence updated it to have it work on AR8031/AR8033.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2013-11-22 14:39:54 -06:00
Masahiro Yamada
e32459e24a drivers: net: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 13:22:13 -04:00
Robert P. J. Day
1bce2aeb6f Cosmetic: Fix a number of typos, no functional changes.
Fix various misspellings of things like "environment", "kernel",
"default" and "volatile", and throw in a couple grammar fixes.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2013-09-20 10:30:54 -04:00
Bhupesh Sharma
c624d168bf net: phy/realtek: Add support for RTL8211DN and RTL8211E phy modules
This patch adds support for Realtek PHY modules RTL8211DN and
RTL8211E (variants: RTL8211E-VB-CG, RTL8211E-VL-CG, RTL8211EG-VB-CG),
which can be found on Freescale's T1040RDB boards.

To make the driver more generic across 8211 family, a generic name 8211x
is added for macros and function names.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-19 12:34:19 -05:00
Fabio Estevam
25634210af phy: smsc: LAN8710/8720 are not Gbit PHYs
LAN8710/8720 are 10/100 Mbps PHYs, so fix the '.features' field.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-08-19 12:34:18 -05:00
Heiko Schocher
f6d1f6e4a5 net, phy, cpsw: fix gigabit register access
accessing a lan9303 switch with the cpsw driver results in wrong
speed detection, as the switch sets the BMSR_ERCAP in BMSR
register, and follow read of the MII_STAT1000 register fails, as
the switch does not support it. Current code did not check,
if a phy_read() fails ... fix this.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-30 09:21:42 -04:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Fabio Estevam
9a5dad2393 net: phy: Set SUPPORTED_1000baseX_Half flag in ESTATUS_1000_XHALF case
Commit de1d786e (add support for Xilinx 1000BASE-X phy (GTX)) introduced the
checking for ESTATUS_1000_XHALF, but it incorrectly sets the
SUPPORTED_1000baseX_Full flag in this case.

Set the SUPPORTED_1000baseX_Half flag instead.

Acked-by: Charles Coldwell <coldwell@gmail.com>
Reviewed-By: Sascha Silbe <t-uboot@infra-silbe.de>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-07-19 17:12:20 -04:00
Sascha Silbe
9ba30f6bc2 phy: fix 10/100Mbps operation on 1Gbps-capable links
de1d786 [add support for Xilinx 1000BASE-X phy (GTX)] introduced a
check for the extended status register in order to support
1Gbps-capable PHYs that don't have the 1000BASE-T registers. Since
Extended Status only indicates what the PHY (i.e. the local side) is
capable of, this broke communication with non-1Gbps peers.

Only check the extended status if the 1000BASE-T registers are
actually missing so we don't end up setting speed to 1Gbps even though
the previous test (for the combination of local and peer support for
1Gbps) already indicated we can't do 1Gbps with the current peer.

Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2013-07-19 17:12:16 -04:00
Heiko Schocher
433a2c5325 phylib: add atheros ar803x phy
add atheros ar803x phy, used on the upcoming siemens boards.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
2013-06-24 19:11:17 -05:00
Heiko Schocher
96d0b9e100 phylib: add natsemi dp83630 phy
add natsemi dp83630 phy, used on the upcoming siemens boards.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
2013-06-24 19:11:17 -05:00
SARTRE Leo
42a7cb50a9 net: phy: supplement support for Micrel's KSZ9031
Add function ksz9031_phy_extended_write and ksz9031_phy_extended_read

Signed-off-by: Leo Sartre <lsartre@adeneo-embedded.com>
2013-06-24 19:11:16 -05:00
Xie Xiaobo
6027384a69 phylib: Add Atheros AR8035 GETH PHY support
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
2013-06-24 19:11:14 -05:00
Charles Coldwell
de1d786edf add support for Xilinx 1000BASE-X phy (GTX)
commit 39695029bc15041c809df3db4ba19bd729c447fa
Author: Charles Coldwell <coldwell@ll.mit.edu>
Date:   Tue Feb 19 08:27:33 2013 -0500

    Changes to support the Xilinx 1000BASE-X phy (GTX/MGT)

Signed-off-by: Charles Coldwell <coldwell@ll.mit.edu>
2013-06-24 19:11:13 -05:00
David Andrey
62d7dba7be PHY: micrel.c: add support for KSZ9031
Add support for Micrel PHY KSZ9031 in phylib,
including small rework for KSZ9021 to avoid
code duplication

Signed-off-by: David Andrey <david.andrey@netmodule.com>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Joe Herschberger <joe.hershberger@gmail.com>
Cc: Andy Fleming <afleming@freescale.com>
Acked-by: Stefan Roese <sr@denx.de>
2013-06-24 19:11:13 -05:00
Sebastian Hesselbarth
aeceec0d0e NET: phy: add 88E1310 PHY initialization
This adds PHY initialization for Marvell Alaska 88E1310 PHY.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2013-06-24 19:10:14 -05:00
Yegor Yefremov
0fae25089d net: add ICPlus PHY driver
The driver code was taken from Linux kernel source:
drivers/net/phy/icplus.c

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
2013-06-24 19:07:32 -05:00
Yegor Yefremov
e2043f5c27 phy: export genphy_parse_link()
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
2013-06-24 19:07:32 -05:00
Albert ARIBAUD
a19b0dd62d Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	common/cmd_fpga.c
	drivers/usb/host/ohci-at91.c
2013-05-30 14:45:06 +02:00
Shaohui Xie
d54097b6c1 net/phy: fix select line for TN80xx
TN80xx has same PHY ID as TN2020, but it needs different setting to register
30.93 which used to select line, so we read register 30.32 which has
bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2,
for TN80xx we will get 5 or 4.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:09 -05:00
Shaohui Xie
7794b1a7e6 net/phy: add VSC8574 support
The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes
interfaces for quad-port dual media capability. This driver supports SGMII
and QSGMII MAC mode. For now SGMII mode is tested.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:13:25 -05:00
Matt Porter
f485c8a35b phy: add support for ET1011C phys
Adds an ET1011C PHY driver which is derived from the
Linux kernel PHY driver (drivers/net/phy/et1011c.c)
from the v3.9-rc2 tag. Note that an errata workaround
config option is implemented to allow for TX_CLK to be
enabled even when gigabit mode is negotiated. This
workaround is used on the PG1.0 TI814X EVM.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-10 08:25:54 -04:00
Michal Simek
1415107e46 net: phy: Define Marvell 88e1518 phy
This phy is used on zedboard (xilinx zynq platform).

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:13 +02:00
Troy Kisky
1adb406b01 phy: add phy_find_by_mask/phy_connect_dev
It is useful to be able to try a range of
possible phy addresses to connect.

Also, an ethernet device is not required
to use phy_find_by_mask leading to better
separation of mii vs ethernet, as suggested
by Andy Fleming.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-28 06:57:50 +01:00
Albert ARIBAUD
0a16ea5933 mv88e61xx: refactor PHY and SWITCH level-code
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-01-09 04:12:10 +05:30
Michal Simek
b4b81e83f5 phy: Add support for Marvell 88E1118R
Marvell 88E1118R has different uid then 88E1118.

Signed-off-by: Michal Simek <monstr@monstr.eu>
CC: Andy Fleming <afleming@freescale.com>
CC: Zang Roy-R61911 <tie-fei.zang@freescale.com>
CC: Kumar Gala <galak@kernel.crashing.org>
2012-12-15 12:28:22 -06:00
Kim Phillips
960d70c600 drivers/net/: sparse fixes
phy.c:46:5: warning: symbol 'genphy_config_advert' was not declared. Should it be static?
phy.c:121:5: warning: symbol 'genphy_setup_forced' was not declared. Should it be static?
phy.c:468:5: warning: symbol 'phy_probe' was not declared. Should it be static?
phy.c:491:19: warning: symbol 'get_phy_driver' was not declared. Should it be static?
phy.c:508:19: warning: symbol 'phy_device_create' was not declared. Should it be static?
phy.c:552:5: warning: symbol 'get_phy_id' was not declared. Should it be static?
phy.c:584:19: warning: symbol 'get_phy_device' was not declared. Should it be sta
vitesse.c:126:5: warning: symbol 'vsc8601_config' was not declared. Should it be static?
vsc7385.c:33:5: warning: symbol 'vsc7385_upload_firmware' was not declared. Should it be static?
tgec_phy.c:33:5: warning: symbol 'tgec_mdio_write' was not declared. Should it be static?
tgec_phy.c:75:5: warning: symbol 'tgec_mdio_read' was not declared. Should it be static?
tgec_phy.c:117:5: warning: symbol 'tgec_mdio_reset' was not declared. Should it be static?
eth.c:48:6: warning: symbol 'dtsec_configure_serdes' was not declared. Should it be static?
p4080.c:26:5: warning: symbol 'port_to_devdisr' was not declared. Should it be static?

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:36 -07:00
Kim Phillips
0637059088 net/: sparse fixes
bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static?
bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static?
bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static?
arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static?
arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static?
arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static?
atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static?
net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static?
net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static?
ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static?
ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static?
tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static?
tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static?
eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static?

Note: in the ping.c fix, commit a36b12f95a
"net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING
clause from when it was necessary to avoid warnings when it was embedded
in net.c.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:36 -07:00
Priyanka Jain
f91ba0ecbc net: Add Vitesse VSC8662 PHY support
-VSC8662 is Dual Port 10/100/1000Base-T Phy,
 100Base-FX/1000/Base-X Gigabit Ethernt Transceiver Phy.

-Its register set and features are similar to
 other Vitesse Phys

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2012-09-27 12:21:59 -05:00
Valentin Longchamp
b737337aaf net/phy: support the mv88e6352 switch
This patch add support for the configuration of an external switch from
the 88E6xxx series from Marvell trough an MDIO link using indirect
adressing. This can be used if we do not want to use an EEPROM for the
configuration.

This driver is not generic and was not tested on other switches than the
88e6352. This is proposed as a first implementation that is somewhat
limited but works and that can be used as a basis for further
developments for this switch family.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Joe Hershberger <joe.hershberger@gmail.com>
2012-09-27 12:21:56 -05:00
Troy Kisky
cc5f552283 net: phy: micrel: make ksz9021 phy accessible
Micrel accidentally used the same part number
for the KS8721 and KSZ9021. So, both cannot be
in the same build of u-boot. Add a config option
to handle this.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
2012-07-11 13:15:30 -05:00
Timur Tabi
6e5b9ac097 phylib: phy_startup() should return an error code on failure
phy_startup() calls the PHY driver's startup function, but it ignores the
return code from that function, and so it never returns any failures.

Signed-off-by: Timur Tabi <timur@freescale.com>
2012-07-11 13:15:30 -05:00
Troy Kisky
9fafe7dab9 net: phy: make board_phy_config responsible for calling drv->config
Boards may have things they want done before or after normal phy config.
Letting the boards call drv->config allows them more flexibilty.
Boards affected by this change are corenet_ds and mpc8544ds.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2012-02-27 21:19:25 +01:00
Troy Kisky
8682aba7da net: phy: add support for Micrel's KSZ9021
Add the gigabit phy KSZ9021.
Also, add function ksz9021_phy_extended_write
/_read for access to the phys extended registers.
The environment variable "disable_giga"
can be used to disable 1000baseTx.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2012-02-27 21:19:25 +01:00
Vladimir Zapolskiy
fcc0c75dea phy: add Micrel KS8721BL phy definition
This adds support for the Micrel KS8721BL/SL PHY.

The definition is taken from the correspondent datasheet.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2011-12-20 23:50:10 +01:00
Nobuhiro Iwamatsu
5751aa2f24 phy: Add support for SMSC LAN87xx PHYs
This adds support for the SMSC LAN87xx PHYs.

Following PHYs can be used by set CONFIG_PHY_SMSC to config.
 - SMSC LAN8700
 - SMSC LAN8710/LAN8720
 - SMSC LAN8710/LAN8720

A setup of PHY was copied from linux kenrel.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Fixed white space errors; modified commit message a bit.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-12-05 23:07:59 +01:00
Zang Roy-R61911
fa12a08ec0 Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code
The original m88e1111s_config() does not do the SGMII mode
initialization and is buggy. Rewrite the function according to
3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
2011-12-05 21:59:00 +01:00
Timur Tabi
a836626cc4 powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)
The work-around for P4080 erratum SERDES9 says that the SERDES receiver
lanes should be reset after the XAUI starts tranmitting alignment signals.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-20 16:01:37 -05:00
Timur Tabi
2339e4972f phylib: wait for TN2020 to achieve SERDES lane alignment at startup
Before the Teranetics TN2020 PHY can be used, the SERDES lanes need to be
aligned, so wait for lane alignment before completing the startup sequence.

Note that this process can take up to three seconds.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-13 23:38:11 -05:00
Andy Fleming
ebfdacb42b phylib: Work around bug in Teranetics PHY
The Teranetics PHY does not properly report the link state
for fiber connections. The new PHY code actually checked the link,
and so the FM driver would refuse to talk over a linkless PHY.

But the link may actually be up, so now we always report it as up
for fiber connections on the tn2020.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2011-10-09 17:57:53 -05:00
Wolfgang Denk
0dcfb0fcb8 Revert "phylib: remove a couple of redundant code lines"
This reverts commit 041c542219.

The lines removed by this commit weren't redundant. The logic is (and
probably should be better commented):

Find the intersection of the advertised capabilities of both sides of
the link (lpa).
From that intersection, find the highest capability we can run at
(that will be the negotiated link).

Now imagine that the intersection (lpa) is (LPA_100HALF | LPA_10FULL).

The code will now set phydev->speed to 100, and phydev->duplex to 1,
but this link does not support 100FULL.

Kudos to Andy Fleming <afleming@gmail.com> for binging this to
attention and for the explanation.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-09-28 21:02:43 +02:00
Vladimir Zapolskiy
041c542219 phylib: remove a couple of redundant code lines
This change slightly improves readability of the phydev speed/duplex
assignment logic.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Detlev Zundel <dzu@denx.de>
2011-09-10 00:08:26 +02:00
Vladimir Zapolskiy
e3a77218a2 phylib: reset mii bus only if reset handler is registered
This change allows to cope with a mii bus device registered using
miiphy_register(), which doesn't assign a default reset handler.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Detlev Zundel <dzu@denx.de>
2011-09-10 00:07:55 +02:00
Wolfgang Denk
b91a9d9d4d phy.c: make less verbose - turn printf() into debug()
The PHY driver was too verbose and corrupted the boot message display
like this:

	...
	Net:   TSEC0 connected to Marvell 88E1111S
	TSEC1 connected to Marvell 88E1111S
	TSEC0, TSEC1
	...

Turn printf() into debug() so we het the expected output again:

	...
	Net:   TSEC0, TSEC1
	...

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Kumar Gala <galak@kernel.crashing.org>
2011-08-31 22:35:27 +02:00
Andy Fleming
ee8fa20f54 phylib: Detect link on 10G devices correctly
gen10g_startup() had 2 bugs:

1) It had a boolean logic error in checking the MMD mask, and
always checked all of them.

2) It checked devices which don't actually report link state, which
meant that it would never believe the link was fully up.

Fix the boolean logic, and then mask the MMD mask so only link-reporting
devices are checked.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Reported-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2011-07-27 23:21:25 +02:00
Wolfgang Denk
cd6881b519 Minor coding style cleanup.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-05-19 22:22:44 +02:00
Andy Fleming
9082eeac5d phylib: Add a bunch of PHY drivers from tsec
The tsec driver had a bunch of PHY drivers already written. This
converts them all into PHY Lib drivers, and serves as the first
set of PHY drivers for PHY Lib.

While doing that, cleaned up a number of magic numbers (though
not all of them, as PHY vendors like to keep their numbers as
magical as possible).  Also, noticed that almost all of the
vitesse/cicada PHYs had the same config/parse/startup functions,
so those have been collapsed into one.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-20 15:09:34 -05:00
Andy Fleming
5f184715ec Create PHY Lib for U-Boot
Extends the mii_dev structure to participate in a full-blown MDIO and
PHY driver scheme.  The mii_dev structure and miiphy calls are modified
in such a way to allow the original mii command and miiphy
infrastructure to work as before, but also to support a new set of APIs
which allow (among other things) sharing of PHY driver code and 10G support

The mii command will continue to support normal PHY management functions
(Clause 22 of 802.3), but will not be changed to support 10G
(Clause 45).

The basic design is similar to PHY Lib from Linux, but simplified for
U-Boot's network and driver infrastructure.

We now have MDIO drivers and PHY drivers

An MDIO driver provides:
read
write
reset

A PHY driver provides:
(optionally): probe
config - initial setup, starting of auto-negotiation
startup - waiting for AN, and reading link state
shutdown - any cleanup needed

The ethernet drivers interact with the PHY Lib using these functions:
phy_connect()
phy_config()
phy_startup()
phy_shutdown()

Each PHY driver can be configured separately, or all at once using
config_phylib_all_drivers.h (added in the patch which adds the drivers)

We also provide generic drivers for Clause 22 (10/100/1000), and
Clause 45 (10G) PHYs.

We also implement phy_reset(), and call it in phy_connect(). Because
phy_reset() is essentially the same as miiphy_reset, but:
a) must support 10G PHYs, and
b) should use the phylib primitives,

we implement miiphy_reset, using phy_reset(), but only when
CONFIG_PHYLIB is set. Otherwise, we just use the old version. In this
way, we save on compile size, even if we don't manage to save code size.

Pulled ethtool.h and mdio.h from:
git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6
782d640afd15af7a1faf01cfe566ca4ac511319d
With many, many deletions so as to enable compilation under u-boot

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-20 15:09:19 -05:00
Mike Frysinger
8ef583a035 miiphy: convert to linux/mii.h
The include/miiphy.h header duplicates a lot of things from linux/mii.h.
So punt all the things that overlap to keep the API simple and to make
merging between U-Boot and Linux simpler.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-01-09 18:06:50 +01:00
Sebastien Carlier
6d8962e814 Switch from archive libraries to partial linking
Before this commit, weak symbols were not overridden by non-weak symbols
found in archive libraries when linking with recent versions of
binutils.  As stated in the System V ABI, "the link editor does not
extract archive members to resolve undefined weak symbols".

This commit changes all Makefiles to use partial linking (ld -r) instead
of creating library archives, which forces all symbols to participate in
linking, allowing non-weak symbols to override weak symbols as intended.
This approach is also used by Linux, from which the gmake function
cmd_link_o_target (defined in config.mk and used in all Makefiles) is
inspired.

The name of each former library archive is preserved except for
extensions which change from ".a" to ".o".  This commit updates
references accordingly where needed, in particular in some linker
scripts.

This commit reveals board configurations that exclude some features but
include source files that depend these disabled features in the build,
resulting in undefined symbols.  Known such cases include:
- disabling CMD_NET but not CMD_NFS;
- enabling CONFIG_OF_LIBFDT but not CONFIG_QE.

Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com>
2010-11-17 21:02:18 +01:00
Wolfgang Denk
2e5167ccad Replace CONFIG_RELOC_FIXUP_WORKS by CONFIG_NEEDS_MANUAL_RELOC
By now, the majority of architectures have working relocation
support, so the few remaining architectures have become exceptions.
To make this more obvious, we make working relocation now the default
case, and flag the remaining cases with CONFIG_NEEDS_MANUAL_RELOC.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
Tested-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2010-10-29 21:32:07 +02:00
Ben Warren
d7fb9bcfb2 Fix compile warnings for const correctness
Commit 6e37b1a3a25004d3df5867de49fff6b3fc9c4f04 modifies several net calls
to take a (const char *) parameter instead of (char *), but in some cases
the modified functions call other functions taking (char *).  The end result
is warnings about discarding the const qualifier.

This patch fixes these other function signatures.

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-08-09 11:52:30 -07:00
Wolfgang Denk
4946775c6d Coding Style cleanup; update CHANGELOG, prepare -rc1
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-10-28 00:49:47 +01:00
Wolfgang Denk
16d1c10783 drivers/net/phy/miiphybb.c: fix warning: no newline at end of file
Add missing newline.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Luigi Mantellini <luigi.mantellini@idf-hit.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
2009-10-27 20:58:24 +01:00
Luigi 'Comio' Mantellini
4ba31ab33a Rewrite the miiphybb (Bit-banged MII bus driver) in order to support an arbitrary number of mii buses.
This feature is useful when your board uses different mii buses for different
phys and all (or a part) of these buses are implemented via bit-banging mode.

The driver requires that the following macros should be defined into the board
configuration file:

CONFIG_BITBANGMII       - Enable the miiphybb driver
CONFIG_BITBANGMII_MULTI - Enable the multi bus support

If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs
to define at least the following macros:

MII_INIT      - Generic code to enable the MII bus (optional)
MDIO_DECLARE  - Declaration needed to access to the MDIO pin (optional)
MDIO_ACTIVE   - Activate the MDIO pin as out pin
MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin
MDIO_READ     - Read the MDIO pin
MDIO(v)       - Write v on the MDIO pin
MDC_DECLARE   - Declaration needed to access to the MDC pin (optional)
MDC(v)        - Write v on the MDC pin

The previous macros make the driver compatible with the previous version
(that didn't support the multi-bus).

When the CONFIG_BITBANGMII_MULTI is also defined, the board code needs to fill
the bb_miiphy_buses[] array with a record for each required bus and declare
the bb_miiphy_buses_num variable with the number of mii buses.
The record (struct bb_miiphy_bus) has the following fields/callbacks (see
miiphy.h for details):

char name[]            - The symbolic name that must be equal to the MII bus
                         registered name
int (*init)()          - Initialization function called at startup time (just
                         before the Ethernet initialization)
int (*mdio_active)()   - Activate the MDIO pin as output
int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin
int (*set_mdio)()      - Write the MDIO pin
int (*get_mdio)()      - Read the MDIO pin
int (*set_mdc)()       - Write the MDC pin
int (*delay)()         - Delay function
void *priv             - Private data used by board specific code

The board code will look like:

struct bb_miiphy_bus bb_miiphy_buses[] = {
 { .name = miibus#1, .init = b1_init, .mdio_active = b1_mdio_active, ... },
 { .name = miibus#2, .init = b2_init, .mdio_active = b2_mdio_active, ... },
 ...
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
                          sizeof(bb_miiphy_buses[0]);

Signed-off-by: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-10 23:16:53 -07:00
Prafulla Wadaskar
32e7f239dd net: phy: mv88e61xx.c : fixed build warning
following build warning was observed

mv88e61xx.c: In function ‘mv88e61xx_busychk’:
mv88e61xx.c:208: warning: dereferencing type-punned pointer will break strict-aliasing rules

This patch fixes the same
Patch tested for rd6281a board build

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-04 22:30:46 -07:00
Prafulla Wadaskar
08c2df33f1 net: phy: bugfixes: mv88E61xx compiler warnings fixed
1. mv88E61xx driver compiler warnings fixed
2. idstr if-else statements changed to switch() construct
   and added default case too.
   This fixed idstr may be uninitialized warning

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-08-10 14:53:52 -07:00
Prafulla Wadaskar
443ce4ac9d net: phy: bugfixes: mv88E61xx multichip addressing support
With these fixes, this driver works properly for multi chip
addressging mode

Bugfixes:
1. Build error fixed for function mv88e61xx_busychk_multic-fixed
2. PHY dev address error detection- fixed
3. wrong busy bit was refered in function mv88e61xx_busychk -fixed
4. invalid data read ptr was refered for RD_PHY in case of
	multichip addressing mode -fixed

The Multichip Address mode is tested with RD6281A board having
MV88E6165 switch on it

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-07-22 22:53:45 -07:00
Richard Retanubun
3f6b18ffd9 MIIPHYBB: Return 0xFFFF if the PHY is not asserting TA.
This patch sets the returned value to 0xFFFF if the PHY does not exist
and does not assert Transfer Acknowledge. A NULL check for the value
pointer is also added for buffer overflow protection.

Without this patch 'mii info' will  show 'phantom' devices because the
value will be not be initialized and return with some random value.

Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-07-22 22:53:44 -07:00
Prafulla Wadaskar
6f51deb7f2 Marvell MV88E61XX Switch Driver support
Chips supported:-
1. 88E6161 6 port gbe swtich with 5 integrated PHYs
2. 88E6165 6 port gbe swtich with 5 integrated PHYs
2. 88E6132 3 port gbe swtich with 2 integrated PHYs
Platform specific configuration supported for:-
default or router port vlan configuration
led_init configuration
mdip/n polarity reversal configuration

Note: This driver is supported and tested against
kirkwood egiga interface

Contributors:
Yotam Admon <yotam@marvell.com>
Michael Blostein <michaelbl@marvell.com

Reviewed by: Ronen Shitrit <rshitrit@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-06-15 00:13:54 -07:00
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Jean-Christophe PLAGNIOL-VILLARD
ba7b5b2348 miiphyutil: Move conditional compilation to Makefile
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-08-29 21:53:56 +02:00
Jean-Christophe PLAGNIOL-VILLARD
55195773ea miiphybb: move to drivers/net/phy
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-08-29 12:25:02 +02:00