Commit graph

36062 commits

Author SHA1 Message Date
Masahiro Yamada
2247c332db ARM: uniphier: rename PH1-LD10/PH1-sLD11 to PH1-LD20/PH1-LD11
Due to the company's awful projecting, PH1-LD10 and PH1-sLD11 have
been renamed to PH1-LD20 and PH1-LD11, respectively.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
5fb87a1632 ARM: uniphier: rework UniPhier SoC select in Kconfig
The chains of "depends on <SoC_name>" in the current Kconfig is
clumsy.  The idea here is to allow users to choose a SoC group first
(SoC group consists of some SoCs that can coexist in one binary).
Then, allow to enable/disable each SoC support in the selected SoC
group.  This makes the Kconfig menu clearer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
fe7c95ee5c ARM: uniphier: merge two defconfig files
PH1-Pro5 support and ProXstream2/PH1-LD6b support can coexist in one
image and there is bit more room in SPL to accommodate all of them.
Merge uniphier_pro5_defconfig into uniphier_pxs2_defconfig.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
4e651003e5 ARM: uniphier: rename variable for DRAM controller base address
Rename the variable that contains the base address for consistency.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
a191e0dee0 ARM: uniphier: deprecate umc_dram_init_{start, poll}
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
7c9cac9c22 ARM: uniphier: remove unused macros for UMC base addresses
These macros are no longer used.  These base addresses are
SoC-dependent, so they should not be placed in the header.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
fd14397e93 ARM: uniphier: rework DRAM size handling in UMC init code
Currently, DRAM size is converted twice:
  size in byte -> size in Gbit -> enum

Optimize the code by converting the "size in byte" into enum directly.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
9a71844a38 ARM: uniphier: optimize PH1-Pro4 UMC init code with "for" loop
Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
b870848795 ARM: uniphier: optimize PH1-LD4 UMC init code with "for" loop
Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
c5985b4bbb ARM: uniphier: optimize PH1-sLD8 UMC init code with "for" loop
Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
71d7ef35df ARM: uniphier: refactor UMC init code for PH1-LD4
Move frequency-dependent register settings to arrays for clean-up.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
380a8cafc0 ARM: uniphier: support more DRAM use cases for PH1-sLD8
Support DDR3-1600 / 512MB DDR size.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
82e5950802 ARM: uniphier: refactor UMC init code for PH1-sLD8
Move frequency-dependent register settings to arrays for clean-up.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
6257a0b0e9 ARM: uniphier: refactor DDR-PHY init code
The if-else statements for the frequency-dependent register settings
seem clumsy.  Moving them to arrays would make it cleaner.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
7887670498 ARM: uniphier: remove unused argument of ph1_ld4_ddrphy_init()
The DDR PHY settings no longer depend on the DRAM size.  Drop the
argument from the init function.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
4f19f61184 ARM: uniphier: merge DDR PHY init code for 3 SoCs
Now these three are almost the same.  The only difference is the DTPR1
register dependency on the DRAM size, but it can be ignored.  (It has
already been ignored in PH1-sLD8 and PH1-Pro4.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
4021b4381d ARM: uniphier: add a field to specify DDR3+
Add a field to distinguish DDR3+ from (standard) DDR3.  It also
allows to delete CONFIG_DDR_STANDARD (this is not a software
configuration, but a board attribute).

Default DDR3 spec for each SoC:

  PH1-LD4, PH1-sLD8: DDR3+
  Others: DDR3

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
3c963d4899 ARM: uniphier: disable debug circuit clocks for PH1-Pro4
These settings control the clocks around the memory controller.
The debug ability is unneeded once it works properly.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
00dd3f6ab0 ARM: uniphier: remove UMC_INITCTL* and UMC_DRMR* settings
These settings were used only for the PH1-sLD3 and older SoCs.  The
PH1-LD4 and newer one just ignore them because their DDR-PHY take
care of such timing parameters instead.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
94b756f331 ARM: uniphier: refactor UMC init code for ProXstream2
Currently, a dummy value is defined for the UMC_SPCCTLA register
when the DRAM size is zero.  This seems weird because the controller
does not need setting in the first place if the size is zero.

Also, redefine enum dram_size to represent the DRAM size per 16-bit
unit.  This makes things simpler because the channel 0 and 1 are
connected with 32-bit width DRAM, while the channel 2 is connected
with 16-bit width one.

I am renaming SIZE_* into DRAM_SZ_* (and also FREQ_* to DRAM_FREQ_*
for consistency) while I am here because SIZE_* might be easily
mixed-up with the macros in include/linux/sizes.h.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
a54c879a42 ARM: uniphier: use pr_err() where possible
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
59fe23c2e0 ARM: uniphier: optimize ProXstream2 UMC init code with "for" loop
Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
46abfcc99e ARM: uniphier: rework struct uniphier_board_data
This commit reworks "struct uniphier_board_data" with an array of
DRAM channel data in it.  It will allow further cleanups by means of
"for" statements that iterate over the DDR channels.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
8353266825 ARM: uniphier: remove unused umc_polling()
This function is unused.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
aa8a93480e ARM: uniphier: default to environment in eMMC
Of the several boot devices supported, it looks like the eMMC is the
most commonly used.  Enable CONFIG_ENV_IS_IN_MMC by default.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
c231c4367a ARM: uniphier: add emmcupdate command
The Boot ROM expects the boot image (SPL) in the Boot Partition 1.
So, updating images involves the hardware partition switch.  It might
be a bit advanced for some users.

To be user-friendly, this commit adds a useful command to update the
images; just put SPL and U-Boot proper into the public directory of
the TFTP server and execute "run emmcupdate" from the command line.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
569e4be172 ARM: uniphier: add a command to find the first MMC (non-SD) device
UniPhier SoC family supports both (e)MMC boot and SD card boot;
however, both of them are handled in the same uclass.

When booting from the eMMC, we want to know the device number
of the (e)MMC, not SD.  This command is useful to find the first
MMC (non-SD) device.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
a55d9feeec ARM: uniphier: add eMMC boot support
Export device nodes needed for eMMC boot (eMMC node, pinctrl, and
clock) to the SPL DTB.  CONFIG_SUPPORT_EMMC_BOOT is also necessary
to use "mmc partconf" command.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
c7f94eecfd ARM: dts: uniphier: add SD/MMC host controller nodes
This host controller is available for all UniPhier SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
4aceb3f8d4 ARM: uniphier: enable UniPhier SD/MMC host driver
Enable the driver in all UniPhier defconfig files and add some
needed defines to the common files.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:15 +09:00
Masahiro Yamada
a111bfbfad mmc: uniphier: add driver for UniPhier SD/MMC host controller
Add a driver for the on-chip SD/eMMC host controller used by
UniPhier SoC family.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:15 +09:00
Masahiro Yamada
595dc1e162 ARM: dts: uniphier: add GPIO controller nodes
Make the GPIO driver really active.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:15 +09:00
Masahiro Yamada
b800cbde4f ARM: uniphier: enable GPIO command and driver for UniPhier SoCs
This allows to use the "gpio" command.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-02-29 03:50:15 +09:00
Masahiro Yamada
f8facbe71e gpio: do not include <asm/arch/gpio.h> for UniPhier
I implemented a GPIO driver based on Driver Model for the UniPhier
SoC family, but I could not find any good reason why such SoC
specific GPIO headers are needed.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-02-29 03:50:15 +09:00
Masahiro Yamada
b9a66b63b4 gpio: uniphier: add driver for UniPhier GPIO controller
This GPIO controller device is used on UniPhier SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-02-29 03:50:15 +09:00
Masahiro Yamada
0f5fb8ce40 ARM: dts: uniphier: rework System Bus nodes
Follow the changes of DTS in Linux.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:15 +09:00
Tom Rini
50dc8677d7 Merge git://git.denx.de/u-boot-usb 2016-02-26 18:08:43 -05:00
Tom Rini
d5c6144fe3 Merge git://git.denx.de/u-boot-dm 2016-02-26 16:22:28 -05:00
Tom Rini
38e65aeb70 Merge branch 'master' of git://git.denx.de/u-boot-net 2016-02-26 14:56:23 -05:00
Alexandre Messier
50768f5b06 net: bootp: Add environment variable for timeout period
There is currently one config option (CONFIG_NET_RETRY_COUNT) that
is available to tune the retries of the network stack.
Unfortunately, it is global to all protocols, and the value is
interpreted differently in all of them.

Add a new environment variable that directly sets the retry period for
BOOTP timeouts. If this new value is not set, the period is still derived
from the default number of retries, or from CONFIG_NET_RETRY_COUNT if
defined. When both the new variable is set and CONFIG_NET_RETRY_COUNT
is defined, the variable has precedence.

Signed-off-by: Alexandre Messier <amessier@tycoint.com>
2016-02-26 13:37:38 -06:00
Alison Wang
903d384d40 net: phy: atheros: Fix problem with phy_reset() clearing BMCR
In commit <a058052c358c> [net: phy: do not read configuration register on
reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION)
is cleared too. It causes auto-negotiation timeout error on Atheros's
PHY AR8033.

To fix this problem, genphy_config_aneg() and genphy_restart_aneg()
needs to be called in ar8035_config() to enable and restart
auto-negotiation.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-02-26 13:32:37 -06:00
Yangbo Lu
cf23b4da62 powerpc/t208xqds: fix esdhc peripheral clock support
The patch that enabled eSDHC peripheral clock support had an
obvious error as below. This patch is used to fix it.

+#define define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK

Fixes: 3285e6cbcc ("powerpc/t2080qds: enable eSDHC peripheral clock support")
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-26 10:48:07 -08:00
Marek Vasut
abd702f48c usb: ehci: Fix warning on aarch64
Fix the following warning on aarch64 introduced by using p2v/v2p
functions in the code:

In file included from ./arch/arm/include/asm/byteorder.h:29:0,
                 from include/compiler.h:125,
                 from include/image.h:19,
                 from include/common.h:88,
                 from drivers/usb/host/ehci-hcd.c:10:
drivers/usb/host/ehci-hcd.c: In function ‘ehci_td_buffer’:
drivers/usb/host/ehci-hcd.c:250:49: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
   td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr));
                                                 ^
include/linux/byteorder/little_endian.h:34:51: note: in definition of macro ‘__cpu_to_le32’
 #define __cpu_to_le32(x) ((__force __le32)(__u32)(x))
                                                   ^
drivers/usb/host/ehci-hcd.c:250:24: note: in expansion of macro ‘cpu_to_hc32’
   td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr));

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Rini <trini@konsulko.com>
2016-02-26 19:45:05 +01:00
Bin Meng
6796704b0d pci: Fix compiler warnings in dm_pciauto_setup_device()
Fix the following compiler warnings when DEBUG is on.

warning: 'bar_res' may be used uninitialized in this function.
drivers/pci/pci_auto.c:101:21:
   if (!enum_only && pciauto_region_allocate(bar_res, bar_size,
                        ^

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-26 08:53:10 -07:00
Simon Glass
f8025b58f8 spi: Re-enable the SPI flash tests
These are working correctly again, so re-enable them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Jagan Teki <jteki@openedev.com>
2016-02-26 08:53:10 -07:00
Simon Glass
0badb23d11 spi: Correct two error return values
When an error number is provided we should use it, not change it. This fixes
the SPI and SPI flash tests.

One of these is long-standing. The other seems to have been introduced by
commit 1e90d9fd (sf: Move read_id code to sf_ops).

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 1e90d9fd (sf: Move read_id code to sf_ops)
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Jagan Teki <jteki@openedev.com>
2016-02-26 08:53:10 -07:00
Simon Glass
ffe276d27a sandbox: spi: Remove an incorrect free()
We must not free data that is managed by driver mode. Remove this line,
which is a hangover from the pre-driver-model code.

This fixes a problem where 'sf probe' crashes U-Boot if the backing file
for the SPI flash cannot be found.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-02-26 08:53:10 -07:00
Simon Glass
20f655da11 sandbox: spi: Add more debugging to SPI emulation
Add a little more debugging to help when things go wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Jagan Teki <jteki@openedev.com>
2016-02-26 08:53:10 -07:00
Simon Glass
651490212a sandbox: Enable the early timer
Enable this so that tracing works with sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-26 08:53:10 -07:00
Simon Glass
c00e922530 sandbox: Correct ordering of defconfig
This has got out of order: fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-02-26 08:53:10 -07:00