Since spi_slave is a spi pointer in spi_flash{} then assign
spi_slave{} pointer to flash->spi and remove spi_slave
pointer argument to
- spi_flash_probe_slave
- spi_flash_scan
Tested-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
For assigning read_bar commands in spansion case, break
is missing this patch add that break.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
SST parts added on sf_params.c supports both SST_WR which consits
of both BP and WP and there is a spi controller ich which supports
only BP so the relevent _write hook set based on "slave->op_mode_tx"
hence there is no respective change required from flash side hance
removed these.
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Removed unneeded header includes in sf_ops and sf_probe
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Using macro's for flash power up read-only access code
leads wrong behaviour hence use idcode0 for runtime
detection, hence the flash which require this functionality
gets detected at runtime.
Tested-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Most of the register access function are static,
so used simple name to represent each.
Tested-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
This patch removes unneeded ifdef and fixed accordingly.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Use static for file-scope functions and removed
them from header files.
Tested-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
- Move bar read code below the bar write hance both
at once place, hence it easy for #ifdef macro only
once and readable.
- Move read_cmd_array at top
Tested-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
read_id code is related to spi_flash stuff
hence moved to sf_ops.
Tested-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Intension is that sf_ops should deals all spi_flash
related stuff and sf_probe (which should renamed future)
should be an interface layer for spi_flash versus spi drivers.
sf_ops => spi_flash interface
sf_probe => interface layer vs spi_flash(sf_probe) to spi drivers
Tested-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Rename spi_flash_validate_params to spi_flash_scan
as this code not only deals with params setup but
also configure all spi_flash attributes.
And also moved all flash related code into
spi_flash_scan for future functionality addition.
Tested-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Fix erase and write error code, which should be "protected".
From the "Embedded Peripherals IP User Guide" of Altera,
The "Illegal write" flag indicates that a write instruction is
targeting a protected sector on the flash memory. This bit is
set to indicate that the IP has cancelled a write instruction.
The "Illegal erase" flag indicates that an erase instruction has
been set to a protected sector on the flash memory. This bit is
set to indicate that the IP has cancelled the erase instruction.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Add lock() and unlock() mtd ops to altera_qspi.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Marek Vasut <marex@denx.de>
The console includes a global variable and several functions that are only
used by a small subset of U-Boot files. Before adding more functions, move
the definitions into their own header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is follow up patch based on
"dm: Add support for all targets which requires MANUAL_RELOC"
(sha1: 484fdf5ba0)
to update function pointers for DM.
Using post_bind is not ideal but it is one on current option what can be
used. Variable reloc_done has to be used do not call relocation after
every bind. Maybe new core functions should be introduced for this case.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Make spl_*_load_image() functions return a value instead of
hanging if a problem is encountered. This enables main spl code
to make the decision whether to hang or not, thus preparing
it to support alternative boot devices.
Some boot devices (namely nand and spi) do not hang on error.
Instead, they return normally and SPL proceeds to boot the
contents of the load address. This is considered a bug and
is rectified by hanging on error for these devices as well.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Hans De Goede <hdegoede@redhat.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Jagan Teki <jteki@openedev.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Change ioremap() to map_physmem(), as it is more used in u-boot.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Marek Vasut <marex@denx.de>
flash->flags for SST flash should be updated for both DM and non-DM
flash drivers.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
We should check the return value from spi_flash_cmd_read_status() and
propagate it in the case of error.
This fixes a defect caught by Coverity.
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
SST SPI NOR flash has the same locking programming bits
as ST Micro - added support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
[Minor change on commit message]
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
The relevent boards which used this driver got zapped
in previous release and the driver is never used in the
code and also it doesn't use/do any spi-flash operations.
Commit details for relevent removed boards:
"ARM: at91: remove non-generic boards"
(sha1: f6b42c1403)
Cc: Tom Rini <trini@konsulko.com>
Cc: Albin Tonnerre <albin.tonnerre@free-electrons.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
commit c3c016c "sf: Add SPI NOR protection mechanism" introduced
flash_lock()/flash_unlock()/flash_is_locked() methods for SPI flash,
but not every flash driver supplies these. We should test these
methods against NULL before actually calling them.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
The current error message in get_part if CONFIG_MTDPARTS is disabled is
"offset is not a number" which is confusing and doesn't help at all.
Change that for something that might give a hint on what's going on.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add Altera Generic Quad SPI Controller support. The controller
converts SPI NOR flash to parallel flash interface. So it is
not like other SPI flash, but rather like CFI flash.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Implement a Memory Technology Device (MTD) uclass. It should
include most flash drivers in the future. Though no uclass ops
are defined yet, the MTD ops could be used.
The NAND flash driver is based on MTD. The CFI flash and SPI
flash support MTD, too. It should make sense to convert them
to MTD uclass.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Many SPI flashes have protection bits (BP2, BP1 and BP0) in the
status register that can protect selected regions of the SPI NOR.
Take these bits into account when performing erase operations,
making sure that the protected areas are skipped.
Tested on a mx6qsabresd:
=> sf probe
SF: Detected M25P32 with page size 256 Bytes, erase size 64 KiB, total 4 MiB
=> sf protect lock 0x3f0000 0x10000
=> sf erase 0x3f0000 0x10000
offset 0x3f0000 is protected and cannot be erased
SF: 65536 bytes @ 0x3f0000 Erased: ERROR
=> sf protect unlock 0x3f0000 0x10000
=> sf erase 0x3f0000 0x10000
SF: 65536 bytes @ 0x3f0000 Erased: OK
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
[re-worked to fit the lock common to dm and non-dm]
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Add the SPI NOR protection mechanism from the kernel.
This code is based on the work from
Brian Norris <computersforpeace@gmail.com>
Here is the commit details:
"mtd: spi-nor: refactor block protection functions"
(sha1: 62593cf40b23b523b9fc9334ca61ba6c595ebb09)
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Use the is_power_of_2() definition from log2.h to align with the
kernel implementation.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
This patch changes the cword union to use specific length types that are
architecture indepented.
This patch also renames the members of the cword union to represent
their usage, i.e.:
c -> w8
s -> w16
l -> w32
ll -> w64
Where "w" stands for "width" in bits.
I discovered this problem when enabling CFI flash on vexpress64.
cword.l was an unsigned long int, but it was intended to be 32 bits wide.
Unfortunately, it's 64-bits wide on a 64-bit system, meaning that a
64-bit system fails when attempting to use 32-bit wide CFI flash parts.
Similar problems also existed with the other cword sizes.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stefan Roese <sr@denx.de>
The PEB array is an array of __be32, so let's fix the
scan_pool() prototype accordingly.
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Heiko Schocher <hs@denx.de>
sync with linux v4.2
commit 64291f7db5bd8150a74ad2036f1037e6a0428df2
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun Aug 30 11:34:09 2015 -0700
Linux 4.2
This update is needed, as it turned out, that fastmap
was in experimental/broken state in kernel v3.15, which
was the last base for U-Boot.
Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
This patch adds flag status register reading support to
spi_flash_cmd_wait_ready.
Cc: Simon Glass <sjg@chromium.org>
Cc: Marek Vasut <marex@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Hou Zhiqiang <B48286@freescale.com>
Tested-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Current flash wait_ready logic is not modular to add new
register status check, hence updated the status check for
adding few more register checks in future.
Below are the sf speed runs with 'sf update' on whole flash, 16MiB.
=> sf update 0x100 0x0 0x1000000
device 0 whole chip
16777216 bytes written, 0 bytes skipped in 59.564s, speed 289262 B/s
=> sf update 0x100 0x0 0x1000000
device 0 whole chip
16777216 bytes written, 0 bytes skipped in 62.549s, speed 275036 B/s
=> sf update 0x100 0x0 0x1000000
device 0 whole chip
16777216 bytes written, 0 bytes skipped in 61.276s, speed 284359 B/s
Cc: Simon Glass <sjg@chromium.org>
Cc: Marek Vasut <marex@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Tom Rini <trini@konsulko.com>
Tested-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Use the flash->flags for generic usage, not only for dm-spi-flash,
this will be used for future flag additions.
[Correct the spi flash flags detect logic]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Optimized spi-flash bar writing code and also removed
unnecessary bank_sel in read_ops.
Cc: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Add spi_flash_read_bar function for reading bar and
discovering bar commands at probe time.
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
If computed bank_sel is same as flash->bank_curr which is
computed at probe time, then return the bank_sel instead of zero.
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Added support for IS25LP128 flash part.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Added support for IS25LP064 flash part.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Added support for IS25LP032 flash part.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
The current name is inconsistent with other driver model data access
functions. Rename it and fix up all users.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
This resyncs the driver changes with the Linux version of the
driver. The driver received some feedback in the LKML and got
recently acceppted, the latest version can be found here:
https://lkml.org/lkml/2015/9/2/678
Notable changes are:
- On ECC error, reread OOB and count bit flips in OOB too.
If flipped bits are below threshold, also return an empty
OOB buffer.
- Return the amount of bit flips in vf610_nfc_read_page.
- Use endianness aware vf610_nfc_read to read ECC status.
- Do not enable IDLE IRQ (since we do not operate with an
interrupt service routine).
- Use type safe struct for buffer variants (vf610_nfc_alt_buf).
- Renamed variables in struct vf610_nfc (column and page_sz)
to reflect better what they really representing.
The U-Boot version currently does not support RAW NAND write
when using the HW ECC engine.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Tested-by: Stefan Agner <stefan@agner.ch>
Acked-by: Scott Wood <scottwood@freescale.com>
Messages on corrected bit-flips are not really useful,
as bit-flips are perfectly normal. Let's avoid cluttering
the console and make them debug.
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
AT26DF081A is the spi flash type of TWR-MEM(SCH-26248) card.
We can access the flash through DSPI2 on LS1021ATWR board.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
We know when u-boot is written to its own partition, in this case the
layout always is:
eb 0 spl
eb 1 spl-backup
eb 2 u-boot
eb 3 u-boot-backup
eb: erase-block
So if we cannot load u-boot from its primary offset we know exactly where
to look for it.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Check maximum ecc strength for each platfrom to avoid the calculated ecc
exceed the limitation.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Han Xu <b45815@freescale.com>
Tested-By: Tim Harvey <tharvey at gateworks.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
This patch addresses some comments raised by Scott in the last versions.
Here the changes in detail:
- Removed __maybe_unused as its not needed
- Added check for strength == 4 and error out for the unsupported
ECC strength values
- Don't set .caclulate, .correct, and .bytes for NAND_ECC_SOFT_BCH as this
will be done in nand_scan_tail()
- Set .caclulate back to fsmc_read_hwecc() in the HW case
- Added comment that this function will only be called on SPEAr platforms,
not supporting the BCH8 HW ECC (FSMC_VER8)
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Acked-by: Scott Wood <scottwood@freescale.com>
introduce BIT() definition, used in at91_udc gadget
driver.
Signed-off-by: Heiko Schocher <hs@denx.de>
[remove all other occurrences of BIT(x) definition]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
Now that we have a new header file for cache-aligned allocation, we should
move the stack-based allocation macro there also.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present malloc.h is included everywhere since it recently was added to
common.h in this commit:
4519668 mtd/nand/ubi: assortment of alignment fixes
This seems wasteful and unnecessary. We have been trying to trim down
common.h and put separate functions into separate header files and that
change goes in the opposite direction.
Move malloc_cache_aligned() to a new header so that this can be avoided.
The header would perhaps be better named as alignmem.h but it needs to be
included after common.h and people might be confused by this. With the name
memalign.h it fits nicely after malloc() in most cases.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
be used by boards equipped with a NAND chip that requires 4-bit ECC strength.
The SPEAr600 HW ECC only supports 1-bit ECC strength.
To enable SW BCH4, you need to specify this in your config header:
#define CONFIG_NAND_ECC_BCH
#define CONFIG_BCH
And use the command "nandecc bch4" to select this ECC scheme upon runtime.
Tested on SPEAr600 x600 board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
This patch adds support for NAND chips with 4KiB page size and 24/1024
ECC strength. Like the Micron MT29F32G08CBACAWP which is used on the
ICnova-A20 SoM.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Make CONFIG_SYS_NAND_U_BOOT_OFFS configurable through Kconfig, just like
SYS_NAND_BUSWIDTH_16BIT this is only enabled on some SoCs using depends,
to avoid double defining it for SoCs which have not yet moved to Kconfig
for this.
Having this in Kconfig is useful because this is something which may
differ from one board to the other even when using the same SoC.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Scott Wood <scottwood@freescale.com>
Some status flags remain set until you explicetly clear the bit
in the status register.
Fix the SPL implementation to avoid false positive.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[hdegoede@redhat.com: Port from v2015.07 to v2015.10]
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
We only ever use syndrome mode for the partitions which contain the SPL,
as that is required for the BROM to be able to read the SPL.
Instead of using some arbritray limit for deciding whether or not to
use syndrome, be smart and check if u-boot-dtb.bin is directly behind
the SPL, if it is not then it is on its own partition and we should not
use syndrome.
Note the reason why we only use syndrome mode for the SPL is because it
comeswith weaker randomization, introducing a risk for more bit errors,
so we want to avoid it when possible.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We eventually want to add full nand support, since it makes no sense
to build SPL with nand support and u-boot without, or the other way
around, a single option will suffice.
Renaming the Kconfig option now makes things easier when we add full
nand support in the future.
The "obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o" is moved to an
"ifdef CONFIG_SPL_BUILD" block in the Makefile.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The BROM does not care / use bad page markings, instead it deals with
any bad pages in the first erase-block by simply trying to load "boot0"
from the next erase-block.
This commit implements the same strategy for the sunxi spl nand code,
allowing it to boot from the backup boot partition when the main boot
partition is bad (tested by erasing the main boot partition).
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Auto detect the nand configuration parameters, like the BROM does.
This allows us to get rid of various Kconfig settings, and is
necessary to support generic boards like the mk802 which have seen
many production runs with different nands.
The full blown u-boot/kernel nand driver uses the nand id to determine
this info, for the SPL we do as the BROM does and simply try a few
standard configs.
Note the table only contains configs which are known to actually be used,
rather then all the configs the BROM tries. This means that it may need
to be updated in the future as we add support for nand on more boards.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Parametrize the lowlevel nand_read_page function, instead of directly
using the CONFIG_foo settings for page-size, etc. there and add a few
wrappers / helper functions for calling it.
This is a preparation patch for adding auto-detecting of the nand
parameters like the BROM does.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Properly config page-size in the nand ctl register, it seems that things
work fine without doing this, but still lets play it safe and properly
set the page-size.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Other then having a few less chip-select lines the nand controller
on sun4i, sun5i and sun7i is identical.
Note this patch also muxes GPC7 to the NAND on sun7i where as before
it was not muxed this way. GPC7 is a standard NAND pin, so it should
always be muxed to the NAND when in use.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Sync the code for figuring out the ecc_mode and ecc_offset with the linux
kernel v4.1. Keeping this in sync seems like a good idea in general, and
it fixes / adds support for ecc strengths of 56, 60 and 64 bits.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We are using dma, so we should flush the cache before starting the dma,
and invalidate it once the dma is done.
Things are working without this by mostly luck, but lets not rely on that.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Turn off the nand and dma clocks when we're done with the nand, this
puts the nand and dma controllers back into a clean state for when the
kernel boots.
Without this the kernel will not boot properly when it is built with
dma-controller support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Use SYS_NAND_SELF_INIT and only setup the pinmux and clocks when we are
actually using the nand.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
In syndrome mode we set the NFC_SEQ bit in the command register, so the
spare-area register is not used. Also the value currently being written is
actual wrong, the ecc sits at "column + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE"
not just CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE.
So the current code only serves to confuse the user -> remove it.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
There is no need to reset the nand chip for every ecc-block read.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
nand_spl_load_image() always gets called with either CONFIG_SYS_TEXT_BASE
or spl_image.load_addr as destination, both of which are properly aligened,
and have plenty of space for "overshooting" up to
CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE bytes, as we read in
CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE bytes chunks.
This saves CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE (typically 1k) in
SPL size, which is a lot on the total 24k we have.
Note this changes the dma destination from SRAM to DRAM, so this patch
updates the DDMA_DST_TYPE bits in the dma controller cfg0 reg accordingly.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Since commit 2580a2a7e7 ("mtd: nand: Increase max sizes of OOB and
Page size"), three boards (ph1_ld4, ph1_pro4, ph1_sld8) fail to build
with the following error message:
arm-linux-gnueabi-ld.bfd: SPL image plus BSS too big
They compile drivers/mtd/nand/denali_spl.c and it has a page_buffer
as static data:
static uint8_t page_buffer[NAND_MAX_PAGESIZE];
This buffer required 8KB in .bss section before that commit and now
it has been increased to 16KB. Given limited code/memory size for SPL,
it is not a good idea to allocate a page buffer statically. In the
first place, the load address 'dst' can be used as a page buffer.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Various U-Boot adoptions/extensions to MTD/NAND/UBI did not take buffer
alignment into account which led to failures of the following form:
ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108
ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Scott Wood <scottwood@freescale.com>
[trini: Add __UBOOT__ hunk to lib/zlib/zutil.c due to malloc.h in common.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
Follow linux dma flow:
Before DMA read, be sure to invalidate the cache over the address
range of DMA buffer to prevent cache coherency problems.
After DMA read, invalidate dcache again.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
If ecc chunk data size is 512 and oobsize is bigger than 512, there is
a chance that block_mark_bit_offset conflicts with bch ecc area.
The following graph is modified from kernel gpmi-nand.c driver with
each data block 512 bytes. We can see that Block Mark conflicts with
ecc area from bch view. We can enlarge the ecc chunk size to avoid
this problem to those oobsize which is larger than 512.
| P |
|<----------------------------------------------------------------->|
| |
| (Block Mark) |
| P' | | | |
|<--------------------------------------------------->| D | | O'|
| |<--------->| |<->|
V V V V V
+---+--------------+-+--------------+-+--------------+-+----------+-+---+
| M | data |E| data |E| data |E| data |E| |
+---+--------------+-+--------------+-+--------------+-+----------+-+---+
^ ^
| O |
|<---------------->|
P : the page size for BCH module.
E : The ECC strength.
G : the length of Galois Field.
N : The chunk count of per page.
M : the metasize of per page.
C : the ecc chunk size, aka the "data" above.
P': the nand chip's page size.
O : the nand chip's oob size.
O': the free oob.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-By: Tim Harvey <tharvey@gateworks.com>
Cloned from the Linux driver v4.2.0-rc2. Plus some patches from
Antoine Tenart enabling controller initialization and ONFI timing
support:
http://lists.infradead.org/pipermail/linux-mtd/2015-July/060197.html
Please note that this driver needs the Linux NAND subsystem sync to v4.1
from Scott to be applied:
https://www.mail-archive.com/u-boot@lists.denx.de/msg175762.html
Otherwise it will not compile.
Tested on the Marvell Armada XP DB-MV784MP-GP eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Antoine Tenart <antoine.tenart@free-electrons.com>
Cc: Ezeguil Garcia <ezequiel.garcia@free-electrons.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Scott Wood <scottwood@freescale.com>
Update the NAND code to match Linux v4.1. The previous sync was
from Linux v3.15 in commit 4e67c57125.
CONFIG_SYS_NAND_RESET_CNT is removed, as the upstream Linux code now
has its own timeout. Plus, CONFIG_SYS_NAND_RESET_CNT was undocumented
and not selected by any board.
Signed-off-by: Scott Wood <scottwood@freescale.com>
In addition to mtd_block_isbad(), which checks if a block is bad or
reserved, it's needed to check if a block is reserved only (but not
bad). This commit adds an MTD interface for it, in a similar fashion to
mtd_block_isbad().
While here, fix mtd_block_isbad() so the out-of-bounds checking is done
before the callback check.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
[scottwood: Cherry-picked from Linux 8471bb73ba10ed67]
Signed-off-by: Scott Wood <scottwood@freescale.com>
We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing
devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear
away the ugly logic in include/fdtdec.h:
#ifdef CONFIG_OF_CONTROL
# if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL)
# define OF_CONTROL 0
# else
# define OF_CONTROL 1
# endif
#else
# define OF_CONTROL 0
#endif
Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to
CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for
SPL.
Also, we no longer have to cancel CONFIG_OF_CONTROL in
include/config_uncmd_spl.h and scripts/Makefile.spl.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Incorporate ECC layout for small page NAND from legacy LPCLinux NXP BSP.
The code taken from the legacy patch is:
- lpc32xx SLC NAND driver (ECC layout for small page)
This layout is matching the lpc32xx NAND SLC Linux Kernel driver.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Incorporate NAND SLC hardware ECC support from legacy LPCLinux NXP BSP.
The code taken from the legacy patch is:
- lpc32xx SLC NAND driver (hardware ECC support)
- lpc3250 header file missing SLC NAND registers definition
The legacy driver was updated and clean-up as part of the integration with the existing NAND SLC driver.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Tested-by: Vladimir Zapolskiy <vz@mleia.com>
When doing a memory mapped copy we may have DMA available and thus need
to have this copy abstracted so that the driver can do it, rather than a
simple memcpy.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Make the support for 4K subpage I/O on a SPI NOR flash configurable.
A board which requires the SPI NOR to be accessed in larger 32KiB
or 64KiB pages can disable the 4K subpage support, but by default,
the support for 4K subpage I/O is enabled. The functionality of this
option is the same as CONFIG_MTD_SPI_NOR_USE_4K_SECTORS in Linux.
This is extremely useful in case one uses UBI on a SPI NOR flash.
UBI needs at least 15k EBs and can not work on a flash which uses
4k ones, so disabling the support for 4k subpages lets UBI work on
such flash.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Disable subpage writes as we do not provide ecc->hwctl.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Fix PIO read_byte() implementation not only used for the legacy READ ID
but also the PARAM command required for proper ONFI detection.
This fix is inspired by Lucas Stach's Linux Tegra NAND driver of late
(not mainline yet but getting there soon I hope).
I vaguely remember that those commands are special on 16-bit bus NAND
(e.g. always return 8-bit data regardless) and later Linux MTD fixed/
changed the way this is handled which in turn broke once U-Boot pulled
that in. Basically instead of doing PIO read regular DMA block read is
now used which this patch actually fixes.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The change adds support of LPC32xx SLC NAND controller.
LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.
This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.
Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.
The driver can be included to an SPL image.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
Some NAND controllers define custom functions to read data out,
respect this in order to correctly support bad block handling in
simple SPL NAND framework.
NAND controller specific read_buf() is used even to read 1 byte in
case of connected 8-bit NAND device, it turns out that read_byte()
may become outdated.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Tom Warren <twarren@nvidia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
remove unneeded udelay() in this function, as we use
the dev_ready pin.
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
When SPL_NAND_SUNXI option is selected in config, set some configuration
options for sunxi NAND.
This commit also introduces the configurable options in Kconfig.
Signed-off-by: Peter Gielda <pgielda@antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This driver adds NAND support to SPL.
It was tested on Allwinner A20.
Signed-off-by: Peter Gielda <pgielda@antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add kconfig options for various SPI flashes and use them in cm-fx6 defconfig.
Cc: Jagan Teki <jteki@openedev.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Since commit 09c3280754 (mtd, nand: Move common functions from
cmd_nand.c to common place), NAND commands would not work at all
on large devices.
=> nand read 80000000 10000 10000
NAND read: Offset exceeds device limit
=> nand erase 100000 100000
NAND erase: Offset exceeds device limit
The type of the "size" of "struct mtd_info" is uint64_t, while
mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type.
The chipsize is wrapped around if the argument is given with 2GB
or larger.
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Added SPI_FLASH_DATAFLASH entry on Kconfig with help description.
data flash driver comes with good decription, hence moved the
same on to kconfig help decription.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Haikun Wang <haikun.wang@freescale.com>
Added SPI_FLASH_MTD entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Rename CONFIG_SF_DATAFLASH into CONFIG_SPI_FLASH_DATAFLASH
as it follows the naming convention same as remaining configs.
Signed-off-by: Jagan Teki <jteki@openedev.com>
sst25wf040b doesn't support Auto Address Increment Programming command.
Remove SST_WR flag.
Signed-off-by: Haikun Wang <B53464@freescale.com>
Tested-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
Move common functions from cmd_nand.c (for calculating offset
and size from cmdline paramter) to common place, so they could
used from other commands which use mtd partitions.
For onenand the arg_off_size() is left in common/cmd_onenand.c.
It should use now the common arg_off() function, but as I could
not test onenand I let it there ...
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
Add MTD layer driver for spi, original patch from:
http://git.denx.de/?p=u-boot/u-boot-mips.git;a=commitdiff;h=bb246819cdc90493dd7089eaa51b9e639765cced
Changes from Heiko Schocher against this patch:
- Remove compile error if not defining CONFIG_SPI_FLASH_MTD:
LD drivers/mtd/spi/built-in.o
drivers/mtd/spi/sf_probe.o: In function `spi_flash_mtd_unregister':
/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: multiple definition of `spi_flash_mtd_unregister'
drivers/mtd/spi/sf_params.o:/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: first defined here
drivers/mtd/spi/sf_ops.o: In function `spi_flash_mtd_unregister':
/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: multiple definition of `spi_flash_mtd_unregister'
drivers/mtd/spi/sf_params.o:/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: first defined here
make[1]: *** [drivers/mtd/spi/built-in.o] Fehler 1
make: *** [drivers/mtd/spi] Fehler 2
- Add a README entry.
- Add correct writebufsize, to fit with Linux v3.14
MTD, UBI/UBIFS sync.
Note (From Jagan): For testing raw mtd parition erase/read/write operations
using cmd_sf, sf_mtd should be required to register the spi flash device to
MTD layer but the sf_mtd_info ops were not required until and unless if we
use any flash filesystem layer say for example UBI. Due to this the foot-print
got increased ~290bytes in non-UBI case here that should be acceptible.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Jagannadh Teki <jteki@openedev.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
Atmel DataFlash chips have commands different from common spi
flash commands.
Atmel DataFlash also have special page-size.
This driver add support for accessing Atmel DataFlash.
It is based on the Driver Model.
Example:
=> sf probe 1:0
SPI DataFlash: Detected AT45DB021B with page size 264 Bytes, erase size 264 Bytes, total 264 KiB, revision d
=> sf erase 0 42000
SF: 270336 bytes @ 0x0 Erased: OK
=> mw.l 82000000 45444342 20000
=> sf write 82000000 0 42000
SF: 270336 bytes @ 0x0 Written: OK
=> sf read 83000000 0 42000
SF: 270336 bytes @ 0x0 Read: OK
=> cmp.b 82000000 83000000 42000
Total of 270336 byte(s) were the same
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Tested-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chakra Divi <cdivi@openedev.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
This reverts commit f76eba38b3.
This patch did not have a full and proper copyright/S-o-b chain.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Conflicts:
include/configs/sun6i.h
include/configs/sun8i.h
commit c316f57 "mtd: OMAP: Enable GPMC prefetch mode" only enabled
prefetch mode for 8 bit nand access, this adds 16 bit as well.
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Daniel Mack <zonque@gmail.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Tom Rini <trini@konsulko.com>
The prefech mode is a feature of the gpmc, not the ELM. An am3517
does not have an elm, but can do prefeches, so move the code out
of the CONFIG_NAND_OMAP_ELM ifdef.
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Daniel Mack <zonque@gmail.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit adds support to the sunxi SPL to load u-boot from the internal
NAND. Note this only adds support to access the boot partitions to load
u-boot, full NAND support to load the kernel, etc. from the nand data
partition will come later.
Signed-off-by: Roy Spliet <r.spliet@ultimaker.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This changes enable ONFI detection. The Read ID command now allows
one address byte which is needed for ONFI detection. To read the
ONFI parameter page, the NAND_CMD_PARAM need to be supported. The
CMD code enables one command and one address byte along with reading
data from flash using R/B#, as specified by ONFI.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Add option to choose between current 24-error correction and 32-error
correction through Kconfig. 32-error correction allow to use NAND
chips which require up to 8-bit error correction per 512 byte (when
using 2K pages).
Signed-off-by: Stefan Agner <stefan@agner.ch>
This commit allows users to enable/disable the Freescale NFC
controller found in systems like Vybrid (VF610), MPC5125, MCF54418
or Kinetis K70 via Kconfig with more detailed help docs.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stefano Babic <sbabic@denx.de>
[scottwood: updated vf610twr_nand_defconfig]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Use in-band bad block table (NAND_BBT_NO_OOB) which allows to
use the full OOB for hardare ECC purposes. Since there is no
ECC correction on the OOB it is also safer to use in-band area
to store the bad block table marker.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Implement read of OOB area only. When using column and sector size
properties, only parts of the page can be read. However, this works
only when hardware ECC is disabled, otherwise the ECC engine would
ruin the data in the buffer. To allow OOB only reads, three points
had to be addressed:
- Set ECC mode per command.
- Handle NAND_CMD_READOOB seperate. Make sure column and sector
size is correctly set up, while disabling ECC.
- Now, the OOB data end up at the beginning of the buffer. Remove
the special handling of OOB (spareonly).
Especially bad block scans benefit from this change. On a 512MiB
SLC NAND device, the bad block scan took 1.5s less than before.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Since we do not support sub-page writes anyway, reading the page
back to the controller on SEQIN command is not required. Remove
the page read on SEQIN.
However, the column/page values relevant to the SEQIN command, hence
set the column/row address on SEQIN command.
Signed-off-by: Stefan Agner <stefan@agner.ch>
To improve performance we remember the current page in the buffer
and avoid reading it twice. This implicit page cache increases
complexity while does not increase performance in real world cases.
This patch removes that feature.
Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Calculate ecc strength according oobsize, but not hardcoded
which is not aligned with kernel driver
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <b37916@freescale.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Freeing allocated memory to priv before returning
from the function
Signed-off-by: Raghav Dogra <raghav@freescale.com>
[scottwood: removed unnecessary cast]
Signed-off-by: Scott Wood <scottwood@freescale.com>
On systems with caches enabled, NAND I/O may need to flush/invalidate
the cache during read/write operations. For this to work correctly, all
buffers must be cache-aligned. Fix nand_verify*() to allocate aligned
buffers.
This prevents cache alignment warnings from being spewed when using
U-Boot to write an updated version of itself to flash on NVIDIA Tegra
Seaboard (after perturbation of stack/data layout in current
u-boot-dm/next branch).
I have validatd (executed) nand_verify(), but I don't think I've executed
nand_verify_page_oob(); testing of that would be useful.
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Fixes: 59b5a2ad83 ("nand: Add verification functions")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Scott Wood <scottwood@freescale.com>
This printf() should have a newline at the end. Add it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Default name of spi flash like this "0:0", update it to "spi_flash@0:0".
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
Upto now flash sector_size is assigned from params which isn't
necessarily a sector size from vendor, so based on the SECT_*
flags from flash_params the erase_size will compute and it will
become the sector_size finally.
Bug report (from Bin Meng):
=> sf probe
SF: Detected SST25VF016B with page size 256 Bytes, erase size 4 KiB,
total 2 MiB, mapped at ffe00000
=> sf erase 0 +100
SF: 65536 bytes @ 0x0 Erased: OK
Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Reported-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
With SPI flash moving to driver model, commit fbb0991 "dm: Convert
spi_flash_probe() and 'sf probe' to use driver model" ignored the
SST flash-specific write op (byte program & word program), which
actually broke the SST flash from wroking.
This commit makes SST flash work again under driver model, by adding
SST flash-specific handling in the spi_flash_std_write().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Add a new member 'flags' in struct spi_flash to store the flash flags
during spi_flash_validate_params().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
This adds NAND boot support for LS2085AQDS, using SPL framework.
Details of forming NAND image can be found in README.
Signed-off-by: Scott Wood <scottwood@freescale.com>
[York Sun: Remove +S from defconfig after commit 252ed872]
Signed-off-by: York Sun <yorksun@freescale.com>
IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
two viz FCM and RUNTIME.FCM(Flash control machine) registers
are defined in PAGE0 and controls IFC generic functionality.
RUNTIME registers are defined in PAGE1 and controls NAND and
GPCM funcinality.
FCM and RUNTIME structures defination is common for IFC
version 1.4 and 2.0.
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
IFC 2.0 doubled the SRAM size, which means double the number of
ECCSTAT registers. Fix the resulting array overflow.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This reverts commit 562f8df18d.
Note: Even un-reverting this patch couldn't works as expected, based
on the latest testing from Heiko Schocher.
Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Need to check value of spi_setup_slave and spi_setup_slave_fdt.
If their return value 'bus' is NULL, there is no need to pass it
to following spi_flash_probe_tail.
If 'bus' is null, the original function flow is as following:
spi_flash_probe
|->spi_setup_slave
|->spi_probe_bus_tail
|->spi_flash_probe_slave
|->spi_free_slave
Alougth check the pointer in spi_free_slave is ok, checking the return value
of spi_setup_slave and spi_setup_slave_fdt is better.
Before this fix:
"
=> sf probe 0:2
FSL_QSPI: Not a valid cs !
SF: Failed to set up slave
data abort
pc : [<fff66dcc>] lr : [<fff7628c>]
reloc pc : [<87814dcc>] lr : [<8782428c>]
sp : fdf4fcf0 ip : e630396c fp : fe0d0888
r10: fffa2538 r9 : fdf4feb8 r8 : 02625a00
r7 : 00000002 r6 : fff94ec0 r5 : 00000000 r4 : 9355553c
r3 : 1af0593c r2 : cb3fe030 r1 : fff94eb8 r0 : e59ff018
Flags: nZCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
"
After this fix:
"
=> sf probe 0:2
FSL_QSPI: Not a valid cs !
Failed to initialize SPI flash at 0:2
"
No data abort using this patch.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Poll both the Read status and Flag status registers
for sucessful erase and program operations for the
Micron devices with E_FSR flag set in params table.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
CONFIG_SPI does not exist in Kconfig in the first place, so the
dependency "depends on DM && SPI" is never met, i.e., DM_SPI_FLASH
can never be enabled (unless you ignore the dependency in an illegal
way. See below.)
Actually, some defconfigs such as socfpga_*_defconfig define
CONFIG_DM_SPI_FLASH=y, but it never appears in the .config file
because of this wrong dependency.
On the other hand, all the Tegra boards enable DM_SPI_FLASH because
config DM_SPI_FLASH
default y
silently ignores the dependency.
Unfortunately, this style of CONFIG definition is abused everywhere
in U-Boot, so we easily miss such a wrong dependency.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Permit use of a udevice to talk to SPI flash. Ultimately we would like
to retire the use of 'struct spi_flash' for this purpose, so create the
new API for those who want to move to it.
Signed-off-by: Simon Glass <sjg@chromium.org>
In the case where the arch defines a custom map_sysmem(), make sure that
including just mapmem.h is sufficient to have these functions as they
are when the arch does not override it.
Also split the non-arch specific functions out of common.h
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a convenience function to access the private data that a uclass stores
for each of its devices. Convert over most existing uses for consistency
and to provide an example for others.
Signed-off-by: Simon Glass <sjg@chromium.org>
The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.
The SPL framework is supported.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Add support for on-flash bad block table. This makes U-Boot handle an existing
BBT correctly.
Signed-off-by: David Dueck <davidcdueck@googlemail.com>
Reviewed-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
CC: Boris BREZILLON <boris.brezillon@free-electrons.com>
CC: Josh Wu <josh.wu@atmel.com>
CC: Andreas Bießmann <andreas.devel@googlemail.com>
CC: Scott Wood <scottwood@freescale.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
Testing showed, that commands like STATUS made the buffer dirty
when executed with NFC_SECSZ set to the page size. It looks
like the controller transfers bogus data when this register
is configured. When setting it to 0, the buffer does not get
altered while the status command still seems to work flawless.
Signed-off-by: Stefan Agner <stefan@agner.ch>
The driver tries to re-use the page buffer by storing the page
number of the current page in the buffer. The page is only read
if the requested page number is not currently in the buffer. When
a block is erased, the page number is marked as invalid if the
erased page equals the one currently in the cache. However, since
a erase block consists of multiple pages, also other page numbers
could be affected.
The commands to reproduce this issue (on a written page):
> nand dump 0x800
> nand erase 0x0 0x20000
> nand dump 0x800
The second nand dump command returns the data from the buffer,
while in fact the page is erased (0xff).
Avoid the hassle to calculate whether the page is affected or not,
but set the page buffer unconditionally to invalid instead.
Signed-off-by: Stefan Agner <stefan@agner.ch>
This command is only enabled by one board, complicates the NAND code,
and doesn't appear to have been functioning properly for several
years. If there are no bad blocks in the NAND region being written
nand_write_skip_bad() will take the shortcut of calling nand_write()
which bypasses the special yaffs handling. This causes invalid YAFFS
data to be written. See
http://lists.denx.de/pipermail/u-boot/2011-September/102830.html for
an example and a potential workaround.
U-Boot still retains the ability to mount and access YAFFS partitions
via CONFIG_YAFFS2.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
The CONFIG_MTD_NAND_VERIFY_WRITE has been removed from Linux for some
time and a more generic method of NAND verification now exists in U-Boot.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Add nand_verify() and nand_verify_page_oob(). nand_verify() verifies
NAND contents against an arbitrarily sized buffer using ECC while
nand_verify_page_oob() verifies a NAND page's contents and OOB.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
The 'nandecc sw' command selects a software-based error correction
algorithm. By default, this is OMAP_ECC_HAM1_CODE_SW but some
platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their
software-based correction algorithm. Allow a user to be specific e.g.
# nandecc sw <hamming|bch8>
where 'hamming' is still the default.
Note: we don't just use CONFIG_NAND_OMAP_ECCSCHEME as it might be set
to a hardware-based ECC scheme---a little strange when the user
has requested 'sw' ECC.
Signed-off-by: Ash Charles <ashcharles@gmail.com>
Commit fb384c4720 introduced the use of
WAIT0 pin for determining whether the NAND is ready or not. This only
works if all NAND chips are connected to WAIT0. If some chips are
connected to the other available pin WAIT1, nand_wait() does not really
wait and prints a WARN_ON message.
This patch allows the board to provide configuration of which chip is
connected to which WAITx signal. For example, one can define in
include/configs/foo.h:
#define CONFIG_NAND_OMAP_GPMC_WSCFG 0,0,1,1
This would mean that chips using to CS0 and 1 are connected to WAIT0 and
chips with CS2 and 3 are connected to WAIT1.
Signed-off-by: Michal Sojka <sojka@merica.cz>
Acked-by: Stefan Roese <sr@denx.de>
Tested-by: Michal Vokáč <michal.vokac@comap.cz>
Cc: Tom Rini <trini@ti.com>
Now CONFIG_SPL_BUILD is not defined in Kconfig, so
"!depends on SPL_BUILD" and "if !SPL_BUILD" are redundant.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
When Kconfig for U-boot was examined, one of the biggest issues was
how to support multiple images (Normal, SPL, TPL). There were
actually two options, "single .config" and "multiple .config".
After some discussions and thought experiments, I chose the latter,
i.e. to create ".config", "spl/.config", "tpl/.config" for Normal,
SPL, TPL, respectively.
It is true that the "multiple .config" strategy provided us the
maximum flexibility and helped to avoid duplicating CONFIGs among
Normal, SPL, TPL, but I have noticed some fatal problems:
[1] It is impossible to share CONFIG options across the images.
If you change the configuration of Main image, you often have to
adjust some SPL configurations correspondingly. Currently, we
cannot handle the dependencies between them. It means one of the
biggest advantages of Kconfig is lost.
[2] It is too painful to change both ".config" and "spl/.config".
Sunxi guys started to work around this problem by creating a new
configuration target. Commit cbdd9a9737 (sunxi: kconfig: Add
%_felconfig rule to enable FEL build of sunxi platforms.) added
"make *_felconfig" to enable CONFIG_SPL_FEL on both images.
Changing the configuration of multiple images in one command is a
generic demand. The current implementation cannot propose any
good solution about this.
[3] Kconfig files are getting ugly and difficult to understand.
Commit b724bd7d63 (dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to
Kconfig) has sprinkled "if !SPL_BUILD" over the Kconfig files.
[4] The build system got more complicated than it should be.
To adjust Linux-originated Kconfig to U-Boot, the helper script
"scripts/multiconfig.sh" was introduced. Writing a complicated
text processor is a shell script sometimes caused problems.
Now I believe the "single .config" will serve us better. With it,
all the problems above would go away. Instead, we will have to add
some CONFIG_SPL_* (and CONFIG_TPL_*) options such as CONFIG_SPL_DM,
but we will not have much. Anyway, this is what we do now in
scripts/Makefile.spl.
I admit my mistake with my apology and this commit switches to the
single .config configuration.
It is not so difficult to do that:
- Remove unnecessary processings from scripts/multiconfig.sh
This file will remain for a while to support the current defconfig
format. It will be removed after more cleanups are done.
- Adjust some makefiles and Kconfigs
- Add some entries to include/config_uncmd_spl.h and the new file
scripts/Makefile.uncmd_spl. Some CONFIG options that are not
supported on SPL must be disabled because one .config is shared
between SPL and U-Boot proper going forward. I know this is not
a beautiful solution and I think we can do better, but let's see
how much we will have to describe them.
- update doc/README.kconfig
More cleaning up patches will follow this.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The patch c316f577b4 breaks
siemens boards because prefetch mode is not enabled.
I assume it breaks other boards as well that don't use
prefetch.
This patch sets read_buf to nand_read_buf if
NAND_OMAP_GPMC_PREFETCH is not defined.
Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
CC: Daniel Mack <zonque@gmail.com>
CC: Guido Martínez <guido@vanguardiasur.com.ar>
CC: Tom Rini <trini@ti.com>
CC: Heiko Schocher <hs@denx.de>
Expand the help messages for each driver. Add missing Kconfig for I2C,
SPI flash and thermal.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
As the PMECC hardware has different version. In SAMA5D4 chip, the PMECC ip
can generate 0xff pmecc ECC value for all 0xff sector.
According to this, add PMECC version check, if it's SAMA5D4 then we always
let PMECC hardware to correct it.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
At present we go through various contortions to store the SPI slave's chip
select in its private data. This only exists when the slave is active so
must be set up when it is probed. Until the device is probed we don't
actually know what chip select it will appear on.
However, now that we can support per-child platform data, we can use that
instead. This allows us to set up the chip select when the child is bound,
and avoid the messy contortions.
Unfortunately this is a fairly large change and it seems to be difficult to
break it down further.
Signed-off-by: Simon Glass <sjg@chromium.org>
These boards are still non-generic boards.
It is a good thing that we can drop board-specific hack code
from drivers/mtd/nand/nand_base.c
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Andrea "llandre" Marson <andrea.marson@dave-tech.it>
Enable GPMC's prefetch feature for NAND access. This speeds up NAND read
access a lot by pre-fetching contents in the background and reading them
through the FIFO address.
The current implementation has two limitations:
a) it only works in 8-bit mode
b) it only supports read access
Both is easily fixable by someone who has hardware to implement it.
Note that U-Boot code uses non word-aligned buffers to read data into, and
request read lengths that are not multiples of 4, so both partial buffers
(head and tail) have to be addressed.
Tested on AM335x hardware.
Tested-by: Guido Martínez <guido@vanguardiasur.com.ar>
Reviewed-by: Guido Martínez <guido@vanguardiasur.com.ar>
Signed-off-by: Daniel Mack <zonque@gmail.com>
[trini: Make apply again, use 'cs' fix pointed out by Guido]
Signed-off-by: Tom Rini <trini@ti.com>
Currently, "nand scrub" runs chip->scan_bbt at the end of
nand_erase_opts() even if NAND_SKIP_BBTSCAN flag is set.
It violates the intention of NAND_SKIP_BBTSCAN.
Move NAND_SKIP_BBTSCAN flag check to nand_block_checkbad() so that
chip->scan_bbt() is never run if NAND_SKIP_BBTSCAN is set.
Also, unset NAND_BBT_SCANNED flag instead of running chip->scan_bbt()
right after scrub. We can be lazier here because the BBT is scanned
at the next call of nand_block_checkbad().
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Commit 35c204d8a9 (nand: reinstate lazy bad block scanning)
broke NAND_BBT_USE_FLASH feature.
Its git-log claimed that it reinstated the change as by commit
fb49454b1b ("nand: reinstate lazy bad block scanning"), but it moved
"chip->options |= NAND_BBT_SCANNED" below "chip->scan_bbt(mtd);".
It causes recursion if scan_bbt does not find a flash based BBT
and tries to write one, and the attempt to erase the BBT area
causes a bad block check.
Reinstate commit ff49ea8977 (NAND: Mark the BBT as scanned prior to
calling scan_bbt.).
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Rostislav Lisovy <lisovy@merica.cz>
Cc: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Since commit ff94bc40af (mtd, ubi, ubifs: resync with Linux-3.14),
the "nand scrub" command has not been working.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
"err" was an unsigned variable, causing negative error codes to turn
into positive values, which are interpreted as an amount of succesfully
corrected bitflips (and thus not an error).
In particular, this resulted in that if the elm reports uncorrectable
errors (-EBADMSG), the MTD layer (and UBI) falsely succeeded.
Signed-off-by: Guido Martínez <guido@vanguardiasur.com.ar>
Reviewed-by: Stefan Roese <sr@denx.de>
Add the necessary flash entry for the Spansion S25FL164K
flash. Tested on Marvell 88F6218 based design.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Added S25FL116K flash and tested on Marvell 88F6281 based system.
Signed-off-by: Adnan Ali <adnan.ali@codethink.co.uk>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Add support for SST25WF040B-40I-SN flash.
Tested on T1024QDS board.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Removed ramtron driver since the EMK boards are
no longer been active, and these are the only boards
used this flash driver.
Commit details for EMK zap:
"ppc/arm: zap EMK boards"
(sha1: d58a9451e7)
Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
Enabled byte program support for sst flashes in sf.
Few controllers will only support BP, so this patch gives
a tx transfer flag to set the BP so-that sf will operate
on byte program transfer.
A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI
controller to use byte program op for SST flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Currently if SST flash advertises SST_WP flag in the params table
the word program command (ADh) with auto address increment will be
used for the flash write op. However some SPI controllers do not
support the word program command (like the Intel ICH 7), the byte
programm command (02h) has to be used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix
this so that the table in sf_params.c can be used correctly.
Reported-by: Jens Rottmann <Jens.Rottmann@adlinktech.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Few of the spi controllers are only supports array slow
read which is quite different behaviour compared to others.
So this fix on sf will correctly handle the slow read supported
controllers.
Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
'eccstat' array elements might be used uninitialized
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The functions to detect the state of the ready / busy signal is already
available but only used in the SPL case. Lets use it always, also for the
main U-Boot. As all boards should have this HW connection.
Testing on Siemens Draco (am335x) showed a small perfomance gain by using
this ready pin to detect the NAND chip state. Here the values tested on
Draco with Hynix 4GBit NAND:
Without NAND ready pin:
U-Boot# time nand read 80400000 0 400000
NAND read: device 0 offset 0x0, size 0x400000
4194304 bytes read: OK
time: 2.947 seconds, 2947 ticks
With NAND ready pin:
U-Boot# time nand read 80400000 0 400000
NAND read: device 0 offset 0x0, size 0x400000
4194304 bytes read: OK
time: 2.795 seconds, 2795 ticks
So an increase of approx. 5%.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
Merge struct s3c2410_nand and struct s3c2440_nand into one unified
struct s3c24x0_nand. While at it, fix up and rename the functions
to retrieve the NAND base address and fix up the s3c NAND driver to
reflect this change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
This patch disables subpage writes for vf610_nfc nand
driver. This is required, as without this fix, writing
unaligned u-boot images with DFU results in a hang.
Trying to write unalgined binary images also results
in a hang, without disabling subpage writes.
Patch has been tested on a Colibri VF61 module.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Some but not all of implementations of the Denali NAND controller
have hardware circuits to detect the device parameters such as
page_size, erase_size, etc. Even on those SoCs with such hardware
supported, the hardware is known to detect wrong parameters for some
nasty (almost buggy) NAND devices. The device parameters detected
during nand_scan_ident() are more trustworthy.
This commit sets some hardware registers to mtd->pagesize,
mtd->oobsize, etc. in the code between nand_scan_ident() and
nand_scan_tail().
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Chin Liang See <clsee@altera.com>
Some variants of the Denali NAND controller need some registers
set up based on the device information that has been detected during
nand_scan_ident().
CONFIG_SYS_NAND_SELF_INIT has to be defined to insert code between
nand_scan_ident() and nand_scan_tail(). It is also helpful to reduce
the difference between this driver and its Linux counterpart because
this driver was ported from Linux. Moreover, doc/README.nand recommends
to use CONFIG_SYS_NAND_SELF_INIT.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Chin Liang See <clsee@altera.com>
Commit ff94bc40af
("mtd, ubi, ubifs: resync with Linux-3.14")
accidentally reverted part of the commit
13f0fd94e3
("NAND: Scan bad blocks lazily.").
Reinstate the change as by commit
fb49454b1b
("nand: reinstate lazy bad block scanning")
Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
Acked-by: Heiko Schocher <hs@denx.de>
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does. This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.
Many of references of those macros must be fixed to suppress warnings.
We have two options:
- Use min, max, min3, max3 only when the arguments have the same type
(or add casts to the arguments)
- Use min_t/max_t instead with the appropriate type for the first
argument
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
The SPI function does the same thing, so we may as well just use the new
generic function. The 'cs' parameter was not actually used, so can be
dropped.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Heiko Schocher <hs@denx.de>
This code was not updated when the chip select handling was adjusted. Fix
it to call the correct function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Heiko Schocher <hs@denx.de>
The device id makes u-boot think that this chip needs
cfi_reverse_geometry(), which is not the case.
Add it to jedec_flash, so it is handled properly.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
ff94bc40af "mtd, ubi, ubifs: resync with Linux-3.14"
introduced the writebufsize field in struct mtd_info, which
is not initialized in the cfi_flash driver, which leads in
not working ubi on cfi flashes. Fix it
Signed-off-by: Heiko Schocher <hs@denx.de>
Reported-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
As in SAMA5D4 SoC, the gf table in ROM code can not be seen.
So, when we try to use PMECC, we need to build it when do
initialization.
Add a macro NO_GALOIS_TABLE_IN_ROM in soc header file. If it
is defined we will build gf table runtime.
The PMECC use the BCH algorithm, so based on the build_gf_tables()
function in lib/bch.c, we can build the Galois Field lookup table.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
device ready pin is signalling that the device is ready on state 1
not on 0. Simmiliar as it is in drivers/mtd/nand/nand_spl_simple.c
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
erase one nand block in spl code. keep it simple, as size matters
This is used on the upcoming taurus spl support.
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
