Commit graph

346 commits

Author SHA1 Message Date
Albert ARIBAUD
19d829fa60 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts:
	drivers/serial/serial.c

The conflict above was a trivial case of adding one init
function in each branch, and manually resolved in merge.
2013-09-05 11:15:26 +02:00
Amaury Pouly
49b0415a80 mmc: mxsmmc: Enable MMC HC support
Enable support for high-capacity eMMC and MMC cards. The MXS MMC
driver has no problem with those.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Amaury Pouly <amaury.pouly@gmail.com>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
2013-08-23 15:53:21 +02:00
York Sun
bf90256623 SPDX-License-Identifier: clean up license header
This patch cleans up license header in these files:
	board/freescale/p1022ds/spl.c
	drivers/mmc/fsl_esdhc_spl.c
	drivers/mtd/spi/fsl_espi_spl.c

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-20 10:15:37 -07:00
Ying Zhang
bb0dc1084f powerpc: mpc85xx: Support booting from SD Card with SPL
The code from the internal on-chip ROM. It loads the final uboot image
into DDR, then jump to it to begin execution.

The SPL's size is sizeable, the maximum size must not exceed the size of L2
SRAM. It initializes the DDR through SPD code, and copys final uboot image
to DDR. So there are two stage uboot images:
	* spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that
	ddr spd code can get the interleaving mode setting in env. It loads
	final uboot image from offset 96KB.
	* final uboot image, size is variable depends on the functions enabled.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 09:47:26 -07:00
Tom Rini
aaf5e82560 Merge branch 'master' of git://git.denx.de/u-boot-nds32 2013-07-25 08:51:51 -04:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Gabor Juhos
dbb713baa6 mmc: ftsdc010_mci: fix build error if CONFIG_FTSDC010_SDIO is not defined
The FTSDC010_DCR_FIFO_RST symbol is conditionally
defined in <faraday/ftsdc010.h> and it is available
available when CONFIG_FTSDC010_SDIO is enabled.

However the actual driver code unconditionally uses
the FTSDC010_DCR_FIFO_RST constant and this causes
build error if CONFIG_FTSDC010_SDIO is not enabled.

The following error happens when compiling for the
adp-ag101 board:

  ftsdc010_mci.c: In function 'ftsdc010_request':
  ftsdc010_mci.c:178: error: 'FTSDC010_DCR_FIFO_RST' undeclared (first use in this function)
  ftsdc010_mci.c:178: error: (Each undeclared identifier is reported only once
  ftsdc010_mci.c:178: error: for each function it appears in.)

The patch ensures that the FTSDC010_DCR_FIFO_RST
symbol gets used only if CONFIG_FTSDC010_SDIO is
defined.

Compile tested only.

Cc: Kuo-Jung Su <dantesu@faraday-tech.com>
Cc: Macpaul Lin <macpaul@andestech.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Reviewed-by: Kuo-Jung Su <dantesu@faraday-tech.com>
2013-07-24 11:49:17 +08:00
Dirk Behme
a61da72bda fsl_esdhc: Touch only relevant sys ctrl bits
Dealing with the sys ctrl register should touch only the
relevant bits and not accidently the whole register. On i.MX6,
the sys control register contains bits which shouldn't be reset to
0, e.g. SYS_CTRL[3-0] and IPP_RST_N (SYS_CTRL[23]).

Do this by read/modify/write instead of just a 32bit write.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-07-16 18:44:23 -05:00
Alexey Brodkin
ca6d4d0f8f drivers/mmc/dw_mmc - remove extra arch specific "asm/arch/clk.h" inclusion
1. No contents of "asm/arch/clk.h" is used within "dw_mmc.c".
2. If arch doesn't have "asm/arch/clk.h" driver won't build.

Without mentioned inclusion dw_mmc driver could be built for arches
other than ARM. For ARM driver still builds without it.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Mischa Jonker <mjonker@synopsys.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Cc: Amar <amarendra.xt@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-07-16 18:44:22 -05:00
Haijun.Zhang
b8e5b07225 Powerpc: eSDHC: Fix mmc read write err in uboot of T4240QDS board
Fill the right command type when using CMD12 to stop data transfer.

Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
CC: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-07-16 18:44:22 -05:00
Sascha Silbe
ff8fef5666 Fix block device accesses beyond 2TiB
With CONFIG_SYS_64BIT_LBA, lbaint_t gets defined as a 64-bit type,
which is required to represent block numbers for storage devices that
exceed 2TiB (the block size usually is 512B), e.g. recent hard drives.

For some obscure reason, the current U-Boot code uses lbaint_t for the
number of blocks to read (a rather optimistic estimation of how RAM
sizes will evolve), but not for the starting address. Trying to access
blocks beyond the 2TiB boundary will simply wrap around and read a
block within the 0..2TiB range.

We now use lbaint_t for block start addresses, too. This required
changes to all block drivers as the signature of block_read(),
block_write() and block_erase() in block_dev_desc_t changed.

Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
2013-06-26 10:26:06 -04:00
Tom Rini
348e47f766 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-06-22 07:38:12 -04:00
Albert ARIBAUD
69f14dc2fd Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
Conflicts:
	spl/Makefile
2013-06-19 12:53:59 +02:00
Rajeshwari Shinde
ed7bdc03eb MMC: DWMMC: Fix FIFO_DEPTH calculation
Current DWMMC driver used to give FIFO underrun/overrun error every 3rd time
for mmc rescan command.
In current code FIFO_DEPTH is getting calculated after reading the default FIFOTH
register and extracting the RX_WMARK bits from it i.e (RX_WMARK = FIFO_DEPTH/2 -1).
Instead of storing the correct value, we were recalculating the FIFO_DEPT each
time which is not correct.

Based on "[PATCH V9 3/9] DWMMC: Initialise dwmci and resolve EMMC read write issues"
http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/160247

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-17 11:03:42 +09:00
Tom Rini
dfdb3d37dd Merge branch 'master' of git://www.denx.de/git/u-boot-mmc 2013-06-14 16:06:49 -04:00
Stephen Warren
f866a46d6e mmc: report capacity for the selected partition
Enhance the MMC core to calculate the size of each MMC partition, and
update mmc->capacity whenever a partition is selected. This causes:

mmc dev 0 1 ; mmcinfo

... to report the size of the currently selected partition, rather than
always reporting the size of the user partition.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-13 16:52:19 -05:00
Andrew Gabbasov
01b77353e4 fsl_esdhc: Do not clear interrupt status bits until data processed
After waiting for the command completion event, the interrupt status
bits, that occured to be set by that time, are cleared by writing them
back. It is supposed, that it should be command related bits (command
complete and may be command errors).

However, in some cases the DMA already completes by that time before
the full transaction completes. The corresponding DINT bit gets set
and then cleared before even entering the loop, waiting for data part
completion. That waiting loop never gets this bit set, causing the
operation to hang. This is reported to happen, for example, for write
operation of 1 sector to upper area (block #7400000) of SanDisk Ultra II
8GB card.

The solution could be to explicitly clear only command related interrupt
status bits. However, since subsequent processing does not rely on
any command bits state, it could be easier just to remove clearing
of any bits at that point, leaving them all until all data processing
completes. After that the whole register will be cleared at once.

Also, on occasion, interrupts masking moved to before writing the command,
just for the case there should be no chance of interrupt between the first
command and interrupts masking.

Reported-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-13 16:52:19 -05:00
Fabio Estevam
c2137b10a4 mmc: fsl_esdhc: Fix hang after 'save' command
Since commit 48e0b2bd (powerpc/esdhc: Correct judgement for DATA PIO mode)
we see mx6 systems to hang after doing a 'save' command.

Revert this commit since the original 'ifdef' logic from 7b43db92
(drivers/mmc/fsl_esdhc.c: fix compiler warnings) was the correct one.

Reported-by: Tapani Utriainen <tapani@technexion.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-13 16:52:19 -05:00
Ruud Commandeur
a586c0aa21 mmc write bug fix
This patch fixes a bug related to mmc writes.

When doing fatwrites on an SD-Card, MMC bus problems can occur. Depending
on the size of the file, "MMC0: Bus busy timeout!" is reported, resulting
in an SD-Card that is no longer responding.
It appears to be, that set_cluster can be called with a size being zero.
That can be with a file that has a size being an exact multiple
(including 0) of the clustersize, but also for files that are smaller than
the size of one cluster.
The same problem occurs if the "mmc write" command is given with a block
count being 0.

By adding a check for the block count being zero in mmc_write_blocks
(drivers/mmc.c), this problem is solved.

Signed-off-by: Ruud Commandeur <rcommandeur@clb.nl>
Cc: Tom Rini <trini@ti.com>
Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Mats Karrman <Mats.Karrman@tritech.se>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-13 16:46:57 -05:00
Jagannadha Sutradharudu Teki
1695b29a5d mmc: sdhci: Enable 8-bit bus width only for 3.0 spec onwards
CAP register don't have any information for 8-bit buswidth support
on 2.0 sdhci spec, only from 3.0 onwards bit[18] got this information.

Due to this misassignment in sdhci, mmc is setting 8-bit buswidth using
mmc_set_bus_width even if controller doesn't support.
Below change has code information.
"mmc: Properly determine maximum supported bus width"
(sha1: 7798f6dbd5)

Bug log: <mmc plus and emmc cards)
-------
zynq-uboot> mmcinfo
Error detected in status(0x208100)!
Device: zynq_sdhci
Manufacturer ID: fe
.....

So enable 8-bit support only for 3.0 spec using CAP and for below 3.0
assign mmc->host_caps = MMC_MODE_8BIT on respective platform driver
if host have a support.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-13 16:44:49 -05:00
Amar
3690d6d66b MMC: APIs to support resize of EMMC boot partition
This patch adds APIs to access(open / close) and to resize boot partiton of EMMC.

Signed-off-by: Amar <amarendra.xt@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-13 17:35:14 +09:00
Amar
a082a2dde0 EXYNOS5: DWMMC: Added FDT support for DWMMC
This patch adds FDT support for DWMMC, by reading the DWMMC node data
from the device tree and initialising DWMMC channels as per data
obtained from the node.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Amar <amarendra.xt@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-13 17:35:14 +09:00
Amar
9c50e35ff2 DWMMC: Initialise dwmci and resolve EMMC read write issues
This patch enumerates dwmci and set auto stop command during
dwmci initialisation.
EMMC read/write is not happening in current implementation
due to improper fifo size computation. Hence modified the fifo size
computation to resolve EMMC read write issues.

Signed-off-by: Amar <amarendra.xt@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-13 17:35:13 +09:00
Balaji T K
a5d439c2d3 mmc: omap_hsmmc: Update pbias programming
Update pbias programming sequence for OMAP5 ES2.0/DRA7

Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:10 -04:00
Albert ARIBAUD
a19b0dd62d Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	common/cmd_fpga.c
	drivers/usb/host/ohci-at91.c
2013-05-30 14:45:06 +02:00
Haijun.Zhang
48e0b2bd2b powerpc/esdhc: Correct judgement for DATA PIO mode
The logic for the whether to configure for polling or DMA
was mistakenly reversed in this patch:

Commit 7b43db9211
drivers/mmc/fsl_esdhc.c: fix compiler warnings

Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
CC: Sun Yusong-R58495 <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-15 18:18:16 -05:00
Kuo-Jung Su
f6c3b34697 mmc: update Faraday FTSDC010 for rw performance
Faraday FTSDC010 is a MMC/SD host controller.
Although there is already a driver in current u-boot release,
which is modified from eSHDC and contributed by Andes Tech.
Its performance is too terrible on Faraday A36x SoC platforms,
so I turn to implement this new version of driver which is
10+ times faster than the old one.

It's carefully designed to be compatible with Andes chips,
so it should be safe to replace it.

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Andy Fleming <afleming@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-15 18:18:15 -05:00
Ying Zhang
ade8a1a6d3 drivers/mmc: move spl_mmc.c to common/spl
The mpc85xx repuires a special layout on the memory device that is
connected to the eSDHC controller interface. But the file spl_mmc.c
didn't handle this specfic case, there needs a special treatmen, in
the powerpc drictory. So, there is no longer to keep spl_mmc.c on
mpc85xx, CONFIG_SPL_FRAMEWORK is not set.

When CONFIG_SPL_MMC_SUPPORT is set and CONFIG_SPL_FRAMEWORK is not
set, there was an error in drivers/mmc/spl_mmc.c:

drivers/mmc/libmmc.o:(.got2+0x8): undefined reference to `spl_image'.

Now, the solution is to move the file "spl_mmc.c" to directory "common/spl".

Signed-off-by: Ying Zhang <b40530@freescale.com>
2013-05-15 08:41:03 -04:00
Bo Shen
93e3236ccb mmc: atmel_mci: add mmc card support
add mmc card support with atmel mci driver

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-05-12 16:48:11 +02:00
Bo Shen
aac4b69b2c mmc: atmel_mci: using IP version for different setting
Using IP version for different setting
  - Higher version supports 8bit mode
  - Higher version bus width setting is different

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-05-12 16:47:05 +02:00
Albert ARIBAUD
cac423a730 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-05-11 22:24:28 +02:00
Albert ARIBAUD
ec7023db8d Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts:
	drivers/mtd/nand/mxc_nand_spl.c
	include/configs/m28evk.h
2013-05-11 09:25:36 +02:00
Albert ARIBAUD
e825b100d2 Merge branch 'u-boot-pxa/master' into 'u-boot-arm/master' 2013-05-11 00:06:03 +02:00
Nishanth Menon
384bcae013 palmas: rename twl6035_mmc1_poweron_ldo with an palmas generic function
Since TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs,
rename twl6035_mmc1_poweron_ldo by a more generic palmas_mmc1_poweron_ldo
function.

Signed-off-by: Nishanth Menon <nm@ti.com>
2013-05-10 08:25:55 -04:00
Nishanth Menon
cb199102b0 twl6035: rename to palmas
TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs
Rename twl6035 to palmas to allow reuse across multiple current and
future platforms

As part of this change, change the CONFIG_TWL6035_POWER to
CONFIG_PALMAS_POWER and update usage of header file accordingly.

Signed-off-by: Nishanth Menon <nm@ti.com>
2013-05-10 08:25:54 -04:00
Fabio Estevam
88227a1d8a mmc: fsl_esdhc: Use calloc()
A malloc() followed by memset() can be simply replaced by calloc().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-06 16:26:25 -05:00
Jaehoon Chung
a68aac4947 mmc: sdhci: return error when failed add_sdhci().
If failed the add_host(), it is reasonable that return value of
add_sdhci().

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-06 16:26:24 -05:00
Vipin Kumar
1f4ca2547c sdhci: Add sdhci support for spear devices
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-06 16:26:24 -05:00
Davide Bonfanti
3ba36d603a davinci, mmc: Added a delay reading ext CSD register
Without this additional delay, some eMMC don't negotiate properly bus width
Tested on:
 - Toshiba THGBM2G8D8FBAIB
 - Toshiba THGBM4G4D1HBAR
 - Micron MTFC4GMVEA (the one giving the problem)
 - Hynix H26M64002BNR
 - SanDisk SDIN5E1-32G

Signed-off-by: Davide Bonfanti <davide.bonfanti@bticino.it>
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-06 16:26:24 -05:00
Che-Liang Chiou
e95504497e mmc: Split device init to decouple OCR-polling delay
Most of time that MMC driver spends on initializing a device is polling
OCR (operation conditions register).  To decouple this polling loop,
device init is split into two parts: The first part fires the OCR query
command, and the second part polls the result.  So the caller is now no
longer bound to the OCR-polling delay; he may fire the query, go
somewhere and then come back later for the result.

To use this, call mmc_set_preinit() on any device which needs this.

This can save significant amounts of time on boot (e.g. 200ms) by
hiding the MMC init time behind other init.

Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-06 16:12:38 -05:00
Egbert Eich
0472fbfd32 part/dev_desc: Add log2 of blocksize to block_dev_desc data struct
log2 of the device block size serves as the shift value used to calculate
the block number to read in file systems when implementing avaiable block
sizes.
It is needed quite often in file systems thus it is pre-calculated and
stored in the block device descriptor.

Signed-off-by: Egbert Eich <eich@suse.com>
2013-05-01 16:24:02 -04:00
Simon Glass
8bfa195e4e mmc: Define a constant for the maximum block size
The number 512 appears quite a bit in the mmc code. Add a constant for this
so that it can be used here and in other parts of the code (e.g. SPL code
which loads from mmc).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
2013-05-01 16:24:01 -04:00
Peter Korsgaard
2e222105c5 spl_mmc: cleanup variable types
block_read returns unsigned long, so it doesn't make sense to check for
< 0. and neither does marking the header structure as const and then
casting away the constness to load data into it.

Also cleanup some unneeded pointer casting while we're at it.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-01 16:24:00 -04:00
Michal Simek
293eb33fcb mmc: Add support for Xilinx Zynq sdhci controller
Add support for SD, MMC and eMMC card on Xilinx Zynq.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:27 +02:00
Stefan Roese
0499218dbc imx: Move some header files from arch-mxs to imx-common
The following headers are moved to a i.MX common location:

- regs-common.h
- regs-apbh.h
- regs-bch.h
- regs-gpmi.h
- dma.h

This way this header can be re-used also by other i.MX platforms.
For example the i.MX6 which will need it for the upcoming NAND
support.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 10:22:22 +02:00
Jaehoon Chung
1741c64d64 mmc: check the revision for sd3.0
Support to check whether the SD3.0 or not.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Rommel Custodio <sessyargc@gmail.com>
2013-04-17 10:58:51 -04:00
Jaehoon Chung
64f4a6192f mmc: support the correct card version for eMMC
eMMC vesrion is supported up to v4.5.
But bootloader isn't saw the exact eMMC version.
After applied this patch,
if use the mmcinfo command, then can see the exactly mmc version.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Rommel Custodio <sessyargc@gmail.com>
2013-04-17 10:58:51 -04:00
Albert ARIBAUD
345be0b267 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-04-14 11:45:06 +02:00
Andrew Gabbasov
9b74dc56fb fsl_esdhc: Fix DMA transfer completion waiting loop
Rework the waiting for transfer completion loop condition
to continue waiting until both Transfer Complete and DMA End
interrupts occur. Checking of DLA bit in Present State register
looks not needed in addition to interrupts status checking,
so it can be removed from the condition. Also, DMA Error
condition is added to the list of data errors, checked in the loop.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2013-04-14 11:22:47 +02:00
Eric Nelson
54899fc8fe fsl_esdhc: flush cache after IO completion
The cache should invalidate the read buffer for
the SD card interface after the transfer complete,
not command-complete.

Tested-by: Andrew Gabbasov <Andrew_Gabbasov@mentor.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-04-14 11:20:53 +02:00