Let common code set the machine ID.
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
As only one RAM bank is used we can rely on the code from arch/arm/lib/board.c
Cc: Matthias Weisser <weisserm@arcor.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Let common code set the machine ID.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
Add NAND SPL support to the devkit8000 config
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Without this change CS's configured for synchronous clocking cannot
read data.
Signed-off-by: Philip Balister <philip@opensdr.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The existing timing does not quite meet the minimum requirements
in the LAN9221 datasheet. The timing in this patch solves problems
noticed on some parts. The patch also combines the CS configuration
for the overo and igep0020 boards per request.
Signed-off-by: Philip Balister <philip@opensdr.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch adds support for 88E3015 PHY for Marvell GplugD board.
This patch depends on series of patch which adds support for Marvell
GuruPlug-Display.
Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
This patch enables ethernet support for Marvell GplugD board. Network
related commands works.
Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
Update MPC8349EMDS to use unified DDR driver instead of spd_sdram.c.
The unified driver can initialize data using DDR controller. No need to
use DMA if just to initialze for ECC.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The P2041RDB has almost identical setup for TLB, LAWS, and PCI with
other P-Series CoreNet platforms.
The only difference between P2041RDB & P3041DS/P4080DS/P5020DS is the
CPLD vs PIXIS FPGA which we can handle via some simple #ifdefs in the
TLB and LAW setup tables.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We currently support 4 SoC/Boards from the P-Series of QorIQ SoCs that
are based on the 'CoreNet' Architecture: P2041RDB, P3041DS, P4080DS, and
P5020DS. There is a significant amount of commonality shared between
these boards that we can refactor into common code:
* Initial LAW setup
* Initial TLB setup
* PCI setup
We start by moving the shared code between P3041DS, P4080DS, and P5020DS
into a common directory to be shared with other P-Series CoreNet boards.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We shouldn't be setting execute permissions on TLB entries that will not
actually have any code run from them.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
RDIMM has different timing parameters from UDIMM. Create new tables for
RDIMMs. Single-, dual- and quad-rank RDIMMs have been verified with speeds
from 800 to 1333MT/s. Speed table expands to include 1600MT/s for future
use. Single- and quad-rank RDIMM entries are copied into UDIMM tables for
future use.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
DDR RCW varies at different speeds. It is common for all platform. Move it
out from corenet_ds.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support for RGMII, SGMII and XAUI Ethernet on P2041RDB board.
The five dTSEC can be routed to two on-board RGMII phy, three on-board
SGMII phy or four SGMII phy on SGMII riser card according to different
serdes protocol configuration and board lane configuration. Also updated
the device tree to direct the Fmac MAC to the correct PHY.
Removed CONFIG_SYS_FMAN_FW as its not used anywhere.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The P1023 has two 1G ethernet controllers the first can run in
SGMII, RGMII, or RMII. The second can only do SGMII & RGMII.
We need to setup a for SoC & board registers based on our various
configuration for ethernet to function properly on the board.
Removed CONFIG_SYS_FMAN_FW as its not used anywhere.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Lei Xu <B33228@freescale.com>
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P3041DS &
P5020DS ("Hydra").
The lane_to_slot[] array is initialized dynamically, since board switches
can be used to control the muxing of SERDES lanes to slots.
The BRDCFG1 PIXIS register is used to route the MII bus to the appropriate
slot. The SERDES configuration is queried to help determine the routing
between MACs and slot/phy combination.
If a XAUI card is inserted, muxing for that card is enabled and never
turned off. The PHY address for the 10G XAUI card depends on the slot in
which it's inserted. If it's in slot 1, the address is 4. If it's in
slot 2, the address is 0.
Update the MDIO routing in the P3041DS and P5020DS device trees based on
the board-level muxing. The SERDES configuration determines which
SGMII/XGMII boards are located in which slots, and so the MDIO bus needs
to be muxed correctly whenever talking to a PHY connected to any Fman MAC.
The Fman Ethernet nodes in the device tree also need to be routed to the
correct PHYs.
Removed CONFIG_SYS_FMAN_FW as its not used anywhere.
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P4080DS.
The board supports add-on cards for SGMII and XAUI functionality. Which
slots on the board these cards are in is a function of the SERDES option
selected and muxes on the board.
Additionally because of the high-configurablity which MDIO bus one is
connected to is "selected" via an FPGA register. We create dummy MDIO
bus for the phy layer and hide the mux manipulation in this dummy layer.
Add fman fdt helper function in board common code it'll be used by several
freescale boards that do various muxing of the MDIO signals based on which
controller/interface one is trying to talk to.
Removed CONFIG_SYS_FMAN_FW as its not used anywhere.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove unnecessary or dead code/includes.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We shouldn't be setting execute permissions on TLB entries that will not
actually have any code run from them.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Boot methods supported: NOR Flash, SPI Flash and SDCARD
This patch adds the following basic interfaces:
DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, SPI Flash.
P1010RDB Overview
-----------------
1Gbyte DDR3 (on board DDR)
Local Bus (IFC):
32Mbyte 16bit NOR flash
32Mbyte SLC NAND Flash
64KB CPLD device(GPCM interface)
SPI Flash:
128 Mbit SPI Flash memory
SD/MMC:
connector to interface with the SD memory card
SATA:
1 internal SATA connect to 2.5. 160G SATA2 HDD
1 eSATA connector to rear panel
USB 2.0:
x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface.
x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet
eTSEC:
eTSEC1: Connected to RGMII PHY VSC8641XKO
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY VSC8221
eCAN:
Two DB-9 female connectors for Field bus interface
UART:
supports two UARTs up to 115200 bps for console
TDM:
2 FXS ports connected via an external SLIC to the TDM interface.
SLIC:
SPI SLIC
I2C:
Serial EEprom
Real time clock
256 Kbit M24256 I2C EEPROM
PCIe:
PCIe and mPCIe connectors.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The following boards share a common design but with minor variations
between them:
P1020MSBG-PC
P1020RDB-PC
P1020UTM-PC
P1021RDB-PC
P1024RDB
P1025RDB
P2020RDB-PC
The P1020RDB-PC shares its roots in the existing P1020RDB board design,
however uses DDR3 instead of DDR2.
P2020RDB-PC differs from the P102x RDB-PC with 64-bit DDR and 100Mhz SYSCLK.
Key features on these boards include:
* DDR3
* NOR flash
* NAND flash (on RDB's only)
* SPI flash (on RDB's only)
* SDHC/MMC card slot
* VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB)
* PCIE slot and mini-PCIE slots
As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM
is used to store SPD data. In case of absent or corrupted SPD, falling back
to timing data embedded in the source code will be used. Raw timing data is
extracted from DDR chip datasheet. Different speeds of DDR are supported
with this approach. ODT option is forced to fit this set of boards, again
because they don't have regular DIMMs.
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet
specification for writing timing.
VSC firmware Address is defined by default in config file for eTSEC1.
SD width is based off DIP switch. DIP switch is detected on the
board by reading i2c bus and setting the appropriate mux values.
Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC
have pins multiplexing. QE function needs to be disabled to access Nor Flash
and CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below
'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Zhao Chenhui <b26998@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Tang Yuantian <b29983@freescale.com>
Signed-off-by: ramneek.mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Akhil Goyal <akhil.goyal@freescale.com>
Since commit d388298a59 by
Stefano Babic this file is no longer needed so delete it.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Loïc Minier <loic.minier@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The MAC address stored in the inventory eeprom begins at offset 1.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Wolfgang Denk <wd@denx.de>
Result of running the following command to address Wolfgang's
comment about camel case:
for file in `find . | grep '\.[chS]$'`; do perl -i -pe
's/(green|yellow|red|blue)_LED_(on|off)/$1_led_$2/g' $file; done
Discussion:
http://patchwork.ozlabs.org/patch/84988/
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
omap4: fix pad configuration settings for SDP and Panda
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sebastien Jan <s-jan@ti.com>
Signed-off-by: David Anders <x0132446@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Make use of GPIO framework and avoid the following build error:
tx25.c: In function 'tx25_fec_init':
tx25.c:73: error: dereferencing pointer to incomplete type
tx25.c:74: error: dereferencing pointer to incomplete type
tx25.c:75: error: dereferencing pointer to incomplete type
tx25.c:76: error: dereferencing pointer to incomplete type
tx25.c:83: error: dereferencing pointer to incomplete type
tx25.c:84: error: dereferencing pointer to incomplete type
tx25.c:114: error: dereferencing pointer to incomplete type
tx25.c:115: error: dereferencing pointer to incomplete type
tx25.c:116: error: dereferencing pointer to incomplete type
tx25.c:117: error: dereferencing pointer to incomplete type
tx25.c:124: error: dereferencing pointer to incomplete type
tx25.c:125: error: dereferencing pointer to incomplete type
tx25.c:126: error: dereferencing pointer to incomplete type
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Fix build problem:
nand_spl/board/davinci/da8xxevm/hawkboard_nand_spl.c: In function 'board_init_f':
nand_spl/board/davinci/da8xxevm/hawkboard_nand_spl.c:132: warning: implicit declaration of function 'nand_boot'
nand_spl/board/davinci/da8xxevm/hawkboard_nand_spl.c:133: warning: 'noreturn' function does return
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Syed Mohammed Khasim <sm.khasim@gmail.com>
Cc: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Fix these:
cm4008.c: In function 'board_eth_init':
cm4008.c:79: warning: implicit declaration of function 'ks8695_eth_initialize'
cm41xx.c: In function 'board_eth_init':
cm41xx.c:79: warning: implicit declaration of function 'ks8695_eth_initialize'
While we are at it, sort include list in netdev.h
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Greg Ungerer <greg.ungerer@opengear.com>
The pointer to the flash based bootargs should be a "char *", not unsigned.
Fixes:
cm41xx.c: In function ‘env_flash_cmdline’:
cm41xx.c:67: warning: pointer targets in passing argument 2 of ‘setenv’ differ in signedness
Signed-off-by: Greg Ungerer <greg.ungerer@opengear.com>
The pointer to the flash based bootargs should be a "char *", not unsigned.
Fixes:
cm4008.c: In function ‘env_flash_cmdline’:
cm4008.c:67: warning: pointer targets in passing argument 2 of ‘setenv’ differ in signedness
Signed-off-by: Greg Ungerer <greg.ungerer@opengear.com>
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/mpc8610hpcd: set pci1_hose.config_table after fsl_setup_hose
powerpc/mpc8548cds: set pci1_hose.config_table after fsl_setup_hose
powerpc/mpc8568mds: set pci1_hose.config_table after fsl_setup_hose
Use _bss_start_ofs as the size of the boot loader code+data that we want
to protect in the flash. This replaces use of the no longer defined
_armboot_start.
Fixes:
flash.c: In function ‘flash_init’:
flash.c:75: error: ‘_bss_start’ undeclared (first use in this function)
flash.c:75: error: (Each undeclared identifier is reported only once
flash.c:75: error: for each function it appears in.)
flash.c:75: error: ‘_armboot_start’ undeclared (first use in this function)
Signed-off-by: <greg.ungerer@opengear.com>
The function fsl_setup_hose clears the variable pci1_hose.
Set pci1_hose.config_table after it.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The function fsl_setup_hose clears the variable pci1_hose.
Set pci1_hose.config_table after it.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The function fsl_setup_hose clears the variable pci1_hose.
Set pci1_hose.config_table after it.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The out-of-tree build fails because the Makefiles in question depend on
source files of another directory but do not explicitly mkdir that
directory.
As a matter of fact, other Makefiles under board/*/ directory that refer
to source files under another directory explicitly call mkdir.
This patch adds explicit mkdir's to the Makefiles in question, and
verifies that out-of-tree build is working.
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
commit 0edf8b5b2f breaks
building on a different directory with the O= parameter.
The patch wil fix this issue, generating always asm-offsets.h before
the other targets.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Matthias Weisser <weisserm@arcor.de>
CC: Wolfgang Denk <wd@denx.de>
The ALPR custom FPGA code was missed by commit e6a857d "fpga:
constify to fix build warning" resulting in such warnings:
fpga.c:226: warning: initialization from incompatible pointer type
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Commit 58c583b "net: Check network device driver name" increased the
code size and broke building for the ETX094 board.
Adjust the linker script to make it build again.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Commit 09c2e90 "unify version_string" defines a default value for
CONFIG_IDENT_STRING in version.h, so any private settings musty be
done before including this file. Move the include for version.h after
the one for common.h to fix the build problem.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
* 'master' of git://git.denx.de/u-boot-coldfire:
ColdFire:Clean up the CONFIG_STANDALONE_LOAD_ADDR usage
ColdFire:Add mb for 5253 dram initialization
ColdFire:Define the DM9000 byteswap for M5253 board.
ColdFire:Update the env settings for several boards.
ColdFire:disable the NFS define for 52277 board.
ColdFire:Update the timer_init since it was unified.
ColdFire: Cleanup for partial linking and --gc-sections
ColdFire: Update compile flags for each CPUs
ColdFire:Fix the configuration broken for some boards.
The dram initialization sequence should be in order.
This patch add mb for the dram intialization code to make
sure the compiler do not disorder the code.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Introduce the --gc-sections for ColdFire platform and clean up the
corresponding lds file.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
* Read the led output state from GPIO instead saving state in memory when it is [re]set
* Added a toggle option to the led command
Previous discussion:
http://lists.denx.de/pipermail/u-boot/2011-May/093068.html
Changes since v1:
Fixed checkpatch errors
Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com>
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Fixed USR0/USR1 to be LED 0/1 respectively
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Based on patches from Syed Mohammed Khasim (khasim@ti.com).
Configures the output of the BeagleBoard DVI to be orange.
Configures the output of the BeagleBoard S-Video to be a colorbar.
Changed display_init to beagle_display_init as suggested by Igor Grinberg:
http://www.mail-archive.com/u-boot@lists.denx.de/msg51446.html
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Based on commit f1099c7c43caf5bac3bf6a65aa266fade4747072
Author: Greg Turner <gregturner@ti.com>
Date: Tue May 25 09:19:06 2010 -0500
New u-boot command for status of USER button on BeagleBoard-xM
Modified bootcmd to check the staus at boot time and set
filename of the boot script.
* Moved to a BeagleBoard specific file.
* Removed changes to default boot command from adding userbutton
command.
* Made to handle pre-xM boards.
* Flipped polarity of the return value to avoid confusion. Success (0)
is when the button is pressed. Failure (1) is when the button is NOT
pressed.
* Used latest revision getting function.
* Used latest macros for board revision.
* Added xM-C revision definition (optional, since it was default)
* updated default configuration with UserButton functionality
* Added a separate bootenv variable to load a user defined .txt file
* Added an example, showing how a different environment file can be loaded with
the user button pressed
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com>
Cc: Greg Turner <gregturner@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This fixes display problems in linux
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The below patch reverses the order of two segments in the board file.
Output pins need to have their values initialized, before they are
exposed to the logic outside the chip.
Signed-off-by: Bob Feretich <bob.feretich@rafresearch.com>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
NOR to work on Rev.3 EVM. When GP0[11] is low,
the SD0 interface will not work, but NOR flash will.
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
add support for DSP wake-up by default on DA850/OMAP-L138
during board initialization. Enable hwconfig environment and added
extra env setting through CONFIG_EXTRA_ENV_SETTINGS.
To prevent DSP from being woken up,set the environment variable as,
set hwconfig "dsp:wake=no"
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Add pin-mux support for NOR in board file and correspanding
macros to use NOR boot mode in configuration file.
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Switch from the legacy omap3 mmc driver to the new generic omap hsmmc
driver. This patch is based on the work done for Beagle, etc.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Switch from the legacy omap3 mmc driver to the new generic omap hsmmc
driver. This patch is based on the work done for Beagle, etc.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Switch from the legacy omap3 mmc driver to the new generic omap hsmmc
driver. This patch is based on the work done for Beagle, etc.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Switch from the legacy omap3 mmc driver to the new generic omap hsmmc
driver. This patch is based on the work done for Beagle, etc.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Switch from the legacy omap3 mmc driver to the new generic omap hsmmc
driver. This patch is based on the work done for Beagle, etc.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Switch from the legacy omap3 mmc driver to the new generic omap hsmmc
driver. This patch is based on the work done for Beagle, etc.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Switch from the legacy omap3 mmc driver to the new generic omap hsmmc
driver. This patch is based on the work done for Beagle, etc.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Switch from the legacy omap3 mmc driver to the new generic omap hsmmc
driver. This patch is based on the work done for Beagle, etc.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
