This patch adds support for software ECC to the nand_spl_simple driver.
To enable this one have to define CONFIG_SPL_NAND_SOFTECC.
Tested on OMAP3.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Acked-by: Scott Wood <scottwood@freescale.com>
For some reason code setting the speed based on the PHY feedback causes
troubles on AM3517 so hardcode 100Mbps for now.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
DaVinci EMAC is present on TI AM35xx SoCs (ARMv7) which run with D-Cache
enabled by default. So we have to take care and flush/invalidate the
cache before/after the DMA operations.
Please note that the receive buffer alignment to 32 byte boundary comes
from the old driver version I don't know if it is really needed or
alignment to cache line size is enough.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Added noop implementation for dcache operations that will buzz
about missing real implementation and disable the dcache.
This fixes compilation of DaVinci EMAC driver on arm926ejs.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
On AM35xx CPPI RAM had different addresses when accessed from the CPU
and from the EMAC. We need to account this to deal with the buffer
descriptors correctly.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
DaVinci EMAC is found not only on DaVinci SoCs but on some OMAP3 SoCs
also. This patch moves common defines from arch-davinci/emac_defs.h to
drivers/net/davinci_emac.h
DaVinci specific PHY drivers hacked to include the new header. We might
want to switch to phylib in future.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
The previous commit changed it to "zero two" instead of the proper "Oh two". This was completely broken!
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
Acked-by: Tom Rini <trini@ti.com>
Fix:
arch/arm/cpu/arm926ejs/davinci/libdavinci.o: In function `timer_init':
/work/agust/git/u-boot/arch/arm/cpu/arm926ejs/davinci/timer.c:62:
undefined reference to `davinci_arm_clk_get'
drivers/i2c/libi2c.o: In function `i2c_init':
/work/agust/git/u-boot/drivers/i2c/davinci_i2c.c:102:
undefined reference to `davinci_arm_clk_get'
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
This patch removes the definition of stack sizes for
irq and fiq if the CONFIG_USE_IRQ is undefined before.
Acked-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Thomas Weber <weber@corscience.de>
Acked-by: Luca Ceresoli <luca.ceresoli@comelit.it>
This patch removes the unused definition of SDRC_R_C_B
from the config files.
Acked-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Thomas Weber <weber@corscience.de>
Acked-by: Luca Ceresoli <luca.ceresoli@comelit.it>
Acked-by: Tom Rini <trini@ti.com>
This patch removes the CONFIG_OMAP3430, because it is unused.
Acked-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Thomas Weber <weber@corscience.de>
Acked-by: Luca Ceresoli <luca.ceresoli@comelit.it>
The value from TRIM is not working for some 4430 silicons.
So, override with hw team recommended value. However, for
4460 TRIM value shall be used as long as the part is trimmed
This fixes boot problem on some OMAP4430 ES2.0 Panda boards
out there.
Cc: Steve Sakoman <sakoman@gmail.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
Change the CONFIG_SYS_TEXT_BASE and the addresses of SDRAM
buffers used by SPL(heap and BSS) keeping in mind the
following requirements:
1. Make sure that SPL's heap and BSS doesn't come in the way
of Linux kernel, which is typically loaded at 0x80008000. This
will be important when SPL directly loads kernel.
2. Align the CONFIG_SYS_TEXT_BASE between TI internal
U-Boot and mainline U-Boot. This avoids a lot of confusion
and allows for the inter-operability of x-loader, SPL,
internal U-Boot, mainline U-Boot etc. The internal U-Boot's
address can not be changed to that of mainline U-Boot
as internal U-Boot doesn't have relocation and 0x80100000
used by mainline U-Boot will clash with kernel
3. Assume only a minimum amount of memory that may be available
on any practical OMAP4/5 board in future too. We are assuming
a minimum of 128 MB of memory
Signed-off-by: Aneesh V <aneesh@ti.com>
There was a typo in the EMIF driver. It went un-noticed
because it affected only when automatic detection is enabled
and even then half the memory was configured and identified
properly.
Reported-by: Rockefeller <rockefeller.lin@innocomm.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
TPS power IC is controlled using a GPIO (gpio_wk7).
This GPIO should be maintained at logic 1 always. As
such an internal pull-up on this pin will do the job,
driving the GPIO outuput is not needed. This will avoid
the need of using GPIO library in SPL and also may
save some power.
Signed-off-by: Aneesh V <aneesh@ti.com>
Improve the tool that finds multiplier and divider for PLLs:
The previous algorithm could get stuck on local maxima
and required the user to specify the tolerance. Improve
the algorithm to go through the entire search space and find
the optimal solution.
Signed-off-by: Aneesh V <aneesh@ti.com>
The vector is not correctly setup in armv7 except for OMAP3.
Correcting this.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Aneesh V <aneesh@ti.com>
This allows SPL to have default implementation of
save_boot_params(), useful for SoCs that do
not intend to override this default implementation
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Aneesh V <aneesh@ti.com>
We were not disabling external caches before jumping
to kernel. We were flushing all caches including
external caches and disabling caches globally in
CP15 System Control register. Apparently this is not
enough.
The bootstrap loader in Linux kernel that does decompression
enables data-caches again, flush them after use and disable
them before jumping to kernel proper. However, it's not aware
of the external caches.
Since we have left external cache enabled, external cache will
get used once caches are enabled globally, but it's not flushed
because decompressor is not aware of external caches. When it
jumps to kernel with caches disabled globally, we have stale
data in the external cache and a coherency problem.
This was breaking the boot for OMAP4 with latest mainline
kernel. The solution is to disable external caches in
cleanup_before_linux(). With this fix kernel is booting again.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Aneesh V <aneesh@ti.com>
This patch fixes the clear bss loop for bss sections that have
zero length, i.e., where __bss_start == __bss_end__.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
V2: Add missing u-boot-spl.lds, convert bitshifts to division,
convert to spl_onenand_load_image()
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefan Herbrechtsmeier <sherbrec@cit-ec.uni-bielefeld.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
The start.S on PXA was very obscure. This reworks it back to be close to arm1136
start.S and others.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
V2: Don't compile in relocation support if building SPL
The board is unmaintained and maintainer doesn't respond.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
The board is unmaintained and maintainer doesn't respond.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
The board is unmaintained and maintainer doesn't respond.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
The board is unmaintained and maintainer doesn't respond.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
