Commit graph

1820 commits

Author SHA1 Message Date
Tom Rini
0ce4af99c0 Merge branch 'master' of git://git.denx.de/u-boot-imx 2014-10-27 09:08:42 -04:00
Tom Rini
5aa7bece10 Merge branch 'master' of git://git.denx.de/u-boot-ti 2014-10-27 09:05:43 -04:00
Tom Rini
674ca84d11 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2014-10-27 09:05:20 -04:00
Marek Vasut
34584d190d arm: socfpga: Zap spl.h and ad-hoc related syms
Switch to the common spl.h file and zap the arch/spl.h . Since the arch/spl.h
contained various ad-hoc symbols, zap those symbols as well and rework the
board configuration a little so it doesn't depend on them.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Pavel Machek <pavel@denx.de>
2014-10-27 02:26:24 +01:00
Tom Rini
d0796defbe Merge http://git.denx.de/u-boot-sunxi 2014-10-26 14:13:24 -04:00
Tom Rini
1fba907f9a Merge branch 'master' of git://git.denx.de/u-boot-usb 2014-10-26 14:12:18 -04:00
Tom Rini
84a6df09c7 Merge git://git.denx.de/u-boot-dm
Fix a trivial conflict over adding <dm.h>

Conflicts:
	arch/arm/cpu/armv7/omap3/board.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-10-26 14:03:08 -04:00
Jeroen Hofstee
7b8119ddf5 tegra: add proto for pin_mux_mmc
while at it, fix a typo

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-10-25 15:27:37 -04:00
Jeroen Hofstee
49c4bc3a6c arm: vectors: provide protypes from vectors.S
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-10-25 15:27:36 -04:00
Jeroen Hofstee
bf8550287d omap3: board: add missing include and proto
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-10-25 15:27:35 -04:00
Jeroen Hofstee
67c398d2c0 arch-mx: add missing include
mxs_wait_mask_set and friends need a declaration
of struct mxs_register_32.

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-10-25 07:27:37 -04:00
Hans de Goede
9e54f6ee01 sunxi: Add clock_get_pll5p() function
This is a preparation patch for making the pll5 "p" divisor configurable
through Kconfig.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:37:24 +02:00
Chen-Yu Tsai
c757a50bd1 ARM: sunxi: Add support for using R_UART as console
The A23 only has UART0 muxed with MMC0. Some of the boards we
encountered expose R_UART as a set of pads.

Add support for R_UART so we can have a console while using mmc.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:39 +02:00
Chen-Yu Tsai
472ed0641e ARM: sunxi: Allow specifying module in prcm apb0 init function
The prcm apb0 controls multiple modules. Allow specifying which
modules to enable clocks and de-assert resets so the function
can be reused.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:39 +02:00
Hans de Goede
e373aad32a ARM: sunxi: Add support for R_PIO gpio banks
The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO
or R_PIO, which handles pin banks L and beyond.

Also add a clear description about SUNXI_GPIO_BANKS, stating it only
counts the number of pin banks in the _main_ pin controller.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: expanded commit message]
[wens@csie.org: add pin bank M and expand comments]
[wens@csie.org: add comment on SUNXI_GPIO_BANKS macro]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:39 +02:00
Chen-Yu Tsai
8ebe4f4292 ARM: sunxi: Add basic A23 support
The basic blocks of the A23 are similar to the A31 (sun6i). Re-use
sun6i code for initial clock, gpio, and uart setup.

There is no SPL support for A23, as we do not have any documentation
or sample code for DRAM initialization.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:39 +02:00
Chen-Yu Tsai
e637b30b9c mmc: sunxi: Add support for sun8i (A23)
The Allwinner A23 SoC has reset controls like the A31 (sun6i).
The FIFO address is also the same as sun6i.

Re-use code added for sun6i.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:39 +02:00
Chen-Yu Tsai
7f87ad354b ARM: sunxi: Add sun8i (A23) UART0 pin mux support
UART0 pin muxes on the A23 have a different function value.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:38 +02:00
Chen-Yu Tsai
78c396a113 ARM: sunxi: Fix reset command on sun6i/sun8i
The watchdog on sun6i/sun8i has a different layout.

Add the new layout and fix up the setup functions so that reset works.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
[ ijc -- removed sun5i workaround from sun6i/sun8i codepath as discussed ]
2014-10-24 09:35:38 +02:00
Chen-Yu Tsai
4cdefba86d ARM: sunxi: Add sun6i/sun8i timer block register definition
The RTC hardware has been moved out of the timer block on sun6i/sun8i.
In addition, there are more watchdogs available.

Also note that the timer block definition is not completely accurate
for sun5i/sun7i. Various blocks are missing or have been moved out.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:38 +02:00
Chen-Yu Tsai
2b679f9fa4 ARM: sunxi: Move watchdog register definitions to separate file
On later Allwinner SoCs, the watchdog hardware is by all means a
separate hardware block, with its own address range and interrupt
line.

Move the register definitions to a separate file to facilitate
supporting newer SoCs.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:38 +02:00
Hans de Goede
bbff84b3b0 sunxi: Use PG3 - PG8 as io-pins for mmc1
None of the known sunxi devices actually use mmc1 routed through PH, where
as some devices do actually use mmc1 routed through PG, so change the routing
of mmc1 to PG. If in the future we encounter devices with mmc1 routed through
PH, we will need to change things to be a bit more flexible.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:38 +02:00
Hans de Goede
e79c7c8810 sunxi: When we've both mmc0 and mmc2, detect from which one we're booting
sunxi SOCs can boot from both mmc0 and mmc2, detect from which one we're
booting, and make that one "mmc dev 0" so that a single u-boot binary can
be used for both the onboard eMMC and for external sdcards.

When we're booting from mmc2, we make it dev 0 because that is where the SPL
will load the tertiary payload (the actual u-boot binary in our case) from,
see: common/spl/spl_mmc.c, which has dev 0 hardcoded everywhere.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:38 +02:00
Chen-Yu Tsai
ba1e40fdd3 ARM: sun6i: Define UART0 pins for A31
UART0 is the default debug/console UART on the A31.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:38 +02:00
Hans de Goede
1d1bd42eb0 ARM: sunxi-mmc: Add mmc support for sun6i / A31
The mmc hardware on sun6i has an extra reset control that needs to
be de-asserted prior to usage. Also the FIFO address is different.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: use setbits_le32 for reset control, drop obsolete changes,
		rewrite different FIFO address handling, add commit message]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:37 +02:00
Chen-Yu Tsai
14177e47e8 ARM: sun6i: Add clock support
This patch adds the basic clocks support for the Allwinner A31 (sun6i)
processor. This code will not been compiled until the build is hooked
up in a later patch. It has been split out to keep the patches manageable.

This includes changes from the following commits from u-boot-sunxi:

a92051b ARM: sunxi: Add sun6i clock controller structure
1f72c6f ARM: sun6i: Setup the UART0 clocks
5f2e712 ARM: sunxi: Enable pll6 by default on all models
2be2f2a ARM: sunxi-mmc: Add mmc support for sun6i / A31
12e1633 ARM: sun6i: Add initial clock setup for SPL
1a9c9c6 ARM: sunxi: Split clock code into common, sun4i and sun6i code
0b194ee ARM: sun6i: Properly setup the PLL LDO in clock_init_safe
b54c626 sunxi: avoid sr32 for APB1 clock setup.
68fe29c sunxi: remove magic numbers from clock_get_pll{5,6}
c89867d sunxi: clocks: clock_get_pll5 prototype and coding style
501ab1e ARM: sunxi: Fix sun6i PLL6 settings
37f669b ARM: sunxi: Fix macro names for mmc and uart reset offsets
61de1e6 ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: styling fixes reported by checkpatch.pl]
[wens@csie.org: drop unsupported SPL code block and unused gpio.h header]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:37 +02:00
Oliver Schinagl
174deb768c ARM: sun6i: Add support for the power reset control module found on the A31
The A31 has a new module called PRCM, or Power, Reset Control Module.
This module controls clocks and resets for RTC block modules, and also
PLL biasing in the main clock module.

This patch adds the register definitions, and also enables the clocks
and resets for the RTC block PIO (pin controller) and P2WI (push-pull
2 wire interface) which is used to talk to the PMIC.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: spacing fixes reported by checkpatch.pl]
[wens@csie.org: Use setbits helper in PRCM init function]
[wens@csie.org: rephrase commit message to explain what the hardware
		supports and what we actually enable]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:37 +02:00
Oliver Schinagl
93ce1e9dad ARM: sun6i: Add base address for the new controllers in A31
A31 has several new and changed memory address. This patch adds them.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:37 +02:00
Masahiro Yamada
d064cbffff dm: serial: use Driver Model for UniPhier serial driver
This commit converts UniPhier on-chip serial driver to driver model.

Since UniPhier SoCs do not have Device Tree support, some board files
should be added under arch/arm/cpu/armv7/uniphier/ph1-*/ directories.
(Device Tree support for UniPhier platform is still under way.)

Now the base address and master clock frequency are passed from
platform data, so CONFIG_SYS_UNIPHIER_SERIAL_BASE* and
CONFIG_SYS_UNIPHIER_UART_CLK should be removed.

Tested on UniPhier PH1-LD4 ref board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-10-23 21:43:09 -06:00
Simon Glass
5915a2ad0d dm: omap: gpio: Support driver model
Add driver model support to this driver, while retaining support for the
legacy system. Driver model GPIO support is enabled with CONFIG_DM_GPIO
as usual.

Since gpio_is_valid() no longer exists, we can use the -EINVAL error
returned from gpio_request().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
2014-10-23 19:29:07 -06:00
Tom Rini
03a3536c7b Merge branch 'master' of git://git.denx.de/u-boot-tegra 2014-10-23 14:05:34 -04:00
Igor Grinberg
b5ff205cdb omap3/am33xx: mux: fix several checkpatch issues
Fix the following checkpatch issues:

CHECK: No space is necessary after a cast
\#39: FILE: arch/arm/include/asm/arch-am33xx/mux.h:39:
+#define PAD_CTRL_BASE  0x800
+#define OFFSET(x)      (unsigned int) (&((struct pad_signals *) \

CHECK: Avoid CamelCase: <CONTROL_PADCONF_JTAG_nTRST>
\#284: FILE: arch/arm/include/asm/arch-omap3/mux.h:284:
+#define CONTROL_PADCONF_JTAG_nTRST     0x0A1C

ERROR: space required after that ',' (ctx:VxV)
\#446: FILE: arch/arm/include/asm/arch-omap3/mux.h:446:
+#define MUX_VAL(OFFSET,VALUE)\
                       ^
Cc: Raphael Assenat <raph@8d.com>
Cc: Ilya Yanok <yanok@emcraft.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Peter Barada <peter.barada@logicpd.com>
Cc: Grazvydas Ignotas <notasas@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Stefan Roese <sr@denx.de>
2014-10-23 11:53:02 -04:00
Vitaly Andrianov
89f44bb0ce keystone2: ecc: add ddr3 error detection and correction support
This patch adds the DDR3 ECC support to enable ECC in the DDR3
EMIF controller for Keystone II devices.

By default, ECC will only be enabled if RMW is supported in the
DDR EMIF controller. The entire DDR memory will be scrubbed to
zero using an EDMA channel after ECC is enabled and before
u-boot is re-located to DDR memory.

An ecc_test environment variable is added for ECC testing.
If ecc_test is set to 0, a detection of 2-bit error will reset
the device, if ecc_test is set to 1, 2-bit error detection
will not reset the device, user can still boot the kernel to
check the ECC error handling in kernel.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:29 -04:00
Vitaly Andrianov
079da2d514 ARM: keystone: msmc: extend functionality of SES
Add functions to set/get SES PMAX values of Pivilege ID pair.
Also add msmc module definitions.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:29 -04:00
Khoronzhuk, Ivan
e165b1d34c dma: ti-edma3: introduce edma3 driver
The EDMA3 controller’s primary purpose is to service data transfers
that you program between two memory-mapped slave endpoints on the device.

Typical usage includes, but is not limited to the following:
- Servicing software-driven paging transfers (e.g., transfers from external
  memory, such as SDRAM to internal device memory, such as DSP L2 SRAM)
- Servicing event-driven peripherals, such as a serial port
- Performing sorting or sub-frame extraction of various data structures
- Offloading data transfers from the main device DSP(s)
- See the device-specific data manual for specific peripherals that are
  accessible via the EDMA3 controller

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:29 -04:00
Khoronzhuk, Ivan
69a3b81141 ARM: keystone: clock: add support for K2E SoCs
For K2E and K2L SoCs clock output from PASS PLL has to be enabled
after NETCP domain and PA module are enabled. So create new function
for that and call it after PA module is enabled.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:29 -04:00
Khoronzhuk, Ivan
ff11c7697c net: keystone_net: add Keystone2 K2E SoC support
The Keystone2 Edison SoC uses the same keystone net driver.
This patch adds opportunity to use it by K2E SoCs.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:29 -04:00
Khoronzhuk, Ivan
3c61502aad net: keystone_serdes: add keystone K2E SoC support
Keystone2 Edison SoC uses the same keystone SerDes driver.
This patch adds support for K2E SoCs.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:29 -04:00
Khoronzhuk, Ivan
2162faaf58 ARM: keystone2: keysonte_nav: add support for K2E SoC
Keystone2 Edison SoC uses the same keystone navigator, but
uses different NETCP PktDMA definitions. This patch adds
required definitions.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:29 -04:00
Khoronzhuk, Ivan
3fe93623cc net: keystone_net: register eth PHYs on MDIO bus
As MDIO bus has been added we can register PHYs with it.
After registration, the PHY driver will be probed according to the
hardware on board.

Startup PHY at the ethernet open.

Use phy_startup() instead of keystone_get_link_status() when eth open,
as it verifies PHY link inside and SGMII link is checked before.

For K2HK evm PHY configuration at init was absent, so don't enable
phy config at init for k2hk evm.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:28 -04:00
Hao Zhang
92a16c81f5 soc: keystone_serdes: generalize to be used by other sub systems
SerDes driver is used by other sub systems like PCI, sRIO etc.
So modify it to be more general. The SerDes driver provides common
API's that can also be extended for other peripherals SerDes
configurations.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:28 -04:00
Hao Zhang
95f74dad91 soc: keystone_serdes: enhance to use cmu/comlane/lane specific configurations
Enhance the driver to use cmu/comlane/lane specific configurations
instead of 1 big array of configuration.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:28 -04:00
Khoronzhuk, Ivan
a43febde44 soc: keystone_serdes: create a separate SGMII SerDes driver
This patch split the Keystone II SGMII SerDes related code from
Ethernet driver and create a separate SGMII SerDes driver.
The SerDes driver can be used by others keystone subsystems
like PCI, sRIO, so move it to driver/soc/keystone directory.

Add soc specific drivers directory like in the Linux kernel.
It is going to be used by keysotone soc specific drivers.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:28 -04:00
Vitaly Andrianov
f077226610 net: keystone_net: increase MDIO clock frequency
With MAC_PHY sgmii configuration, u-boot checks PHY link status before
sending each packet. Increasing MDIO frequency increases overall tftp
speed. We set it to maximum 2.5MHz.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:05 -04:00
Khoronzhuk, Ivan
0935cac685 net: keystone_net: move header file from arch to ti-common
The header file for the driver should be in correct place.
So move it to "arch/arm/include/asm/ti-common/keystone_net.h"
and correct driver's external dependencies. At the same time
align and correct some definitions.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:05 -04:00
Khoronzhuk, Ivan
e3114c9a06 net: keystone_net: add support for NETCP v1.5
Currently the network driver is used only by k2hk evm board.
The k2hk SoC contains NETCP v1.0, but Keystone2 SoCs, like k2e
contain NETCP v1.5. So driver should be able to work with such kind
of NETCP. This commit adds this opportunity. The main difference in
masks and some registers, the logic is the same, so only definitions
should be changed. To differentiate between versions add KS2_NETCP_V1_0
and KS2_NETCP_V1_5. Also remove unused and no more needed defines.

The port number is specific for each board so move this parameter to
configuration.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:05 -04:00
Hao Zhang
b2cfe32278 net: keystone_net: remove SoC specific emac_regs structure
This patch removes K2HK SOC specifc emac_regs structure, it uses
soc specific register offset to keep the network driver common across
all the Keystone II EVMs.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:05 -04:00
Hao Zhang
345af53456 keystone2: k2l-evm: add board support
This patch adds Keystone II Lammar (K2L) EVM board support.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:05 -04:00
Hao Zhang
b66604fb66 keystone2: enable OSR clock domain for K2L SoC
This patches enables the On-chip Shared Ram clock domain for K2L SoC.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:05 -04:00
Hao Zhang
5ec66b140a ARM: keystone2: spl: move board specific code
The initialization of PLLs is a part of board specific code, so
move it appropriate places.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:05 -04:00