Commit graph

31717 commits

Author SHA1 Message Date
Thierry Reding
6527268d6e ARM: tegra: Disable SPL and non-cached memory on 64-bit
For 64-bit ARM SoCs we rely on non-U-Boot code to bring up the CPU in
AArch64 mode so that we don't need the SPL. Non-cached memory is not
implemented (yet) for 64-bit ARM.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-07-28 10:30:18 -07:00
Thierry Reding
32b3234f09 ARM: tegra: Use standard cache enable for 64-bit
On 64-bit SoCs the I-cache isn't enabled in early code, so the default
cache enable functions for 64-bit ARM can be used.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-07-28 10:30:18 -07:00
Thierry Reding
00f782a9f8 ARM: tegra: Restrict usable RAM to 32-bit on 64-bit SoCs
Most peripherals on Tegra can do DMA only to the lower 32-bit
address space, even on 64-bit SoCs. This limitation is
typically overcome by the use of an IOMMU. Since the IOMMU is
not entirely trivial to set up and serves no other purpose
(I/O protection, ...) in U-Boot, restrict 64-bit Tegra SoCs to
the lower 32-bit address space for RAM. This ensures that the
physical addresses of buffers that are programmed into the
various DMA engines are valid and don't alias to lower addresses.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-07-28 10:30:17 -07:00
Thierry Reding
5b34436035 fdt: Fix fdtdec_get_addr_size() for 64-bit
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-07-28 10:30:17 -07:00
Thierry Reding
8b19dff579 armv8/cache: Fix page table creation
While generating the page tables, a running integer index is shifted by
SECTION_SHIFT (29) and causes overflow for any integer bigger than 7.
The page tables therefore alias to the same 8 sections and cause U-Boot
to hang once the MMU is enabled.

Fix this by making the index a 64-bit unsigned integer and so avoid the
overflow.

swarren notes: currently "i" ranges from 0..8191 on all ARM64 boards, and
"j" varies depending on RAM size; from 4 to 11 for a board with 4GB at
physical address 2GB, as some Tegra boards have.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:30:17 -07:00
Chris Packham
488d19cbca patman: add distutils based installer
To make it easier to use patman on other projects add a distutils style
installer. Now patman can be installed with

  cd u-boot/tools/patman && python setup.py install

There are also the usual distutils options for creating source/binary
distributions of patman.

Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:25 -06:00
Bin Meng
1ed6648be0 x86: Reserve PCIe ECAM address range in the E820 table
We should mark PCIe ECAM address range in the E820 table as reserved
otherwise kernel will not attempt to use ECAM.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:25 -06:00
Bin Meng
9830d2ebb4 x86: qemu: Turn on PCIe ECAM address range decoding on Q35
Turn on PCIe ECAM address range decoding on Q35.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:25 -06:00
Bin Meng
a8ebf283e9 x86: qemu: Enable writing MP table
Enable writing MP table for QEMU boads (i440fx and q35).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:25 -06:00
Bin Meng
c77b8912d8 x86: Allow cpu-x86 driver to be probed for UP
Currently cpu-x86 driver is probed only for SMP. We add the same
support for UP when there is only one cpu node in the deive tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:25 -06:00
Bin Meng
e7cd070da6 x86: qemu: Enable I/O APIC chip select on PIIX3
The PIIX3 chipset does not integrate an I/O APIC, instead it supports
connecting to an external I/O APIC which needs to be enabled manually.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:24 -06:00
Bin Meng
53832bb8d6 x86: mpspec: Move writing ISA interrupt entry after PCI
On some platforms the I/O APIC interrupt pin#0-15 may be connected
to platform pci devices' interrupt pin. In such cases the legacy ISA
IRQ is not available so we should not write ISA interrupt entry if
it is already occupied.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:24 -06:00
Bin Meng
abab912813 x86: mpspec: Allow platform to determine how PIRQ is connected to I/O APIC
Currently during writing MP table I/O interrupt assignment entry, we
assume the PIRQ is directly mapped to I/O APIC INTPIN#16-23, which
however is not always the case on some platforms.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:24 -06:00
Bin Meng
a277194341 x86: Convert to use driver model pci on queensbay/crownbay
Move to driver model pci for Intel queensbay/crownbay.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-28 10:36:24 -06:00
Bin Meng
d11d9ef157 dm: pci: Support bridge device configuration correctly
Commit aec241d "dm: pci: Use the correct hose when configuring devices"
was an attempt to fix pci bridge device configuration, but unfortunately
that does not work 100%. In pciauto_config_devices(), the fix tried to
call pciauto_config_device() with a ctlr_hose which is supposed to be
the root controller hose, however when walking through a pci topology
with 2 or more pci bridges this logic simply fails.

The call chain is: pciauto_config_devices()->pciauto_config_device()
->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus()
does not make any sense as the given hose is not the bridge device's
hose, instead it is either the root controller's hose (case#1: if it
is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2:
if it is the 3rd pci bridge). In both cases the logic is wrong.

For example, for failing case#1 if the bridge device to config has the
same devfn as one of the devices under the root controller, the call
to pci_bus_find_devfn() will return the udevice of that pci device
under the root controller as the bus, but this is wrong as the udevice
is not a bus which does not contain all the necessary bits associated
with the udevice which causes further failures.

To correctly support pci bridge device configuration, we should still
call pciauto_config_device() with the pci bridge's hose directly.
In order to access valid pci region information, we need to refer to
the root controller simply by a call to pci_bus_to_hose(0) and get the
region information there in the pciauto_prescan_setup_bridge(),
pciauto_postscan_setup_bridge() and pciauto_config_device().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-28 10:36:24 -06:00
Bin Meng
8326f136da dm: pci: Pass only device/function to pci_bus_find_devfn()
In dm_pci_hose_probe_bus(), pci_bus_find_devfn() is called with a bdf
which includes a bus number, but it really should not as this routine
only expects a device/function encoding.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-28 10:36:23 -06:00
Bin Meng
4d8615cbf5 dm: pci: Use complete bdf in all pci config read/write routines
Currently pci_bus_read_config() and pci_bus_write_config() are
called with bus number masked off in the parameter bdf, and bus
number is supposed to be added back in the bridge driver's pci
config read/write ops if the device is behind a pci bridge.
However this logic only works for a pci topology where there is
only one bridge off the root controller. If there is addtional
bridge in the system, the logic will create a non-existent bdf
where its bus number gets accumulated across bridges.

To correct this, we change all pci config read/write routines
to use complete bdf all the way up to the root controller.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-28 10:36:23 -06:00
Bin Meng
95f3aa209a dm: pci: Correct primary/secondary/subordinate bus number assignment
In driver model, each pci bridge device has its own hose structure.
hose->first_busno points to the bridge device's device number, so
we should not substract hose->first_busno before programming the
bridge device's primary/secondary/subordinate bus number registers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-28 10:36:23 -06:00
Bin Meng
7e378b8bfc Fix incorrect comments in linker_lists.h
This corrects several typos in the comment block as well as some
indentions and nits in the linker_lists.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-28 10:36:23 -06:00
Bin Meng
9f244b27cf buildman: Correct '--fetch-arch' command documentation
The doc wrongly put sandbox in the '--fetch-arch' command. Remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:22 -06:00
Bin Meng
6fc0e8a1fa x86: pci: Do not assign irq 0 to pci device
IRQ 0 is reserved and should not be assigned to pci device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:22 -06:00
Bin Meng
31a2dc6955 x86: pci: Assign pci irqs to all functions
We need walk through all functions within a PCI device and assign
their IRQs accordingly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:22 -06:00
Bin Meng
93f8a31186 x86: Enable DM RTC support for all x86 boards
Add a RTC node in the device tree to enable DM RTC support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
(Squashed in 'x86: Fix RTC build error on ivybridge')
2015-07-28 10:36:22 -06:00
Bin Meng
8ba25eec86 x86: Change pci option rom area MTRR setting to cacheable
Turn on cache on the pci option rom area to improve the performance.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:22 -06:00
Bin Meng
3ccd49cab4 x86: Simplify architecture defined exception handling in irq_llsr()
Instead of using switch..case for architecture defined exceptions,
simply unify the handling by printing a message of exception name,
followed by registers dump then halt the CPU.

With this unification, it also fixes the wrong exception numbers
for #MF/#AC/#MC/#XM which should be 16/17/18/19 not 15/16/17/18.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:21 -06:00
Bin Meng
013cf483c9 x86: Display correct CS/EIP/EFLAGS when there is an error code
Some exceptions cause an error code to be saved on the current stack
after the EIP value. We should extract CS/EIP/EFLAGS from different
position on the stack based on the exception number.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-28 10:36:21 -06:00
Tom Rini
66d10c18bf Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze 2015-07-28 11:31:21 -04:00
Michal Simek
711e5e26b4 cmd_mp: Add support for showing all CPU status by one command
Use one command for showing overall CPU status than several without
knowing how many cpus is available in the system.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-07-28 11:56:29 +02:00
Michal Simek
80fd9792f5 spi: zynq_spi: Simplify debug macro
Trivial fix.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:28 +02:00
Michal Simek
260bdf07a3 zynq: Fix typo in Makefile about custom ps7_init file
Trivial fix.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:28 +02:00
Michal Simek
4c8b7bf49f net: gem: Extend timeout value
Extend time for MDIO. (Because of zed board)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:28 +02:00
Michal Simek
a0736efbe2 zynqmp: Show EL level where U-Boot runs
Add one more print to make clear which EL level U-Boot runs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:27 +02:00
Michal Simek
6fe6f13509 ARM: zynqmp: Wire up SATA for the board
Enable SATA for the ZynqMP targets.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:27 +02:00
Michal Simek
cb7ea82059 ARM: zynqmp: Wire up ethernet controllers
Wire up ethernet controllers and enable MII and BOOTP options.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:27 +02:00
Michal Simek
6d6e3dbefe ARM: zynq: Add support for zc770-xm011
Add xm011 DTS file and related configs and configurations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:26 +02:00
Michal Simek
5c45b16678 ARM: zynq: DT: Update zc770 dtses
Platform DTSes are missing content needed for platform to be able to use
OF binding and DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:26 +02:00
Michal Simek
91f9f17262 ARM: zynq: DT: Add zc702 pushbuttons to DT as gpio-keys
Adds the two MIO connected pushbuttons on the zc702 board to the
devicetree as a single multi-key device for us with the gpio-keys driver.

Signed-off-by: Ezra Savard <ezra.savard@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:26 +02:00
Michal Simek
d50cb3d64b ARM: zynq: DT: Add missing interrupt for L2 pl310
Add pl310 interrupt to the Zynq devicetree.

Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:26 +02:00
Michal Simek
b4e9eaf71f ARM: zynq: DT: Get rid of ps-clk-frequency
ps-clk-frequency is platform specific setting and shouldn't be the part
of DTSI.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:25 +02:00
Michal Simek
05e7ca63b7 ARM: zynq: DT: Update years in copyright
Trivial.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:25 +02:00
Michal Simek
999667ca9c ARM: zynq: DT: Sync zc702/zc706/zed/zybo DT with kernel
Syncup with the latest DT from the Linux kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:25 +02:00
Michal Simek
461c388806 ARM: zynq: DT: Add reference to bus node
For adding OCM memory in platform DTS is necessary to have reference to
amba bus.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:24 +02:00
Michal Simek
e913ce2ad5 ARM: zynq: DT: Add pinctrl node
Add pinctrl node to DTSI.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:24 +02:00
Michal Simek
5ee236a3ea ARM: zynq: DT: Cleanup address-cells and size-cells
Remove unneeded address-cells form intc node because it is already setup
in parent node.
Add missing address-cells and size-cells to eth node to be shared for
every platform DTSes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:24 +02:00
Michal Simek
b346bd1d2d ARM: zynq: DT: Clean up timer device tree nodes
Separate IRQ cells from each other for easier reading.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:23 +02:00
Michal Simek
7e163363fb ARM: zynq: DT: Use the zynq binding with macb
Use the new zynq binding for macb ethernet, since it will disable half
duplex gigabit like the Zynq TRM says to do. Also allow the compatible
cadence gem binding that won't disable half duplex but works otherwise.

Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:23 +02:00
Michal Simek
08305feb8e ARM: zynq: DT: Fix GEM register area size
The size of the GEM's register area is only 0x1000 bytes.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:22 +02:00
Michal Simek
40b383fa84 spi: Fix zynq SPI binding
Zynq is using Cadence IP where binding is documented in the Linux kernel
and there is no reason to use different binding.
Synchronize it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:22 +02:00
Michal Simek
3ffcdc7aaf ARM: zynq: DT: Remove 222 MHz OPP
Due to dependencies between timer and CPU frequency, only changes by
powers of two are allowed. The clocksource driver prevents other
changes, but with cpufreq and its governors it can result in being
spammed with error messages constantly. Hence, remove the 222 MHz OPP.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:22 +02:00
Michal Simek
8a8c46a65d ARM: zynq: DT: Migrate UART to Cadence binding
The Zynq UART is Cadence IP and the driver has been renamed accordingly.
Migrate the DT to use the new binding for the UART driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Michal Simek <michal.simek@xilinx.com>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:22 +02:00