Commit graph

72564 commits

Author SHA1 Message Date
Aaron Williams
1c0bf7905c mips: octeon: Add cvmx-pko-defs.h header file
Import cvmx-pko-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
aee94afd66 mips: octeon: Add cvmx-pki-defs.h header file
Import cvmx-pki-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
711cc5388b mips: octeon: Add cvmx-pip-defs.h header file
Import cvmx-pip-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
49a8669d59 mips: octeon: Add cvmx-pepx-defs.h header file
Import cvmx-pepx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
01dc174b6b mips: octeon: Add cvmx-pemx-defs.h header file
Import cvmx-pemx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
e613aca532 mips: octeon: Add cvmx-pcsx-defs.h header file
Import cvmx-pcsx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
b7e180a9f1 mips: octeon: Add cvmx-pciercx-defs.h header file
Import cvmx-pciercx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
11c2849f08 mips: octeon: Add cvmx-pcieepx-defs.h header file
Import cvmx-pcieepx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
1c5237729d mips: octeon: Add cvmx-npi-defs.h header file
Import cvmx-npi-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
a152234752 mips: octeon: Add cvmx-mio-defs.h header file
Import cvmx-mio-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
3359eabe03 mips: octeon: Add cvmx-l2c-defs.h header file
Import cvmx-l2c-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
622d5b9864 mips: octeon: Add cvmx-ipd-defs.h header file
Import cvmx-ipd-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
57d89c957a mips: octeon: Add cvmx-gserx-defs.h header file
Import cvmx-gserx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
84afd35619 mips: octeon: Add cvmx-gmxx-defs.h header file
Import cvmx-gmxx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
c9f3e7e430 mips: octeon: Add cvmx-fpa-defs.h header file
Import cvmx-fpa-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
1e12976f5d mips: octeon: Add cvmx-dtx-defs.h header file
Import cvmx-dtx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
826d071c7c mips: octeon: Add cvmx-dpi-defs.h header file
Import cvmx-dpi-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
4f83af4855 mips: octeon: Add cvmx-dbg-defs.h header file
Import cvmx-dbg-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
321101e90c mips: octeon: Add cvmx-ciu-defs.h header file
Import cvmx-ciu-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
8a65676f37 mips: octeon: Add cvmx-bgxx-defs.h header file
Import cvmx-bgxx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
cb0d1cb172 mips: octeon: Add cvmx-asxx-defs.h header file
Import cvmx-asxx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
2bfbfc6f7a mips: octeon: Add cvmx-agl-defs.h header file
Import cvmx-agl-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Aaron Williams
e7bc6eabd1 mips: octeon: Add misc cvmx-helper header files
Import misc cvmx-helper header files from 2013 U-Boot. They will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Stefan Roese
2d80cbfb05 mips: global_data.h: Add Octeon specific data to arch_global_data struct
This will be used by the upcoming Serdes and driver code ported from
the original 2013 U-Boot code to mainline.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:02:12 +02:00
Stefan Roese
91ce06ad34 mips: octeon: octeon_ebb7304_defconfig: Enable USB storage support
This patch enables USB storage support with the necessary partition
support on the MIPS Octeon EBB7304.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
2021-04-22 03:02:37 +02:00
Stefan Roese
b9849fd543 mips: octeon: octeon_ebb7304_defconfig: Enable MMC support
Enable MMC support including the regulator support on Octeon EBB7304.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-22 02:47:57 +02:00
Stefan Roese
cfa39fe78b mips: octeon: mrvl,octeon_ebb7304.dts: Add MMC DT node
Add the MMC DT node to the Octeon EBB7304 DT file including the
regulator node for the MMC power supply.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-22 02:47:57 +02:00
Stefan Roese
25869707c1 mips: octeon: mrvl,cn73xx.dtsi: Add MMC DT node
Add the MMC DT node to the Octeon CN73xx dtsi file.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-22 02:47:57 +02:00
Stefan Roese
f9bb0baa75 mmc: octeontx_hsmmc: Add support for MIPS Octeon
Until now, the Octeontx MMC driver did only support the ARM Octeon
TX/Tx2 platforms. This patch adds support for the MIPS Octeon platform
to this driver. Here a short summary of the changes:

- Enable driver compilation for MIPS Octeon, including the MMC related
  header file
- Reorder header inclusion
- Switch to using the clk framework to get the input clock
- Remove some functions for MIPS Octeon, as some registers don't
  exist here

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-22 02:47:57 +02:00
Weijie Gao
ff6d1948dc mips: mt7628: fix the displayed DDR type of mt7628
The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR type
from bootstrap register must be ignored, and always be assumed as DDR1.

This patch fixes the displayed DDR type of mt7628.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-22 02:44:42 +02:00
Weijie Gao
a9961e5acd mips: mt7628: fix ddr_type for MT7688KN
The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR type
from bootstrap register must be ignored, and always be assumed as DDR1.

This patch fixes an issue that mt7628_ddr_pad_ldo_config() may be passed
with a wrong ddr_type in MT7688KN.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-22 02:44:20 +02:00
Horatiu Vultur
42b5143210 net: jr2: Fix Serdes6G configuration
Sometimes no traffic was getting out on the ports, the root cause was
a wrong configuration of the Serdes6G, which is used on jr2 pcb111.
This patch fixes this issue by applying the correct configuration.

Fixes: 5e1d417bec ("net: Add MSCC Jaguar2 network driver.")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-04-22 02:34:45 +02:00
Horatiu Vultur
6b59304602 net: jr2: Reset switch
Make sure to reset the switch core at probe time.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-04-22 02:34:45 +02:00
Tom Rini
842d049be2 Merge branch '2021-04-20-assorted-improvements'
- ARM64 GIC fix, CONFIG_IRQ now moved to Kconfig
- IDE, lz4 fixes
- octeontx cleanups / enhancements
- highbank DM migration
- psci updates
- Enable use of -fstack-protector
2021-04-20 07:32:04 -04:00
Joel Peshkin
4e9bce1243 Add support for stack-protector
Add support for stack protector for UBOOT, SPL, and TPL
as well as new pytest for stackprotector

Signed-off-by: Joel Peshkin <joel.peshkin@broadcom.com>

Adjust UEFI build flags.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-04-20 07:31:12 -04:00
Heinrich Schuchardt
1598c83ece x86: correct usage of CFLAGS_NON_EFI
The current usage of the variable CFLAGS_NON_EFI on the x86 architecture
deviates from other architectures.

Variable CFLAGS_NON_EFI is the list of compiler flags to be removed when
building UEFI applications. It is not a list of flags to be added anywhere.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-04-20 07:31:12 -04:00
Heinrich Schuchardt
1b8897c63e test: fix test/dm/regmap.c
regmap_read() only fills the first two bytes of val. The last two bytes are
random data from the stack. This means the test will fail randomly.

For low endian systems we could simply initialize val to 0 and get correct
results. But tests should not depend on endianness. So let's use a pointer
conversion instead.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-20 07:31:12 -04:00
Denys Drozdov
fd90aca329 toradex: configblock: fix module revision in config block
U-boot might display wrong module revision information
for modules with an assembly version 'K'. "cfgblock create"
does not takes into account all revision digits from PID8.

This fix takes into account all digits of PID8
to store module revision.

Signed-off-by: Denys Drozdov <denys.drozdov@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-04-20 07:31:12 -04:00
Igor Opaniuk
1aa2a745c5 doc: usage: add usage details for reset cmd
Add usage details for reset command.

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2021-04-20 07:31:12 -04:00
Igor Opaniuk
a6713b3a3c sysreset: provide type of reset in do_reset cmd
Add additional param for reset cmd, which provides type of reset.

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2021-04-20 07:31:12 -04:00
Igor Opaniuk
91f00ba2c1 sysreset: psci: use psci driver exported functions
Use psci driver exported functions for reset/poweroff, instead of
invoking directly invoke_psci_fn.

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2021-04-20 07:31:12 -04:00
Igor Opaniuk
b7135b034f psci: add features/reset2 support
Adds support for:
* PSCI_FEATURES, which was introduced in PSCI 1.0. This provides API
that allows discovering whether a specific PSCI function is implemented
and its features.
* SYSTEM_RESET2, which was introduced in PSCI 1.1, which extends existing
SYSTEM_RESET. It provides support for vendor-specific resets, providing
reset_type as an additional param.

For additional details visit [1].

Implementations of some functions were borrowed from Linux PSCI driver
code [2].

[1] https://developer.arm.com/documentation/den0022/latest/
[2] drivers/firmware/psci/psci.c

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2021-04-20 07:31:12 -04:00
Igor Opaniuk
2963d606bc psci: add v1.0/v1.1 definitions from Linux
Sync and add PSCI API versions 1.0/1.1 definitions from Linux.

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2021-04-20 07:31:12 -04:00
Tom Rini
56a3433ef5 sysinfo.h: Add re-inclusion guard
Add #ifndef __SYSINFO_H__ ... #endif to prevent re-inclusion of this
file.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-04-20 07:31:12 -04:00
Andre Przywara
9f4b53436c arm: highbank: Update maintainership
Rob does not have access to any Calxeda systems anymore, also has
expressed a lack of interest in those systems in the past.

I have multiple working Midway nodes under my desk in the office, so
am happy to take over maintainership.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-04-20 07:31:12 -04:00
Andre Przywara
1238d0143a arm: highbank: Do DRAM init from DT
So far U-Boot was hard coding a (surely sufficient) memory size of 512
MB, even though all machines out there have at least 4GB of DRAM.
Since U-Boot uses its memory knowledge to populate the EFI memory map,
we are missing out here, at best losing everything beyond 4GB on Midway
boxes (which typically come with 8GB of DRAM).

Since the management processor populated the DT memory node already with
the detected DRAM size and configuration, we use that to populate
U-Boot's memory bank information, which is the base for the UEFI memory
map.
This finally allows us to get rid of the NR_DRAM_BANKS=0 hack, that we
had in place to avoid U-Boot messing up the DT memory node before
loading the kernel.

Also, to cover the whole of memory, we need to enable PHYS_64BIT.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-04-20 07:31:12 -04:00
Andre Przywara
ff47d539f2 arm: highbank: Remove artificial SDRAM size
So far we were defining a somewhat confusing PHYS_SDRAM_1_SIZE variable,
which originally was only used for setting the memtest boundaries. This
definition in highbank.h has been removed about a year ago (moved to
Kconfig), so we also don't need the hard-coded size definition any longer.

Get rid of the misleading memory size definition, which was actually wrong
anyway (it's 4088 MB for those machines with just 4GB of DRAM).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-04-20 07:31:12 -04:00
Andre Przywara
debb07bf10 net: calxedagmac: Convert to DM_ETH
To squash that nasty warning message and make better use of the newly
gained OF_CONTROL feature, let's convert the calxedagmac driver to the
"new" driver model.
The conversion is pretty straight forward, mostly just adjusting the
use of the involved data structures.
The only actual change is the required split of the receive routine into
a receive and free_pkt part.
Also this allows us to get rid of the hardcoded platform information and
explicit init calls.

This also uses the opportunity to wrap the code decoding the MMIO
register base address, to make it safe for using PHYS_64BIT later.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-04-20 07:31:12 -04:00
Andre Przywara
109552d773 arm: highbank: Enable OF_CONTROL
All Calxeda machines are actually a poster book example of device tree
usage: the DT is loaded from flash by the management processor into
DRAM, the memory node is populated with the detected DRAM size and this
DT is then handed over to the kernel.
So it's a shame that U-Boot didn't participate in this chain, but
fortunately this is easy to fix:

Define CONFIG_OF_CONTROL and CONFIG_OF_BOARD, and provide a trivial
function to tell U-Boot about the (fixed) location of the DTB in DRAM.
Then enable DM_SERIAL, to let the PL011 driver pick up the UART platform
data from the DT. Also define AHCI, to bring this driver into the driver
model world as well.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-04-20 07:31:12 -04:00
Andre Przywara
84b2cd74f3 arm: highbank: Limit FDT and initrd load addresses
So far on Highbank/Midway machines U-Boot only ever uses 512MB of DRAM,
even though the machines have typically 4GB and 8GB, respectively.
That means that so far we didn't need an extra limit for placing the DTB
and initrd, as the 512MB are lower than the kernel's limit ("lowmem",
typically 768MB).

With U-Boot now needing to learn about the actual memory size (to
correctly populate the EFI memory map), it might relocate fdt and initrd
to the end of DRAM, which is out of reach of the kernel.

So add limiting values to the fdt_high and initrd_high environment
variables, to prevent U-Boot from using too high addresses.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-04-20 07:31:12 -04:00