Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to
perform resets and thus depends on it. The actual Watchdog device used
needs to be configured in Device Tree using "aspeed,wdt" property, which
must be WDT phandle, for example:
rst: reset-controller {
compatible = "aspeed,ast2500-reset";
aspeed,wdt = <&wdt1>;
}
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds a reset controller implementation for STMicroelectronics
STi family SoCs; it allows a group of related reset like controls found
in multiple system configuration registers to be represented by a single
controller device.
Driver code has been mainly extracted from kernel
drivers/reset/sti/reset-stih407.c
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.
Signed-off-by: Simon Glass <sjg@chromium.org>
These have now landed upstream. The naming is different and in one case the
function signature has changed. Update the code to match.
This applies the following upstream commits by
Thierry Reding <treding@nvidia.com> :
604e61e fdt: Add functions to retrieve strings
8702bd1 fdt: Add a function to get the index of a string
2218387 fdt: Add a function to count strings
Signed-off-by: Simon Glass <sjg@chromium.org>
This is the initial commit for UniPhier reset controller driver.
Most code was ported from Linux.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Implement a reset uclass driver for the Tegra CAR. This allows clients to
use standard reset APIs on Tegra. This device is intended to be
instantiated by the core Tegra CAR driver, rather than being instantiated
directly from DT. The implementation uses the existing custom Tegra-
specific reset APIs to avoid coupling the series with significant
refactoring of the existing Tegra clock/reset code.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
In Tegra186, on-SoC reset signals are manipulated using IPC requests to
the BPMP (Boot and Power Management Processor). This change implements a
driver that does that. It is unconditionally selected by CONFIG_TEGRA186
since virtually any Tegra186 build of U-Boot will need the feature.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This adds a sandbox reset implementation (provider), a test client
device, instantiates them both from Sandbox's DT, and adds a DM test
that excercises everything.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
A reset controller is a hardware module that controls reset signals that
affect other hardware modules or chips.
This patch defines a standard API that connects reset clients (i.e. the
drivers for devices affected by reset signals) to drivers for reset
controllers/providers. Initially, DT is the only supported method for
connecting the two.
The DT binding specification (reset.txt) was taken from Linux kernel
v4.5's Documentation/devicetree/bindings/reset/reset.txt.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
