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18387 commits

Author SHA1 Message Date
Stefan Agner
71fd11b901 nvme: Use only 32-bit accesses in nvme_writeq/nvme_readq
There might be hardware configurations where 64-bit data accesses
to NVMe registers are not supported properly.  This patch removes
the readq/writeq so always two 32-bit accesses are used to read/write
64-bit NVMe registers, similarly as it is done in Linux kernel.

This patch fixes operation of NVMe devices on RPi4 Broadcom BCM2711 SoC
based board, where the PCIe Root Complex, which is attached to the
system through the SCB bridge.

Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
the 64-bit wide register accesses initiated by the CPU are not properly
translated to a sequence of 32-bit PCIe accesses.
nvme_readq(), for example, always returns same value in upper and lower
32-bits, e.g. 0x3c033fff3c033fff which lead to NVMe devices to fail
probing.

This fix is analogous to commit 8e2ab05000 ("usb: xhci: Use only
32-bit accesses in xhci_writeq/xhci_readq").

Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Cc: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
2021-01-04 09:10:16 -05:00
Tom Rini
ab865a8ee5 Fixes for 2021.1
----------------
 
 CI: https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/5680
 
 - fixes for Variscite dart6ul
 - imx8mp : increase malloc area
 - fixes for bx50v3
 - imx8m: HS400ES and UHS for EVK
 - imx8qm-rom7720: fix phy bind
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Merge tag 'u-boot-imx-20201227' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Fixes for 2021.1
----------------

CI: https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/5680

- fixes for Variscite dart6ul
- imx8mp : increase malloc area
- fixes for bx50v3
- imx8m: HS400ES and UHS for EVK
- imx8qm-rom7720: fix phy bind
2020-12-28 07:44:03 -05:00
Pali Rohár
0eb0eb4ab2 Revert "arm64: a37xx: pci: Assert PERST# signal when unloading driver"
This reverts commit 828d326216.

This change revers code which asserting PERST# signal when unloading
driver. Driver's remove callback is still there as it is used for other
functionality.

Asserting PERST# signal prior booting kernel is causing that A3720 boards
(Turris MOX and Espressobin) with stable Linux kernel versions 4.14 and
4.19 are not able to detect some PCIe cards (e.g. Compex WLE200 and WLE900)
and anymore. When PERST# signal is not asserted these cards are detected
correctly. As this is regression for existing stable Linux kernel versions
revert this problematic change in U-Boot.

To make cards working with OpenWRT 4.14 kernel it is needed to disable link
training prior booting kernel, which is already done in driver's remove
callback.

Described issue is in Linux kernel pci aardvark driver which is (hopefully)
fixed in latest upstream versions. Latest upstream versions should be able
to initialize PCIe bus and detects cards independently of the link training
and PERST# signal state.

So with this change, U-Boot on A3720 boards should be able to boot OpenWRT
4.14 kernel, stable 4.14 and 4.19 kernels and also latest mainline kernels.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-12-28 09:42:06 +01:00
Marc Ferland
26c7048dd9 i2c: mxc_i2c: improve error message readability
Use 0x%2lx to print the i2c bus base address in hexadecimal format
instead of printing as an integer.

Signed-off-by: Marc Ferland <ferlandm@amotus.ca>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-12-26 14:56:09 +01:00
Tom Rini
549e7cb708 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi 2020-12-18 13:06:02 -05:00
Hongwei Zhang
936a645609 mtd: spi-nor-ids: add Micron MT25QL01G flash
Add Micron MT25QL01G flash, used on AST2600 board.

Signed-off-by: Hongwei Zhang <hongweiz@ami.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:19:33 +05:30
Pengpeng Chen
24f2794232 spi: ca_sflash: Add CAxxxx SPI Flash Controller
Add SPI Flash controller driver for Cortina Access
CAxxxx SoCs

Signed-off-by: Pengpeng Chen <pengpeng.chen@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Vignesh R <vigneshr@ti.com>
CC: Tom Rini <trini@konsulko.com>
[jagan: rebase on master]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:37 +05:30
Sean Anderson
fec7bf0460 spi: dw: Add mem_ops
The designware ssi device has "broken" chip select behaviour [1], and needs
specific manipulation to use the built-in chip select. The existing fix is
to use an external GPIO for chip select, but typically the K210 has SPI3
directly connected to a flash chip with dedicated pins. This makes it
impossible to use the spi_xfer function to use spi, since the CS is
de-asserted in between calls.  This patch adds an implementation of
exec_op, which gives correct behaviour when reading/writing spi flash.

This patch also rearranges the headers to conform to U-Boot style.

[1] https://lkml.org/lkml/2015/12/23/132

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:37 +05:30
Sean Anderson
58875790fd spi: dw: Add support for multiple CTRLR0 layouts
CTRLR0 can have several different layouts depending on the specific device
(dw-apb-ssi vs dwc-ssi), and specific parameters set during synthesis.
Update the driver to support three specific configurations: dw-apb-ssi with
SSI_MAX_XFER_SIZE=16, dw-apb-ssi with SSI_MAX_XFER_SIZE=32, and dwc-ssi.

dw-apb-ssi is the version of the device on Altera/Intel SoCFPGAs, MSCC
SoCs, and Canaan Kendryte K210 SoCs. This is the only version this driver
supported before this change. The register layout before version 3.23a is:

|   31 .. 16  |
| other stuff |

|   15 .. 10  | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 |
| other stuff |  TMOD  |  MODE  |  FRF   |  DFS   |

Note that DFS (Data Frame Size) is only 4 bits, limiting transfers to data
frames of 16 bits or less.

In version 3.23a, the SSI_MAX_XFER_SIZE parameter was introduced. This
parameter defaults to 16 (resulting in the same layout as prior versions),
but may also be set to 32. To allow setting longer data frame sizes, a new
DFS_32 register was introduced:

|   31 .. 21  | 20 .. 16 |
| other stuff |  DFS_32  |

|   15 .. 10  | 9 .. 8 | 7 .. 6 | 5 .. 4 |  3 .. 0   |
| other stuff |  TMOD  |  MODE  |  FRF   | all zeros |

The old DFS field no longer controls the data frame size. To detect this
layout, we try writing 0xF to DFS. If we read back 0x0, then this device
has SSI_MAX_XFER_SIZE=32.

dwc-ssi is the version of the device on Intel Keem Bay SoCs and Canaan
Kendryte K210 SoCs. The layout of ctrlr0 is:

|   31 .. 16  |
| other stuff |

|   15 .. 12  | 11 .. 10 | 9 .. 8 | 7 .. 6 | 4 .. 0 |
| other stuff |   TMOD   |  MODE  |  FRF   | DFS_32 |

The semantics of the fields have not changed since the previous version.
However, SSI_MAX_XFER_SIZE is effectively always 32.

To support these different layouts, we model our approach on the one
which the Linux kernel has taken. During probe, the driver calls an init
function stored in driver_data. This init function is responsible for
determining the layout of CTRLR0, and supplying the update_cr0 function.

The style of and information behind this commit is based on the Linux MMIO
driver for these devices. Specific reference was made to the series adding
support for Intel Keem Bay SoCs [1].

[1] https://lore.kernel.org/linux-spi/20200505130618.554-1-wan.ahmad.zainie.wan.mohamad@intel.com/

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:37 +05:30
Sean Anderson
ddd3450f39 spi: dw: Rearrange struct dw_spi_priv
This should reduce the size of the struct, and also groups more similar
fields together.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:37 +05:30
Sean Anderson
934beab882 spi: dw: Remove spi_enable_chip
This function does nothing but wrap dw_write.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:37 +05:30
Sean Anderson
3004034989 spi: dw: Rename registers to match datasheet
A few registers had slightly different names from what is in the datasheet.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:37 +05:30
Sean Anderson
c785f43ffd spi: dw: Use generic function to read reg address
Using an fdt-specific function causes problems when compiled with a live
tree.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:36 +05:30
Sean Anderson
13fc44e222 spi: dw: Rename "cs-gpio" to "cs-gpios"
This property is named differently than other SPI drivers with the same
property, as well as the property as used in Linux.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:36 +05:30
Sean Anderson
1b3dd491e6 spi: dw: Convert calls to debug to dev_*
This allows different log levels to be enabled or disabled depending on the
desired level of verbosity. In particular, it allows for general debug
information to be printed while excluding more verbose logging which may
interfere with timing.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:36 +05:30
Sean Anderson
caf110798c spi: dw: Fix driving MOSI low while recieving
The resting state of MOSI is high when nothing is driving it. If we drive
it low while recieving, it looks like we are transmitting 0x00 instead of
transmitting nothing. This can confuse slaves (like SD cards) which allow
new commands to be sent over MOSI while they are returning data over MISO.
The return of MOSI from 0 to 1 at the end of recieving a byte can look like
a start bit and a transmission bit to an SD card. This will cause the card
to become out-of-sync with the SPI device, as it thinks the device has
already started transmitting two bytes of a new command. The mmc-spi driver
will not detect the R1 response from the SD card, since it is sent too
early, and offset by two bits. This patch fixes transfer errors when using
SD cards with dw spi.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:36 +05:30
Mikhail Kshevetskiy
25f068aa3e mtd: spinand: enable erasing of bad mtd blocks
U-Boot is able to erase bad mtd blocks on raw nand devices, but this
is not true for spinand flashes. Lets enable this feature for spinand
flashes as well. This is extemelly useful for flash testing.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@oktetlabs.ru>
2020-12-18 16:16:36 +05:30
Frieder Schrempf
031b89e51b mtd: spinand: Do not erase the block before writing a bad block marker
Currently when marking a block, we use spinand_erase_op() to erase
the block before writing the marker to the OOB area. Doing so without
waiting for the operation to finish can lead to the marking failing
silently and no bad block marker being written to the flash.

In fact we don't need to do an erase at all before writing the BBM.
The ECC is disabled for raw accesses to the OOB data and we don't
need to work around any issues with chips reporting ECC errors as it
is known to be the case for raw NAND.

Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Cc: stable@vger.kernel.org
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-4-frieder.schrempf@kontron.de
2020-12-18 16:16:36 +05:30
Frieder Schrempf
e6108004e6 mtd: spinand: Explicitly use MTD_OPS_RAW to write the bad block marker to OOB
When writing the bad block marker to the OOB area the access mode
should be set to MTD_OPS_RAW as it is done for reading the marker.
Currently this only works because req.mode is initialized to
MTD_OPS_PLACE_OOB (0) and spinand_write_to_cache_op() checks for
req.mode != MTD_OPS_AUTO_OOB.

Fix this by explicitly setting req.mode to MTD_OPS_RAW.

Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-3-frieder.schrempf@kontron.de
2020-12-18 16:16:36 +05:30
Frieder Schrempf
987f1e56ed mtd: spinand: Stop using spinand->oobbuf for buffering bad block markers
For reading and writing the bad block markers, spinand->oobbuf is
currently used as a buffer for the marker bytes. During the
underlying read and write operations to actually get/set the content
of the OOB area, the content of spinand->oobbuf is reused and changed
by accessing it through spinand->oobbuf and/or spinand->databuf.

This is a flaw in the original design of the SPI NAND core and at the
latest from 13c15e07eedf ("mtd: spinand: Handle the case where
PROGRAM LOAD does not reset the cache") on, it results in not having
the bad block marker written at all, as the spinand->oobbuf is
cleared to 0xff after setting the marker bytes to zero.

To fix it, we now just store the two bytes for the marker on the
stack and let the read/write operations copy it from/to the page
buffer later.

Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Cc: stable@vger.kernel.org
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-2-frieder.schrempf@kontron.de
2020-12-18 16:16:36 +05:30
Robert Marko
d1b6b942f8 mtd: spi-nor-ids: Add SECT_4K to mx25l12805d
According to the mx25l12805d datasheet it supports using 4K or 64K sectors.
So lets add the SECT_4K to enable 4K sector usage.

Datasheet: https://www.mxic.com.tw/Lists/Datasheet/Attachments/7321/MX25L12805D,%203V,%20128Mb,%20v1.2.pdf

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:36 +05:30
Biju Das
9dddead735 mtd: spi-nor-ids: Add Winbond W25M512JW flash entry
Add Winbond W25M512JW flash device description.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:36 +05:30
Lad Prabhakar
1910aca0f1 mtd: spi-nor-ids: Add Winbond W25M512JV flash entry
Add Winbond W25M512JV flash device description.

Linux already has the flash entry present. A snippet below:
{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024...},

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:36 +05:30
Patrick Delaunay
46c5391b3d spi: migrate trace to dev and log macro in spi uclass
Define LOG_CATEGORY and change printf and pr_*
to dev_ (when dev is available) or log_ macro.

This patch adds the support of logging feature with log command
(filtering, display of device name in trace) and allows to
suppress traces via the syslog driver.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:36 +05:30
Tom Rini
51f65b506f Merge branch 'master' of git://git.denx.de/u-boot-usb
- r8152, xhci fixes
2020-12-16 17:43:33 -05:00
Hayes Wang
7229440772 eth/r8152: fix the aggregation issue
Remove the redundant setting for USB_RX_EARLY_SIZE. Besides, for
RTL8153B, it is necessary to notify the hardware of the changes
of the aggregation settings.

Signed-off-by: Hayes Wang <hayeswang@realtek.com>
2020-12-16 10:27:09 +01:00
Hayes Wang
17d5a461a0 eth/r8152: free previous memory if r8152_eth_probe fail
The r8152_eth_probe() may allocate a memory for ss->dev_priv.
It has to be freed if r8152_eth_probe() fails finally.

Signed-off-by: Hayes Wang <hayeswang@realtek.com>
2020-12-16 10:27:09 +01:00
Ran Wang
621ed49d3a usb: xhci: fix lack of short packet event trb handling
For bulk IN transfer, the codes will set ISP flag to request event TRB
being generated by xHC for the case of short packet. So when encountering
buffer-cross-64K-boundary (which we will divide payload and enqueuqe
more than 1 transfer TRB), and the first TRB ends up with a short packet
condition it will trigger an short packet code transfer event per that
flag and cause more than 1 event TRB generated for this transfer.

However, current codes will only handle the first transfer event TRB
then mark current transfer completed, causing next transfer
failure due to event TRB mis-match.

Such issue has been observed on some Layerscape platforms (LS1028A,
LS1088A, etc) with USB ethernet device.

This patch adds a loop to make sure the event TRB for last transfer TRB
has been handled in time.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-12-16 10:27:09 +01:00
Andy Shevchenko
23cdbba8b1 x86: edison: Use dwc3-generic driver for Intel Edison
Use generic Synopsys DesignWare 3 driver on Intel Edison.
For now it's just a stub which allows future refactoring.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-12-16 13:51:24 +08:00
Neil Armstrong
5ccd5d2cc9 pinctrl: meson: fix bit manipulation of pin bias configuration
This fixes the wrong usage of clrsetbits_le32(), badly setting the set argument.

Fixes: c4c726c26b ("pinctrl: meson: add pinconf support")
Reported-by: Anton Arapov <arapov@gmail.com>
Reported-by: Otto Meier <gf435@gmx.net>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-12-14 19:58:54 +01:00
Marek Szyprowski
5c88b6ad40 usb: dwc3-meson-g12a: always configure dr-mode
dwc3_meson_g12a_force_mode() sets the dr-mode of the USB PHY. However
it skips setting the mode if it matches the one done during driver probe
(stored in private structure). This fails if the mode has been changed
to other value and then back to initial one. Fix this by configuring the
dr-mode always, regadless of the one set at the driver probe).

This fixes operation of USB gadget based drivers when they are initialized
for the second time.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-12-14 19:58:54 +01:00
Tom Rini
5a1a8a63be Second set of u-boot-atmel fixes for 2021.01 cycle
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Merge tag 'u-boot-atmel-fixes-2021.01-b' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

Second set of u-boot-atmel fixes for 2021.01 cycle

This set includes very important fixes for: MMC booting on several
boards, drive strength on sam9x60ek mmc lines, compile issues for
timer.c old driver, removal of unwanted access to sam9x60 bit for
oscillator bypass mode, and eeproms read on sama5d2_icp.
2020-12-11 15:55:17 -05:00
Biwen Li
164941c2c4 net: pfe_eth: read PFE ESBC header flash with spi_flash_read API
Read PFE ESBC header flash with spi_flash_read API
- logs as follows,
  Net:   SF: Detected s25fs512s with page size 256 Bytes, erase size 256
  KiB, total 64 MiB
  "Synchronous Abort" handler, esr 0x96000210
  elr: 000000008206db44 lr : 0000000082004ea0 (reloc)
  elr: 00000000b7ba6b44 lr : 00000000b7b3dea0
  x0 : 00000000b79407e8 x1 : 0000000040640000
  x2 : 0000000000000050 x3 : 0000000000000000
  x4 : 000000000000000a x5 : 0000000000000050
  x6 : 0000000000000366 x7 : 00000000b7942308
  x8 : 00000000b76407c0 x9 : 0000000000000008
  x10: 0000000000000044 x11: 00000000b7634d1c
  x12: 000000000000004f x13: 0000000000000044
  x14: 00000000b7634d98 x15: 00000000b76407c0
  x16: 0000000000000000 x17: 0000000000000000
  x18: 00000000b7636dd8 x19: 0000000000000000
  x20: 00000000b79407d0 x21: 00000000b79407e8
  x22: 0000000040640000 x23: 00000000b7634e58
  x24: 0000000000000000 x25: 0000000003800000
  x26: 00000000b7bdd000 x27: 0000000000000000
  x28: 0000000000000000 x29: 00000000b7634d10

  Code: d2800003 eb03005f 54000101 d65f03c0 (f8636826)
  Resetting CPU ...

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
Hou Zhiqiang
ee7c1225e3 pci: layerscape: fix a dead loop issue
Fixes: commit 8ec619f8fd ("pci: layerscape: Fixup PCIe EP
	mode DT nodes for LX2160A rev2")

This added the PCIe EP nodes fixup of LX2160A, but it
didn't update the condition value when there isn't a
property 'apio-wins'.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Fixed checkpatch error]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
Meenakshi Aggarwal
3a187cff7a armv8: lx2162a: Add Soc changes to support LX2162A
LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.

LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module,
microSD card, eMMC support, serial console, qspi nor flash, qsgmii,
sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes
interface to support three PCIe gen3 interface.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
[Fixed whitespace errors]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
Meenakshi Aggarwal
2a29a9a1b4 drivers/net/phy: Add CORTINA_NO_FW_UPLOAD to Kconfig
Move CORTINA_NO_FW_UPLOAD to Kconfig file so that it can
be controlled via defconfig files.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
Wasim Khan
1255f8bc36 pci: ls_pcie_g4: Add size check for config resource
resource "config" is required to have minimum 4KB space
to access all config space of PCI Express EP.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
Wasim Khan
49df7c9086 pci: layerscape: Add size check for config resource
resource "config" is required to have minimum 8KB space
as per hardware documentation.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
Wasim Khan
eac364416c pci: ls_pcie_g4: Print pcie controller number starting from 1
Print pcie controller number starting from 1

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
2020-12-10 13:56:38 +05:30
Wasim Khan
b6c6a245bf pci: layerscape: Update print of pcie controller
Print pcie controller number starting from 1

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
[Trimmed subject]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:38 +05:30
Tom Rini
2a42de6df1 - Manage CONFIG_ENV_EXT4_DEVICE_AND_PART in stm32mp1 board
- Update ARM STI and ARM STM STM32MP Arch maintainers emails
 - Enable internal pull-ups for SDMMC1 on DHCOM SoM
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Merge tag 'u-boot-stm32-20201209' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Manage CONFIG_ENV_EXT4_DEVICE_AND_PART in stm32mp1 board
- Update ARM STI and ARM STM STM32MP Arch maintainers emails
- Enable internal pull-ups for SDMMC1 on DHCOM SoM
2020-12-09 11:36:41 -05:00
Patrice Chotard
0f8106f8e0 treewide: Update email address Patrick Delaunay and Patrice Chotard
Update Patrick and my email address with the one dedicated to
upstream activities.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-12-09 10:57:50 +01:00
Claudiu Beznea
8454cf0d23 clk: at91: sam9x60: remove the parsing of atmel, main-osc-bypass
Remove the parsing of atmel,main-osc-bypass DT property as the SAM9X60
have no support for crystal oscillator bypass. Setting this bit might
affect the device functionality.

Fixes: a64862284f ("clk: at91: sam9x60: add support compatible with CCF")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-12-07 09:36:45 +02:00
Igor Opaniuk
8f9abdf4d4 power: pmic: add SPL_DM_PMIC_PCA9450 symbol to Kconfig
Add SPL_DM_PMIC_PCA9450 symbol to Kconfig.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-12-06 15:31:37 +01:00
Max Krummenacher
5d89afe27f pca9450a: fix i2c address
The I2C address is 0x25, not 0x35. This according to the datasheet and
tests with a PCA9450A.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-12-06 15:31:37 +01:00
Haibo Chen
5d772196d9 mmc: fsl_esdhc_imx: optimize the timing setting
For imx usdhc/esdhc, once set the DDR_EN, enable the DDR mode, the
card clock will be divied by 2 automatically by the host. So need
to first config the DDR_EN correctly, then update the card clock.
This will make sure the actual card clock is as our expected.
IC also suggest config the DDR_EN firstly, then config the clock
divider.

For HS400/HS400ES mode, need to config the strobe dll, this need
to based on the correct target clock rate, so need to do this after
clock rate is update.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-12-06 15:31:37 +01:00
Haibo Chen
b5874b552f mmc: fsl_esdhc_imx: add wait_dat0() support
Add wait_dat0() support, upper layer will use this callback.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-12-06 15:31:36 +01:00
Oliver Graute
61eb1fe568 imx: clk: added IPG Clock for I2C on imx8qm
This patch fixes this clk issue on I2C on imx8qm

 => i2c bus
 Bus 3:  i2c@5a830000
 => i2c dev 3
 Setting bus to 3
 Failed to enable ipg clk
 Failure changing bus number (-524)

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-12-06 15:07:51 +01:00
Michael Walle
382985675c mtd: spi-nor-ids: add Winbond W25Q32JW-IM flash
The Kontron SMARC-sAL28 board uses that flash.

This is the same change as in the linux commit f3418718c0ec ("mtd:
spi-nor: Add support for w25q32jwm").

Signed-off-by: Michael Walle <michael@walle.cc>
Reported-by: Leo Krueger <leo.krueger@zal.aero>
2020-12-02 16:21:58 -05:00
Zhao Qiang
c2ba01c082 watchdog: sbsa: timeout should be in "millisecond"
timeout should be in "millisecond" instead of second,
so divided it by 1000 when calculate the load value.

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2020-12-02 16:21:58 -05:00