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56761 commits

Author SHA1 Message Date
Eugeniu Rosca
1cfe969475 disk: efi: Fix memory leak on 'gpt guid'
Below is what happens on R-Car H3ULCB-KF using clean U-Boot
v2019.04-00810-g6aebc0d11a10 and r8a7795_ulcb_defconfig:

 => ### interrupt autoboot
 => gpt guid mmc 1
 21200400-0804-0146-9dcc-a8c51255994f
 success!
 => ### keep calling 'gpt guid mmc 1'
 => ### on 59th call, we are out of memory:
 => gpt guid mmc 1
 alloc_read_gpt_entries: ERROR: Can't allocate 0X4000 bytes for GPT Entries
 GPT: Failed to allocate memory for PTE
 get_disk_guid: *** ERROR: Invalid GPT ***
 alloc_read_gpt_entries: ERROR: Can't allocate 0X4000 bytes for GPT Entries
 GPT: Failed to allocate memory for PTE
 get_disk_guid: *** ERROR: Invalid Backup GPT ***
 error!

After some inspection, it looks like get_disk_guid(), added via v2017.09
commit 73d6d18b71 ("GPT: add accessor function for disk GUID"),
unlike other callers of is_gpt_valid(), doesn't free the memory pointed
out by 'gpt_entry *gpt_pte'. The latter is allocated by is_gpt_valid()
via alloc_read_gpt_entries().

With the fix applied, the reproduction scenario has been run hundreds
of times ('while true; do gpt guid mmc 1; done') w/o running into OOM.

Fixes: 73d6d18b71 ("GPT: add accessor function for disk GUID")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-02 18:17:50 +02:00
Heinrich Schuchardt
e6023be41e efi_loader: description of efi_add_handle()
Correct the comments describing function efi_add_handle().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-02 18:17:50 +02:00
Heinrich Schuchardt
a9a25cc3e7 efi_selftest: test exit_data
Amend the unit test 'start image exit' to transfer a string as exit data.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-02 18:17:50 +02:00
Heinrich Schuchardt
556d8dc937 efi_loader: implement support of exit data
In case of a failure exit data may be passed to Exit() which in turn is
returned by StartImage().

Let the `bootefi` command print the exit data string in case of an error.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-02 18:17:50 +02:00
Heinrich Schuchardt
45203e0ccb efi_loader: memory leak in append value
When printing an UEFI variable an error may arise while converting an
illegal hexadecimal value. In this case a buffer is leaked.

Close the memory leak. Provide an error message.

Reported-by: Coverity (CID 185830)
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-02 18:17:50 +02:00
Heinrich Schuchardt
39a1ff8cea efi_loader: optional data in load options are binary
The field boot OptionalData in structure _EFI_LOAD_OPTIONS is for binary
data.

When we use `efidebug boot add` we should convert the 5th argument from
UTF-8 to UTF-16 before putting it into the BootXXXX variable.

When printing boot variables with `efidebug boot dump` we should support
the OptionalData being arbitrary binary data. So let's dump the data as
hexadecimal values.

Here is an example session protocol:

=> efidebug boot add 00a1 label1 scsi 0:1 doit1 'my option'
=> efidebug boot add 00a2 label2 scsi 0:1 doit2
=> efidebug boot dump
Boot00A0:
  attributes: A-- (0x00000001)
  label: label1
  file_path: .../HD(1,MBR,0xeac4e18b,0x800,0x3fffe)/doit1
  data:
    00000000: 6d 00 79 00 20 00 6f 00 70 00 74 00 69 00 6f 00  m.y. .o.p.t.i.o.
    00000010: 6e 00 00 00                                      n...
Boot00A1:
  attributes: A-- (0x00000001)
  label: label2
  file_path: .../HD(1,MBR,0xeac4e18b,0x800,0x3fffe)/doit2
  data:

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-02 18:17:50 +02:00
AKASHI Takahiro
ffe2157447 cmd: efidebug: rework "boot dump" sub-command using GetNextVariableName()
Currently in do_efi_boot_dump(), we directly read EFI variables from
related environment variables. To accommodate alternative storage
backends, we should switch to using the UEFI API instead.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-02 18:17:50 +02:00
AKASHI Takahiro
d40e05ae95 efi_loader: set OsIndicationsSupported at init
UEFI variables should be installed using well-defined API.
Currently we don't support much, but the value of OsIndicationsSupported
will be updated once some features are added in the future.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>

Add comments. Rename a variable.

Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-02 18:17:49 +02:00
Heinrich Schuchardt
e00b82db80 efi_loader: FreePages() must fail with pages = 0
The UEFI spec requires that freeing of pages fails if the number of pages
to be freed is 'invalid'. Check that it is not zero.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-02 18:17:49 +02:00
Heinrich Schuchardt
751e928d07 efi_loader: parameter check CreateEventEx()
CreateEvent() and CreateEventEx() should check that a notify function is
provided for either of EVT_NOTIFY_SIGNAL or EVT_NOTIFY_WAIT.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-02 18:17:49 +02:00
Tom Rini
3570ea1f98 Improvements and new features:
- improved SPI driver for better read throughput
 - refactors initialisation of debug UART init
 - restructures header file paths
 - adds pinctrl improvements
 
 Adds Kever as a co-custodian.
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Merge tag 'rockchip-for-2019.07' of git://git.denx.de/u-boot-rockchip

Improvements and new features:
- improved SPI driver for better read throughput
- refactors initialisation of debug UART init
- restructures header file paths
- adds pinctrl improvements

Adds Kever as a co-custodian.
2019-05-01 11:52:04 -04:00
Tom Rini
b4ee6daad7 Porting to DM and i.MX8
------------------------
 
 - warp7 to DM
 - kp_imx53 to DM
 - Warnings in DT
 - MX8QM support
 - colibri-imx6ull to DM
 - imx7d-pico to DM
 - ocotp for MX8
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Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imx

Porting to DM and i.MX8
------------------------

- warp7 to DM
- kp_imx53 to DM
- Warnings in DT
- MX8QM support
- colibri-imx6ull to DM
- imx7d-pico to DM
- ocotp for MX8
2019-05-01 07:25:51 -04:00
Philipp Tomsich
dd320e122f rockchip: rk3288: include header for back_to_bootrom
To avoid a warning, we need to include the header defining
back_to_bootrom for us.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:59 +02:00
Philipp Tomsich
8c5805a210 rockchip: rk3399: include gpio.h
After applying the series for debug_uart_init(), Travis-CI reports:

arch/arm/mach-rockchip/rk3399/rk3399.c:90:2: error: implicit declaration of function 'spl_gpio_set_pull' [-Werror=implicit-function-declaration]
  spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
  ^~~~~~~~~~~~~~~~~

This is caused by a missing header-file include.  Fix it.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:59 +02:00
Kever Yang
c79bce16e5 rockchip: rk3399: add board_debug_uart_init()
Use board_debug_uart_init() for UART iomux init instead of
do it in board_init_f, and move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file for all rockchip SoCs later.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:59 +02:00
Kever Yang
f9e8145614 rockchip: rk3399: use grf structure to access reg
Prefer to use structure to access register if we could.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
6a03335714 rockchip: rk3368: move board_debug_uart_init() to rk3368.c
Move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file later for all rockchip SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
e83e885e53 rockchip: rk3288: add board_debug_uart_init()
Use board_debug_uart_init() for UART iomux init instead of
do it in board_init_f, and move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file for all rockchip SoCs later.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
070e48b30e rockchip: rk3288: use grf structure to access soc_con2
Prefer to use structure to access register if we can.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
28fe4d5b30 rockchip: rk322x: move board_debug_uart_init() to rk322x.c
Move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file later for all rockchip SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed up header-list to not break FASTBOOT:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
86d0eca451 rockchip: rk3188: add board_debug_uart_init()
Use board_debug_uart_init() for UART iomux init instead of
do it in board_init_f, and move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
7f3eec03d5 rockchip: rk3036: add board_debug_uart_init()
Use board_debug_uart_init() for UART iomux init instead of
do it in board_init_f, and move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed whitespace error:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 09:40:58 +02:00
Kever Yang
2b2ff1bd87 rockchip; kylin-rk3036: enabl DEBUG UART
Enable debug uart for kylin board in defconfig.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:57 +02:00
Kever Yang
b0a569da08 rockchip: enable DEBUG_UART_BOARD_INIT by default
All Rockchip SoCs use DEBUG_UART_BOARD_INIT to init per board
UART IOMUX, enable it by default.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:06 +02:00
Kever Yang
b1b449bf1f rockchip: correct ARCH_SOC name
The ARCH_SOC name default as 'rockchip' and we put all the
header file in 'arch/arm/include/asm/arch-rockchip/', but
the 'rockchip' is not the SOC name, let's correct it after
we update all the source file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsiich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Kever Yang
15f09a1a83 rockchip: use 'arch-rockchip' as header file path
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common
header file path, so that we can get the correct path directly.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Kever Yang
6916dad511 rockchip: arm: use 'arch-rockchip' for common header
rockchip platform header file is in 'arch-rockchip'
instead of arch-$(SOC) for all SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Kever Yang
37dc8aaa18 rockchip: add Kever Yang as co-custodian
This updates MAINTAINERS and git-mailrc to add me as a
co-custodian for rockchip

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Tom Rini <trini@konsulko.com>
2019-05-01 00:00:05 +02:00
Kever Yang
9f09b9d3cc rockchip: arm: remove no use macro
TIMER7_BASE is no used by source code now, remove it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Urja Rannikko
59ef021b99 rk3288-board: remove pinctrl call for debug uart
This failed and caused a boot failure on c201, and afaik
the pins should be setup by the new pinctrl driver.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Urja Rannikko
63402831e0 pinctrl: exit pinconfig_post_bind if there are no subnodes
This fixes RK3288 SPL hanging or hitting this assert:
drivers/core/ofnode.c:183: ofnode_first_subnode: Assertion `ofnode_valid(node)' failed.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Jagan Teki
ed9c9059f2 rockchip: rk3399: Add Orangepi RK3399 support
Add initial support for Orangepi RK3399 board.

Specification
- Rockchip RK3399
- 2GB/4GB DDR3
- 16GB eMMC
- SD card slot
- RTL8211E 1Gbps
- AP6356S WiFI/BT
- HDMI In/Out, DP, MIPI DSI/CSI
- Mini PCIe
- Sensors, Keys etc
- DC12V-2A and DC5V-2A

Commit details about Linux DTS sync:
"arm64: dts: rockchip: Add support for the Orange Pi RK3399"
(sha1: d3e71487a790979057c0fdbf32f85033639c16e6)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Jagan Teki
e05b4a4fa8 rockchip: dts: rk3399: Create initial rk3399-u-boot.dtsi
u-boot,dm-pre-reloc is required for SDMMC booted rk3399 boards and
which is U-Boot specific devicetrees binding.

Move it on global rk3399-u-boot.dtsi file and rest of the U-Boot
bindings will move it future based on the requirement.

This would help to sync the devicetrees from Linux whenever required
instead of adding specific nodes.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Jagan Teki
288dbc66da rockchip: dts: rk3399: Sync rk3399-opp from Linux
Sync rk3399-opp.dtsi from Linux.

Linux commit details about the rk3399-opp.dtsi sync:
"arm64: dts: rockchip: use SPDX-License-Identifier"
(sha1: 4ee99cebd486238ac433da823b95cc5f8d8a6905)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:04 +02:00
Philipp Tomsich
2236149e49 rockchip: spi: make optimised receive-handler unaligned-safe
To support unaligned output buffers (i.e. 'in' in the terminology of
the SPI framework), this change splits each 16bit FIFO element after
reading and writes them to memory in two 8bit transactions.  With this
change, we can now always use the optimised mode for receive-only
transcations independent on the alignment of the target buffer.

Given that we'll run with caches on, the impact should be negligible:
as expected, this has no adverse impact on throughput if running with
a 960MHz LPLL configuration.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:04 +02:00
Philipp Tomsich
51a644a1b8 rockchip: spi: add driver-data and a 'rxonly_manages_fifo' flag
The SPI controller's documentation (I only had access to the RK3399,
RK3368 and PX30 TRMs) specifies that, when operating in master-mode,
the controller will stop the SCLK to avoid RXFIFO overruns and TXFIFO
underruns.  Looks like my worries that we'd need to support DMA-330
(aka PL330) to make any further progress were unfounded.

This adds a driver-data structure to capture hardware-specific
settings of individual controller instances (after all, we don't know
if all versions are well-behaved) and adds a 'master_manages_fifo'
flag to it.  The first use of said flag is in the optimised
receive-only transfer-handler, which can now request 64Kframe
(i.e. 128KByte) bursts of data on each reprogramming of CTRLR1
(i.e. every time through the loop).

This improves throughput to 46.85MBit/s (a 94.65% bus-utilisation).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:04 +02:00
Philipp Tomsich
8aa6c921f7 rockchip: spi: add optimised receive-only implementation
For the RK3399-Q7 we recommend storing SPL and u-boot.itb in the
on-module 32MBit (and sometimes even larger, if requested as part of a
configure-to-order configuration) SPI-NOR flash that is clocked for a
bitrate of 49.5MBit/s and connected in a single-IO configuration (the
RK3399 only supports single-IO for SPI).

Unfortunately, the existing SPI driver is excruciatingly slow at
reading out large chunks of data (in fact it is just as slow for small
chunks of data, but the overheads of the driver-framework make it less
noticeable): before this change, the throughput on a 4MB read from
SPI-NOR is 8.47MBit/s which equates a 17.11% bus-utilisation.

To improve on this, this commit adds an optimised receive-only
transfer (i.e.: out == NULL) handler that hooks into the main transfer
function and processes data in 16bit frames (utilising the full with
of each FIFO element).  As of now, the receive-only handler requires
the in-buffer to be 16bit aligned.  Any lingering data (i.e. either if
the in-buffer was not 16-bit aligned or if an odd number of bytes are
to be received) will be handled by the original 8bit reader/wirter.

Given that the SPI controller's documentation does not guarantuee any
interlocking between the RXFIFO and the master SCLK, the transfer loop
will be restarted for each chunk of 32 frames (i.e. 64 bytes).

With this new receive-only transfer handler, the throughput for a 4MB
read increases to 36.28MBit/s (i.e. 73.29% bus-utilisation): this is a
4x improvement over the baseline.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reported-by: Klaus Goger <klaus.goger@theobroma-systems.com>

Series-Cc: Klaus Goger <klaus.goger@theobroma-systems.com>
Series-Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com>
2019-05-01 00:00:04 +02:00
Philipp Tomsich
7e0e5c552f rockchip: spi: only wait for completion, if transmitting
The logic in the main transmit loop took a bit of reading the TRM to
fully understand (due to silent assumptions based in internal logic):
the "wait until idle" at the end of each iteration through the loop is
required for the transmit-path as each clearing of the ENA register
(to update run-length in the CTRLR1 register) will implicitly flush
the FIFOs... transmisson can therefore not overlap loop iterations.

This change adds a comment to clarify the reason/need for waiting
until the controller becomes idle and wraps the entire check into an
'if (out)' to make it clear that this is required for transfers with a
transmit-component only (for transfers having a receive-component,
completion of the transmit-side is trivially ensured by having
received the correct number of bytes).

The change does not increase execution time measurably in any of my
tests.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:04 +02:00
Philipp Tomsich
b6101e906f rockchip: spi: consistently use false/true with rkspi_enable_chip
While rkspi_enable_chip is called with true/false everywhere else in
the file, one call site uses '0' to denot 'false'.
This change this one parameter to 'false' and effects consistency.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:04 +02:00
Philipp Tomsich
e647decdd9 rockchip: spi: fix off-by-one in chunk size computation
The maximum transfer length (in a single transaction) for the Rockchip
SPI controller is 64Kframes (i.e. 0x10000 frames) of 8bit or 16bit
frames and is encoded as (num_frames - 1) in CTRLR1.  The existing
code subtracted the "minus 1" twice for a maximum transfer length of
0xffff (64K - 1) frames.

While this is not strictly an error (the existing code is correct, but
leads to a bit of head-scrating), fix this off-by-one situation.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:04 +02:00
Philipp Tomsich
0e661b6df0 rockchip: spi: remove unused code and fields in priv
Even though the priv-structure and the claim-bus function contain
logic for 16bit frames and for unidirectional transfer modes, neither
of these is used anywhere in the driver.

This removes the unused (as in "has no effect") logic and fields.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:04 +02:00
Philipp Tomsich
f92cf0adca rockchip: spi: add debug message for delay in CS toggle
In analysing delays introduced for large SPI reads, the absence of any
indication when a delay was inserted (to ensure the CS toggling is
observed by devices) became apparent.

Add an additional debug-only debug message to record the insertion and
duration of any delay (note that the debug-message will cause a delay
on-top of the delay-duration).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:04 +02:00
Philipp Tomsich
4abf5d0c02 rockchip: rk3399-puma: support Gigadevice SPI-NOR flash
Over the last quarter, a part of our production has used NOR flash
from Gigadevice in addition to the Winbond parts that we typically
source.  This requires the SPI_FLASH_GIGADEVICE config to be set.

Enable SPI_FLASH_GIGADEVICE in the board's default defconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2019-05-01 00:00:03 +02:00
Tom Rini
a69120a0d7 Prepare v2019.07-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-04-29 21:54:04 -04:00
Simon Goldschmidt
f89d6133ee configs: move CONFIG_SPL_TEXT_BASE to Kconfig
Moved CONFIG_SPL_TEXT_BASE to common/spl/Kconfig and migrate existing
values.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
[trini: Re-run migration]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-04-29 21:41:40 -04:00
Tom Rini
d168bcb6fe configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-04-29 21:41:40 -04:00
Simon Goldschmidt
7110259f55 dts: arm: socfpga: fix socfpga_de10_nano console
Booting this board failed as the initial console isn't found since
commit c402e81702 ("dts: arm: socfpga: merge gen5 devicetrees from linux")

The uart0 devicetree entry was missing "clock-frequency = <100000000>:"
since that commit

Fixes: c402e81702 ("dts: arm: socfpga: merge gen5 devicetrees from linux")
Reported-by: rafael mello <rafaelmello_3@hotmail.com>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-29 20:33:23 +02:00
Marek Vasut
c5f4b80575 ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
The usage of socfpga_sdram_apply_static_cfg() seems rather dubious and
is confirmed to lead to a rare system hang when enabling bridges. This
patch removes the socfpga_sdram_apply_static_cfg() altogether, because
it's use seems unjustified and problematic.

The socfpga_sdram_apply_static_cfg() triggers write to SDRAM staticcfg
register to set the applycfg bit, which according to old vendor U-Boot
sources can only be written when there is no traffic between the SDRAM
controller and the rest of the system. Empirical measurements confirm
this, setting the applycfg bit when there is traffic between the SDRAM
controller and CPU leads to the SDRAM controller accesses being blocked
shortly after.

Altera originally solved this by moving the entire code which sets the
staticcfg register to OCRAM [1]. The commit message claims that the
applycfg bit needs to be set after write to fpgaportrst register. This
is however inverted by Altera shortly after in [2], where the order
becomes the exact opposite of what commit message [1] claims to be the
required order. The explanation points to a possible problem in AMP
use-case, where the FPGA might be sending transactions through the F2S
bridge.

However, the AMP is only the tip of the iceberg here. Any of the other
L2, L3 or L4 masters can trigger transactions to the SDRAM. It becomes
rather non-trivial to guarantee there are no transactions to the SDRAM
controller.

The SoCFPGA SDRAM driver always writes the applycfg bit in SPL. Thus,
writing the applycfg again in bridge enable code seems redundant and
can presumably be dropped.

[1] 75905816ec
[2] 8ba6986b04

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-04-29 10:33:45 +02:00
Marek Vasut
bdb5df1a06 mmc: dw_mmc: Round up descriptor end to nearest multiple of cacheline size
The driver currently calculates the end address of cache flush operation
for the DMA descriptors by adding cacheline size to the start address of
the last DMA descriptor. This is not safe, as the cacheline size may be,
in some unlikely cases, smaller than the DMA descriptor size. Replace the
addition with roundup() applied on the end address of the last DMA
descriptor to round it up to the nearest cacheline size multiple.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
2019-04-29 10:08:56 +02:00
Marek Vasut
6ad5aec419 mmc: dw_mmc: Handle return value from bounce_buffer_start()
The bounce_buffer_start() can return -ENOMEM in case memory allocation
failed. However, in that case, the bounce buffer address is the same as
the possibly unaligned input address, and the cache maintenance operations
were not applied to this address. This could cause subtle problems. Add
handling for the bounce_buffer_start() return value to prevent such a
problem from happening.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
2019-04-29 10:08:56 +02:00