Update DDR configuration with the latest update:
- PUBL_regs: DXnGCR[0]= according to ddr_width to disable Byte
lane 2/3 in 16bit
- fix LPDDR2/3 timing_calc to step RL/WL in relaxed
timings mode
- remove LPDDR3 RL3 (optional) support vs MR0[7]
because MR0[7] can't be read instead always apply
worse RL/WL for LPDDR3 when freq < 166MHz)
- change MR3 to 48ohm drive for LPDDR2/3
- change default ZPROG[7:4] = 0x1 for LPDDR2/3 ,
'0' is not allowed even when ODT not used
- use DQSTRN for LPDDR2/3 (it was not set in PIR)
- LPDDR3: set dqsge/dwsgx gate extension to 2,2
like LPDDR2
-DDRCTRL.dfitmg0:
+ for LPDDR3 tphy_wrlat = WL (as LPDDR2)
+ improvement for relaxed mode vs RL/Wl at corner case.
For example @533MHz RL/WL (relaxed) = 9/5 for LPDDR2/3
and correction to MR2 accordingly
- DDR_PCFGQOS1_1: port1 timeout relaxed from 0x00 to 0x40,
for LTDC.
- DDR_PCFGWQOS0_0: change vpr level from
11 to 12 in order to include the CPU on
the variable priority queue.
- DDR_SCHED: fix to consider 13 levels (13 levels - 1 = 0xC)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This patch synchronizes U-boot DT with kernel one
This is based on https://patchwork.kernel.org/cover/10797115/
This patch adds initial support of STM32MP157 discovery boards:
- Add support of stm32mp157a discovery1 board (part number: STM32MP157A-DK1).
This board embeds a STM32MP157a SOC with AC package (TFBGA361, 148 ios)
and 512MB of DDR3. Several connections are available on this boards:
4*USB2.0, 1*USB2.0 typeC, SDcard, RJ45, HDMI, Arduino connector, ...
- Add support of stm32mp157c discovery2 board (part number: STM32MP157C-DK2).
This board is a "super-set" of stm32mp157a-dk1. A display panel (otm8009a)
and Murata wifi/BT combo is added.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
