Commit graph

196 commits

Author SHA1 Message Date
David Wu
4ee6d51c5a pwm: rk_pwm: Make PWM driver to support all Rockchip Socs
This PWM driver can be used to support pwm functions
for on all Rockchip Socs.

The previous chips than RK3288 did not support polarity,
and register layout was different from the RK3288 PWM.

The RK3288 keep the current functions.

RK3328 and the chips after it, which can support hardware lock,
configure duty, period and polarity at next same period, to
prevent the intermediate temporary state.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-06 00:06:23 +08:00
Paul Kocialkowski
c541bfda2f rockchip: px30: Add support for using UART3 as debug UART
Some generic PX30 SoMs found in the wild use UART3 as their debug output
instead of UART2 (used for MMC) and UART5.

Make it possible to use UART3 as early debug output, with the associated
clock and pinmux configuration. Two sets of output pins are supported (M0/M1).

Future users should also note that the pinmux default in the dts is to use
the M1 pins while the Kconfig option takes M0 as a default.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
2019-12-05 23:53:07 +08:00
Paul Kocialkowski
b0c5e37d0e rockchip: px30: Fixup PMUGRF registers layout order
According to the PX30 TRM, the iomux registers come first, before the pull
and strength control registers.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
2019-12-05 23:53:07 +08:00
Elaine Zhang
bbda2ed584 rockchip: clk: pll: add common pll setting funcs
Common PLL setup function, compatible with different SOC.
Mainly for the subsequent new SOC use.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Heiko Stuebner
a04f6fd17f rockchip: clk: rv1108: remove duplicate reset init
rockchip_reset_bind() already does the needed init for the reset
registers, only referenced the wrong cru structure.

So we can get rid of the open-coded reset init and just fix
the correct cru reference.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Kever Yang
d49a526750 rockchip: clk: add px30 clock driver
The px30 contains 2 separate clock controllers, pmucru and cru.
Add drivers for them.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:23:07 +08:00
Heiko Stuebner
46281a76be rockchip: add core px30 headers
Add headers needed by the upcoming px30 support, including two
new dt-binding headers taken from the Linux kernel.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:23:00 +08:00
Kever Yang
c8863b8508 ram: rk3399: update calculate_stride
Update the calculation of the stride to support all the DRAM case.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
YouMin Chen
a922d0d102 ram: rk3399: migrate to use common code
For there are some structures and functions are common for all rockchip SoCs,
migrate to use the common code so that we can clean up reduandent codes.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
YouMin Chen
ca93e32139 ram: rk3328: use common sdram driver
RK3328 has a similar controller and phy with PX30, so we can use the
common driver for it and remove the duplicate codes.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
YouMin Chen
39edfaa758 ram: px30: add sdram driver
Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3.

For TPL_BUILD, the driver implement full dram init and without DM
support due to the limit of internal SRAM size.
For SPL and U-Boot proper, it's a simple driver with dm for get
dram_info like other SoCs.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
c525bb42aa ram: rockchip: add common msch reg definition
The noc register bit definition may be the same for different SoC while
the offset of the register may be different, add the struction
definition as common code.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
691368c7f7 ram: rockchip: add phy driver code for PX30
This sdram_phy_px30.c is based on PX30 SoC, the functions are common
for phy, other SoCs with similar hardware could re-use it.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
09d7872336 ram: rockchip: add controller code for PX30
This sdram_pctl_px30.c is based on PX30 SoC, the functions are common
for controller, other SoCs with similar hardware could re-use it.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
d6647b08b2 ram: rockchip: add common code for sdram driver
There are some function like os_reg setting, capacity detect functions,
can be used as common code for different Rockchip SoCs, add a
sdram_common.c for all these functions.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
9a46f2a4cb rockchip: sdram: extend to use sys_reg3 for capacity info
Since we have new DRAM type and to support different DRAM size in different
CS, we need more bits, so introduce sys_reg3 to record the info.
Note that the info in sys_reg3 is extension to sys_reg2 and the info in
sys_reg2 is the same as before. We define the DRAM_INFO with sys_reg3 as
VERSION2.
All the ENC macro are moved to sdram_common.h since the sdram.c only
need to do the info decode.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
d5d40f45de rockchip: sdram: move cap structure and debug function to sdram_common.h
The sdram.h suppose to be helper file for sdram.c which including dram
size decode and some u-boot related dram init interface, and all
structure and function for dram driver move to sdram_common.h

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
5d19ddf0db ram: rockchip: rename sdram_common.c/h to sdram.c
rename sdram_common.c in arch/arm/mach-rockchip to sdram.c;
so that we can use the file name sdram_common.c in dram driver for
better understand the code;
clean the related file who has use the header file at the same time.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
2a2f0b177c ram: rockchip: rename sdram.h to sdram_rk3288.h
The header file sdram.h is used for rk3288 and similar SoCs, rename it
to make it more understandable.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Simon South
2cbdb6e051 clk: rockchip: rk3328: Configure CPU clock
Add a call to rk3328_configure_cpu() during initialization to set the
CPU-clock frequency.

Signed-off-by: Simon South <simon@simonsouth.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:40:20 +08:00
Rohan Garg
0482538499 rockchip: rk3399: derive ethaddr from cpuid
Generate a MAC address based on the cpuid available in the efuse
block: Use the first 6 byte of the cpuid's SHA256 hash and set the
locally administered bits. Also ensure that the multicast bit is
cleared.

The MAC address is only generated and set if there is no ethaddr
present in the saved environment.

This is based off of Klaus Goger's work in 8adc9d

Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-23 18:15:31 +08:00
Kever Yang
85a38742e0 rockchip: ram: add full feature rk3328 DRAM driver
This driver supports DDR3/LPDDR3/DDR4 SDRAM initialization.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[cherry picked from commit 9fb0777ec3 with minor modifications]
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:14:45 +08:00
Kever Yang
faa98c7c5a rockchip: rk3399: move chromebook bob specific flow to its board file
Add a board_early_init_f() in board_init_f() and move the board
specific init code into its own board file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Kever Yang
bfcf15aad2 rockchip: declear boot_devices in bootrom.h
boot_devices may defined in soc file, and used in board file,
we need to delear it in header file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-26 17:30:26 +08:00
Kever Yang
cd59501f21 rockchip: intruduce common BROM_BOOTSOURCE_ID_ADDR
The boot source from BootRom is store at a fix offset of IRAM,
update to use the common macro instead of rk3399 specific one.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-26 17:30:26 +08:00
Kever Yang
0845a0ee66 rockchip: remove rk_timer
We have convert all SoC to use DM timer or ARM arch/generic
timer, we can remove this rk_timer now.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Kever Yang
25c6173099 rockchip: rk3288: move configure_l2ctlr back to rk3288
The configure_l2ctlr() is used only by rk3288, do not need to
locate in sys_proto.h

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
614d8ca438 arm: include: rockchip: Add rk3399 pmu file
Add pmu header file for rk3399 SoC, this will help
to configure pmu in sdram driver.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21 00:00:13 +08:00
Jagan Teki
a735550bb8 ram: rk3399: Add DdrMode
Add DdrMode structure with associated bit fields.

These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
ed77ce728a ram: rk3399: Add ddrtimingC0
Add DdrTimingC0 structure with associated bit fields.

These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
b713e0291b ram: rk3399: Add ddr version enc macro
Add dram config macro for handling ddr version number.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
01cc103915 ram: rk3399: Introduce sys_reg3 for more capacity info
cs0_row, cs1_row and cs1_col needs more bits to show its
correct value, update to make use of both sys_reg2,
sys_reg3.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
(Squash similar patches into one patch)
Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
879f9fed6a ram: rk3399: Simply existing dram enc macro
Add simplified and meaningful macro for all setting.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
(Squash the similar patches into 1 patch)
Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20 23:59:44 +08:00
Jagan Teki
cb13534abe ram: rk3399: debug: Add sdram_print_stride
Add code to print the channel stride, this would help to
print the stride of associated channel.

Here is sample print on LPDDR4, 50MHz.
256B stride

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:10 +08:00
Jagan Teki
07894f5aac ram: rockchip: debug: Add sdram_print_ddr_info
Add sdram ddr info print support, this would help to
observe the sdram base parameters.

Here is sample print on LPDDR4, 50MHz channel 0
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:10 +08:00
Jagan Teki
07112672a5 ram: rockchip: Add debug sdram driver
Add sdram driver to handle debug across rockchip SoCs.

This would help to improve code debugging feature for
sdram drivers in rockchip family, whoever wants to
debug the driver should call these core debug code on
their respective platform sdram drivers.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
7757d1102f arm: include: rockchip: Add DDR4 enum
Add DDR4 enum number in common header.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
fafd2ad4df arm: include: rockchip: Move dramtypes to common header
dramtype enum numbers as common across all dram controllers
in rockchip, so move the eneum values in common header.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
e5e444aaa5 ram: rk3399: Move common sdram structures in common header
Move common sdram structures like sdram_cap_info, sdram_base_params
into sdram_common header, this would help to reuse the same
from another controllers like px30.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
1372a6ec47 ram: rk3399: s/rk3399_base_params/sdram_base_params
Most of the ddr parameters are common in rk3399_base_params
structure and which would reuse it in another controller like
px30 in future.

So, rename the structure from rk3399_base_params into
sdram_base_params.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Jagan Teki
355490dc5c ram: rockchip: rk3399: Add cap_info structure
Group common ddr attributes like
- rank
- col
- bk
- bw
- dbw
- row_3_4
- cs0_row
- cs1_row
- ddrconfig

into a common cap_info structure for more code readability and extend
if possible based on the new features.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Christoph Muellner
dee5ad5ae7 rockchip: pinctrl: rk3399: Add support for UART3.
This patch adds the missing GRF bit definitions for UART3 on the RK3399.

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-30 18:22:35 +08:00
Kever Yang
6b780e441b rockchip: boot0: update CONFIG_ROCKCHIP_SPL_RESERVE_IRAM for SPL only
The CONFIG_ROCKCHIP_SPL_RESERVE_IRAM is for SPL only, add
condition to limit it not affect TPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
15f09a1a83 rockchip: use 'arch-rockchip' as header file path
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common
header file path, so that we can get the correct path directly.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Kever Yang
9f09b9d3cc rockchip: arm: remove no use macro
TIMER7_BASE is no used by source code now, remove it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Simon Glass
9e92116bc8 rockchip: Add support for chromebook_bob
Bob is a 10-inch chromebook produced by Asus. It has two USB 3.0 type-C
ports, 4GB of SDRAM, WiFi and a 1280x800 display. It uses its USB ports
for both power and external display. It includes a Chrome OS EC
(Cortex-M3) to provide access to the keyboard and battery functions.

Support so far includes only:
- UART
- SDRAM
- MMC, SD card
- Cros EC (but not keyboard)

Not included:
- Keyboard
- Display
- Sound
- USB
- TPM

Bob is quite similar to Kevin, the Samsung Chromebook Plus, but support
for this is not provided in this series.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
aa48c94ca8 rockchip: Implement spl_gpio in the GPIO driver
Allow rockchip boards to use GPIOs before driver model is ready. This is
really only useful for setting GPIOs to enable the early debug console, if
needed on some platforms.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
3ec6f11c7d rockchip: Move pull-up/down enum into a common file
At present this enum is only available to rk3288. Move it so that other
rockchip SoCs can access it. It is needed for the SPL GPIO driver for
rk3999 in a later patch.

Also adjust the enum name to lower case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
3dbfe5ae61 rockchip: rk3288: Add i2s pinctrl and clock support
Add support for setting pinctrl and clock for I2S on rk3288. This allows
the sound driver to operate. These settings were created by rkmux.py

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Christoph Muellner
af765a49ba rockchip: rk3399: Initialize CPU B clock.
This patch sets the PLL of CPU cluster B (BPLL) to 600 MHz.
This decreases the boot time of Linux 4.19 by about 8%.

The 600 MHz are inspired by the 600 MHz used for LPLL initialization
(came in with commit 9f636a249c).

Tested on RK3399-Q7 on Haikou base board.

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 21:56:45 +01:00