Commit graph

2197 commits

Author SHA1 Message Date
Masahiro Yamada
643aae1406 include: delete include/linux/config.h
Linux Kernel abolished include/linux/config.h long time ago.
(around version v2.6.18..v2.6.19)

We don't need to provide Linux copatibility any more.

This commit deletes include/linux/config.h
and fixes source files not to include this.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-08 15:25:13 -05:00
Masahiro Yamada
0f0f75774e cosmetic: remove empty lines at the top of file
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-08 09:41:37 -05:00
Rob Herring
5b6da28352 ARM: versatile: convert to common timer code
Convert versatile to use the commmon timer code.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-11-04 11:24:22 -05:00
Rob Herring
31df9893b9 ARM: tegra: convert to common timer code
Convert tegra to use the commmon timer code.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-11-04 11:24:22 -05:00
Rob Herring
23ab7ee0ff ARM: socfpga: convert to common timer code
Convert socfpga to use the commmon timer code.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-11-04 11:23:45 -05:00
Rob Herring
3dae5b510e ARM: mx25: convert to common timer code
Convert mx25 to use the commmon timer code.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-11-04 11:09:34 -05:00
Rob Herring
9df1bd416d ARM: highbank: convert to common timer code
Convert highbank to use the commmon timer code.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-11-04 11:08:10 -05:00
Rob Herring
f232950f82 config: remove platform CONFIG_SYS_HZ definition part 2/2
Remove platform CONFIG_SYS_HZ definition for configs a-z*.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-11-04 11:06:16 -05:00
Masahiro Yamada
09ab61c660 ARM: s5pc, exynos: move Samsung ARM SoC specific code under arch/arm/
This patch moves S5PC, EXYNOS specific directory entries
from the toplevel Makefile to arch/arm/cpu/armv7/Makefile
using Kbuild descending feature.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
2013-10-31 13:26:44 -04:00
Masahiro Yamada
3c5edd8ca5 ARM: omap: move OMAP specific code under arch/arm/
This patch moves OMAP specific directory entries
from the toplevel Makefile and spl/Makefile
to arch/arm/cpu/armv7/Makefile using Kbuild descending feature.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
2013-10-31 13:26:44 -04:00
Masahiro Yamada
37d82beb57 ARM: tegra: move Tegra specific code under arch/arm/
This patch moves Tegra specific directory entries
from the toplevel Makefile and spl/Makefile
to arch/arm/cpu/*/Makefile using Kbuild descending feature.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Warren <TWarren@nvidia.com>
2013-10-31 13:26:44 -04:00
Masahiro Yamada
71f84ef073 ARM: imx-common: convert makefiles to Kbuild style
Multiple targets are included in arch/arm/imx-common/Makefile
In order to refactor it,
we need to tweak Makefile and spl/Makefile.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 13:20:39 -04:00
Masahiro Yamada
fa8f95084d ARM: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 12:53:39 -04:00
Masahiro Yamada
3d9c84737b arm720t: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 12:53:39 -04:00
Masahiro Yamada
833db7405a arm920t: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 12:53:39 -04:00
Masahiro Yamada
d8769c62c1 arm926ejs: convert makefiles to Kbuild style
Note1:
In arch/arm/cpu/arm926ejs/spear/Makefile
START := start.o
was changed
extra-$(CONFIG_SPL_BUILD) := start.o
because spear/start.o is only used for SPL.

Note2:
START := start.o
was missing from arch/arm/cpu/arm926ejs/mxs/Makefile.
This commit simply adds
extra-$(CONFIG_SPL_BUILD) := start.o

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 12:53:39 -04:00
Masahiro Yamada
4e1aa8437a armv7: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 12:53:39 -04:00
Rajeshwari Shinde
6f0b7caa67 DWMMC: SMDK5420: Disable SMU for eMMC
SMDK5420 has a new Security Management Unit added
for dwmmc driver, hence, configuring the control
registers to support booting via eMMC.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2013-10-31 09:55:33 +02:00
Tom Rini
748bde608a Merge branch 'master' of git://git.denx.de/u-boot-usb 2013-10-21 08:10:36 -04:00
Dan Murphy
3d799c7f5e usb: am437x: Add support for am437x xhci USB host
Add the support for the am437x xhci usb host.

The xHCI host on AM437 is connected to a usb2 phy so need to
add support to enable those clocks.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-10-20 23:42:41 +02:00
Dan Murphy
834e91af43 usb: dra7xx: Add support for dra7xx xhci USB host
Add the support for the dra7xx xhci usb host.
dra7xx does not contain an EHCI controller so the headers
can be removed from the board file.

The xHCI host on dra7xx is connected to a usb2 phy so need to
add support to enable those clocks.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-10-20 23:42:41 +02:00
Dan Murphy
41b667b834 usb: omap: Move the xhci-omap header file to common location
Moving the xhci-omap header to a more global location so that
other code can reference this code.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-10-20 23:42:41 +02:00
Mateusz Zalega
16297cfb2a usb: new board-specific USB init interface
This commit unifies board-specific USB initialization implementations
under one symbol (usb_board_init), declaration of which is available in
usb.h.

New API allows selective initialization of USB controllers whenever needed.

Signed-off-by: Mateusz Zalega <m.zalega@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Lukasz Majewski <l.majewski@samsung.com>
2013-10-20 23:42:40 +02:00
Troy Kisky
7132869d4c mx6: iomux: add GPR1 defines for use with nitrogen6x
Select GPIO1 as the USB OTG ID pin for Nitrogen6x

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-10-20 23:42:40 +02:00
Dan Murphy
2d2358ac15 OMAP5: USB: Add OMAP xHCI file and header
Add the OMAP file for the xHCI Host controller
This code will initilialize the proper components within the
OMAP5 to enable the xHCI host controller.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-10-20 23:42:39 +02:00
Dan Murphy
d861a333da ARM: OMAP5: Add registers and defines for USBOTG SS
Add the prcm registers and the bit definitions to enable the
USB SS port of the OMAP5 device.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-10-20 23:42:39 +02:00
Vivek Gautam
28cfef5f41 exynos5: dts: Add device node for XHCI
Adding device node for xhci host controller to enable
usb 3.0 on exynos5250.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dan Murphy <dmurphy@ti.com>
Cc: Marek Vasut <marex@denx.de>
2013-10-20 23:42:38 +02:00
Vivek Gautam
80c4c5964f arm: exynos: Add methods to control power to USB 3.0 PHY
Adding methods to turn on/off power to USB3.0 type PHY
as and when required by the controller.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dan Murphy <dmurphy@ti.com>
Cc: Marek Vasut <marex@denx.de>
2013-10-20 23:42:38 +02:00
Vivek Gautam
13194f3b5f USB: XHCI: Add xHCI host controller support for Exynos5
This adds driver layer for xHCI controller in Samsung's
exynos5 soc. This interacts with xHCI host controller stack.

Signed-off-by: Vikas C Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dan Murphy <dmurphy@ti.com>
Cc: Marek Vasut <marex@denx.de>
2013-10-20 23:42:38 +02:00
trem
fac9640895 i2c: mxc: move to new subsystem
Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
2013-10-17 07:20:24 +02:00
Wolfgang Denk
16641d52fc Coding Style cleanup: drop some excessive empty lines
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:54 -04:00
Wolfgang Denk
d4c8aa9cb4 Coding Style cleanup: remove trailing empty lines
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:54 -04:00
Wolfgang Denk
93e1459641 Coding Style cleanup: replace leading SPACEs by TABs
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Drop changes for PEP 4 following python tools]
Signed-off-by: Tom Rini <trini@ti.com>
2013-10-14 16:06:54 -04:00
Wolfgang Denk
3765b3e7bd Coding Style cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:53 -04:00
Dan Murphy
e84b8f6ce0 ARM: omap4-panda: Add MAC address creation for panda
Add a MAC address create based on the OMAP die ID registers.
Then poplulate the ethaddr enviroment variable so that the device
tree alias can be updated prior to boot.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-10-14 16:06:53 -04:00
Dan Murphy
47a4bea6af ARM: omap4: Update sdram setting for panda rev A6
OMAP4 panda rev A6 is a 4430 es2.3 IC with an updated memory
part.

The panda rev A6 uses Elpida 2x4Gb memory and no longer uses Micron
so the timings needs to be updated

Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-10-14 16:06:52 -04:00
Tom Rini
9f3fe6da27 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-10-08 09:51:48 -04:00
Tom Rini
968294bd7b Merge branch 'master' of git://git.denx.de/u-boot-spi 2013-10-08 09:03:15 -04:00
Rajeshwari Shinde
c4a796329d spi: exynos: Support word transfers
Since SPI register access is so expensive, it is worth transferring data
a word at a time if we can. This complicates the driver unfortunately.

Use the byte-swapping feature to avoid having to convert to/from big
endian in software.

This change increases speed from about 2MB/s to about 4.5MB/s.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-10-08 18:18:12 +05:30
Chin Liang See
5d649d2b08 socfpga: Adding System Manager driver
Adding System Manager driver which will configure the
pin mux for real hardware Cyclone V development kit
(not Virtual Platform)

Signed-off-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2013-10-07 19:32:21 +02:00
Albert ARIBAUD
0610a16cf2 omap1510inn: arm925t: remove support
omap1510inn is orphan and has been for years now.
Reove it and, as it was the only arm925t target,
also remove arm925t support.
Update doc/README.scrapyard accordingly.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-10-07 19:25:19 +02:00
Poddar, Sourav
62d206dc31 armv7: hw_data: change clock divider setting.
Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,

f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)

fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-10-07 17:55:51 +05:30
Matt Porter
c97a9b3275 omap5: add qspi support
Add QSPI definitions and clock configuration support.

Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-10-07 17:55:50 +05:30
Andre Przywara
f833e790b4 ARM: virtualization: replace verbose license with SPDX identifier
The original creation of arch/arm/cpu/armv7/{virt-v7.c,nonsec_virt.S}
predates the SPDX conversion, so the original elaborate license
statements sneaked in.
Fix this by replacing them with the proper abbreviation.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-07 08:21:13 -04:00
Enric Balletbo i Serra
94b32f60fe ARM: IGEP0033: Update timing to run DDR at 400MHz.
We can run the DDR at 400MHz, so update the timings for that purpose.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
2013-10-07 07:43:46 -04:00
Tom Rini
f835c77fb7 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-10-04 13:17:48 -04:00
Andre Przywara
d429688754 ARM: extend non-secure switch to also go into HYP mode
For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in non-secure state,
HYP mode switching is within short reach.

While doing the non-secure switch, we have to enable the HVC
instruction and setup the HYP mode HVBAR (while still secure).

The actual switch is done by dropping back from a HYP mode handler
without actually leaving HYP mode, so we introduce a new handler
routine in our new secure exception vector table.

In the assembly switching routine we save and restore the banked LR
and SP registers around the hypercall to do the actual HYP mode
switch.

The C routine first checks whether we are in HYP mode already and
also whether the virtualization extensions are available. It also
checks whether the HYP mode switch was finally successful.
The bootm command part only calls the new function after the
non-secure switch.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 21:28:55 +02:00
Andre Przywara
ba6a169811 ARM: add SMP support for non-secure switch
Currently the non-secure switch is only done for the boot processor.
To enable full SMP support, we have to switch all secondary cores
into non-secure state also.

So we add an entry point for secondary CPUs coming out of low-power
state and make sure we put them into WFI again after having switched
to non-secure state.
For this we acknowledge and EOI the wake-up IPI, then go into WFI.
Once being kicked out of it later, we sanity check that the start
address has actually been changed (since another attempt to switch
to non-secure would block the core) and jump to the new address.

The actual CPU kick is done by sending an inter-processor interrupt
via the GIC to all CPU interfaces except the requesting processor.
The secondary cores will then setup their respective GIC CPU
interface.
While this approach is pretty universal across several ARMv7 boards,
we make this function weak in case someone needs to tweak this for
a specific board.

The way of setting the secondary's start address is board specific,
but mostly different only in the actual SMP pen address, so we also
provide a weak default implementation and just depend on the proper
address to be set in the config file.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 21:28:51 +02:00
Andre Przywara
bb97545565 ARM: trigger non-secure state switch during bootm execution
To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm command implementation.
This way we automatically enable this feature without further user
intervention.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 21:28:46 +02:00
Andre Przywara
1ef923851a ARM: add C function to switch to non-secure state
The core specific part of the work is done in the assembly routine
in nonsec_virt.S, introduced with the previous patch, but for the full
glory we need to setup the GIC distributor interface once for the
whole system, which is done in C here.
The routine is placed in arch/arm/cpu/armv7 to allow easy access from
other ARMv7 boards.

We check the availability of the security extensions first.

Since we need a safe way to access the GIC, we use the PERIPHBASE
registers on Cortex-A15 and A7 CPUs and do some sanity checks.
Boards not implementing the CBAR can override this value via a
configuration file variable.

Then we actually do the GIC enablement:
a) enable the GIC distributor, both for non-secure and secure state
   (GICD_CTLR[1:0] = 11b)
b) allow all interrupts to be handled from non-secure state
   (GICD_IGROUPRn = 0xFFFFFFFF)

The core specific GIC setup is then done in the assembly routine.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 21:28:43 +02:00