Poddar, Sourav 62d206dc31 armv7: hw_data: change clock divider setting. ... Clock requirement for qspi clk is 192 Mhz. According to the below formulae, f dpll = f ref * 2 * m /(n + 1) clockoutx2_Hmn = f dpll / (hmn+ 1) fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz For clockoutx2_Hmn to be 768, hmn + 1 should be 4. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>		2013-10-07 17:55:51 +05:30
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cpu	armv7: hw_data: change clock divider setting.	2013-10-07 17:55:51 +05:30
dts	DTS: Addition of I2S0 channel and replacing I2S1	2013-09-24 09:10:33 -04:00
imx-common	Merge git://git.denx.de/u-boot-arm	2013-07-31 11:30:38 +02:00
include/asm	omap5: add qspi support	2013-10-07 17:55:50 +05:30
lib	ARM: extend non-secure switch to also go into HYP mode	2013-10-03 21:28:55 +02:00
config.mk	ARM: use r9 for gd	2013-09-23 18:00:02 +02:00