Commit graph

106 commits

Author SHA1 Message Date
James Balean
46f51dc9c7 Add 16-bit single register pin controller support
Enables the pinctrl-single driver to support 16-bit registers. Only
32-bit registers were supported previously. Reduced width registers are
required for some platforms, such as OMAP.

Signed-off-by: James Balean <james@balean.com.au>
Cc: Felix Brack <fb@ltec.ch>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Felix Brack <fb@ltec.ch>
Tested-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-11 22:21:26 -04:00
Philipp Tomsich
26e2e404b7 rockchip: pinctrl: rk3399: add support for the HDMI I2C pins
To add HDMI support for the RK3399, this commit provides the needed
pinctrl functionality to configure the HDMI I2C pins (used for reading
the screen's EDID).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Kever Yang
602778d3c7 rockchip: pinctrl: rk3399: add gmac io strength support
GMAC controller need to init the tx io driver strength to 13mA,
just like the description in dts pinctrl node, or else the controller
may only work in 100MHz Mode, and fail to work at 1000MHz mode.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com <mailto:philipp.tomsich@theobroma-systems.com>>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
315e6a38f9 rockchip: pinctrl: rk3399: add support for the SPI5 controller
This commit adds support for the pin-configuration of the SPI5
controller of the RK3399 through the following changes:
 * grf_rk3399.h: adds definition for configuring the SPI5 pins
   		 in the GPIO2C group
 * periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5
 * pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to
   		     PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3
		     through SPI5 to the appropriate pin-config
		     function; implements the pin-configuration
		     for PERIPH_ID_SPI5 using the GPIO2C group

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
maxims@google.com
4f0e44e466 aspeed: AST2500 Pinctrl Driver
This driver uses Generic Pinctrl framework and is compatible with
the Linux driver for ast2500: it uses the same device tree
configuration.

Not all pins are supported by the driver at the moment, so it actually
compatible with ast2400. In general, however, there are differences that
in the future would be easier to maintain separately.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:33 -04:00
Vikas Manocha
58fb3c8d89 stm32f7: increase the max no of pin configuration to 70
The number of pins to be configured could be more than 50 e.g. in case
of sdram controller, there are about 56 pins (32 data lines, 12 address
& some control signals).

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:57:23 -04:00
Vikas Manocha
280057bd7d stm32f7: use stm32f7 gpio driver supporting driver model
With this gpio driver supporting DM, there is no need to enable clocks
for different gpios (for pin muxing) in the board specific code.

Need to increase the allocatable area required before relocation from 0x400 to
0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:21 -04:00
Vikas Manocha
774171020b dm: gpio: Add driver for stm32f7 gpio controller
This patch adds gpio driver supporting driver model for stm32f7 gpio.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Christophe KERELLO <christophe.kerello@st.com>
[trini: Add depends on STM32]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-08 11:57:02 -04:00
Philipp Tomsich
51c7f34809 pinctrl: Kconfig: sort pinctrl config options to prevent future clutter
This originally started out as
     "pinctrl: Kconfig: reorder to keep Rockchip options together"
and tried to keep the Rockchip-related config options together.

However, we now rewrite all chip-specific driver selections to start
with CONFIG_PINCTRL_ (with the inadvertent changes to related
Makefiles) and sort those alphabetically. And as this already means
touching most of the file, we also reformat the help text to not exceed
80 characters (but make full use of those 80 characters).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-27 16:49:04 -04:00
Wenyou Yang
9319a756ff pinctrl: at91: add pinctrl driver
AT91 PIO controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.

Each SoC will have to describe the its limitation and pin
configuration via device tree. This will allow to do not need
to touch the C code when adding new SoC if the IP version is
supported.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-13 14:44:50 -06:00
Philipp Tomsich
476f7090bf rockchip: pinctrl: rk3399: add GMAC (RGMII only) support
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this
point), we need support for additional pin-configuration.  This commit
adds the pinctrl support for GMAC in RGMII signalling mode:
 * adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
 * adds the required defines (in the GRF support) for configuring the
   GPIOC pins for RGMII
 * configures the RGMII pins (in GPIOC) when requested via pinctrl

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:01:57 -06:00
Philipp Tomsich
f3f1af939e rockchip: pinctrl: use per-SoC option names for Kconfig
The config options for pinctrl on the RK3188, RK3288, RK3328 and
RK3399 previously showed up in menuconfig with the generic string
descriptor "Rockchip pin control driver" requiring one to look through
the help/full description to identify which chip each menu entry was
for.

This change renames each option with the chip-name in the description
string to make it easy to identify the configuration options in
menuconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:01:57 -06:00
Felix Brack
44d5c371a6 Add single register pin controller driver
This patch adds a pin controller driver supporting devices
using a single configuration register per pin.
Signed-off-by: Felix Brack <fb@ltec.ch>
2017-03-26 13:23:42 -06:00
Tom Rini
02ccab1908 Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	configs/bk4r1_defconfig
	configs/colibri_vf_defconfig
	configs/pcm052_defconfig
	include/configs/colibri_vf.h
	include/configs/pcm052.h
2017-03-19 15:13:38 -04:00
Tom Rini
f9515756b6 Merge git://git.denx.de/u-boot-rockchip
This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang.  Also included is SPL support for rk3399 and a fix for
rk3288 to get it booting again (spl_early_init()).
2017-03-17 14:15:17 -04:00
Vikas Manocha
94d5308412 PINCTRL: stm32f7: add pin control driver
This driver uses the same pin control binding as that of linux, binding
document of this patch is copied from linux. One addition done is for
GPIO input and output mode configuration which was missing.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-17 14:15:14 -04:00
Peng Fan
4aa9d4d095 pinctrl: Add i.MX7ULP pinctrl driver
Add i.MX7ULP pinctrl driver.
Select CONFIG_PINCTRL_IMX7ULP to use this driver.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by : Stefano Babic <sbabic@denx.de>
2017-03-17 09:27:08 +01:00
Kever Yang
d439a46e46 rockchip: rk3328: add pinctrl driver
Add rk3328 pinctrl driver and grf/iomux structure definition.

Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-03-16 16:03:46 -06:00
Heiko Stübner
155cd37f2c rockchip: rk3188: Add pinctrl driver
Add a driver which supports pin multiplexing setup for the most commonly
used peripherals.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-03-16 16:03:45 -06:00
Heiko Stübner
27326c7ee2 dm: allow limiting pre-reloc markings to spl or tpl
Right now the u-boot,dm-pre-reloc flag will make each marked node
always appear in both spl and tpl. But systems needing an additional
tpl might have special constraints for each, like the spl needing to
be very tiny.

So introduce two additional flags to mark nodes for only spl or tpl
environments and introduce a function dm_fdt_pre_reloc to automate
the necessary checks in code instances checking for pre-relocation
flags.

The behaviour of the original flag stays untouched and still marks
a node for both spl and tpl.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-03-16 16:03:44 -06:00
Kever Yang
6657f66418 rockchip: pinctrl: rk3399: add the of-platdata support
Do not use the API which of-platdata not support.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-03-16 16:03:43 -06:00
Kever Yang
fa72de1045 rockchip: arm64: rk3399: move grf register definitions to grf_rk3399.h
rk3399 grf register bit defenitions should locate in header
file, so that not only pinctrl can use it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-03-16 16:03:43 -06:00
Patrice Chotard
0c56310252 STiH410: Add STi pinctrl driver
Add STMicroelectronics STiH410 pinctrl driver

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-14 20:40:20 -04:00
Masahiro Yamada
6a6b9d5dfd pinctrl: uniphier: support pin configuration
Support the following DT properties:
  "bias-disable"
  "bias-pull-up"
  "bias-pull-down"
  "bias-pull-pin-default"
  "input-enable"
  "input-disable"

My main motivation is to support pull up/down biasing.  For Pro5 and
later SoCs, the pupdctrl register number is the same as the pinmux
number, so this feature can be supported without having big pin
tables.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Simon Glass
e160f7d430 dm: core: Replace of_offset with accessor
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-08 06:12:14 -07:00
Masahiro Yamada
7434bfa0e3 pinctrl: uniphier: support UniPhier PXs3 pinctrl driver
Add pin configuration and pinmux support for UniPhier PXs3 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-22 16:49:34 +09:00
Masahiro Yamada
2cfa35c47b pinctrl: uniphier: fix Ethernet (RMII) pin-mux setting for LD20
Fix the pin-mux values for the MDC, MDIO, MDIO_INTL, PHYRSTL pins.

Fixes: fc9da85c60 ("pinctrl: uniphier: add Ethernet pin-mux settings")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-18 01:24:14 +09:00
Patrick Bruenn
98d62e618b arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC
Add CX9020 board based on mx53loco.
Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse
serial_mxc with DTE and prepare for device tree migration of other
functions and imx53 devices.

The CX9020 differs from i.MX53 Quick Start Board by:
- use uart2 instead of uart1
- DVI-D connector instead of VGA
- no audio
- CCAT FPGA connected to emi
- enable rtc

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2016-12-16 12:57:12 +01:00
Peng Fan
ef0afaa083 pinctrl: imx6: support i.MX6SLL
There two iomuxc for i.MX6SLL. One is normal IOMUXC, the other
is for IOMUXC_SNVS.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-12-16 11:38:24 +01:00
Konstantin Porotchkin
656e6cc86b arm64: mvebu: pinctrl: Add pin control driver for A8K family
Add a DM port of Marvell pin control driver.
The A8K SoC family contains several silicone dies interconnected
in a single package. Every die is normally equipped with its own
pin controller unit.
There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-12-12 09:04:52 +01:00
Masahiro Yamada
6e67f176bb Fix codying style broken by recent libfdt sync
Commit b02e4044ff ("libfdt: Bring in upstream stringlist
functions") broke codying style in some places especially
by inserting an extra whitespace before fdt_stringlist_count().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-10-24 08:04:42 -04:00
Masahiro Yamada
935e09cdcb pinctrl: uniphier: fix unused-const-variable warnings for GCC 6.x
Marek reports warnings in UniPhier pinctrl drivers when compiled by
GCC 6.x, like:

  drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c:58:18: warning:
  'usb3_muxvals' defined but not used [-Wunused-const-variable=]
   static const int usb3_muxvals[] = {0, 0};
                    ^~~~~~~~~~~~

My intention here is to compile minimum set of pin data for SPL to
save memory footprint, but GCC these days is clever enough to notice
unused data arrays.

We can fix it by sprinkling around __maybe_unused on those arrays,
but I did not do that because they are counterparts of the pinctrl
drivers in Linux.  All the pin data were just copy-pasted from Linux
and are kept in sync for maintainability.

I chose a bit tricky way to fix the issue; calculate ARRAY_SIZE of
*_pins and *_muxvals and set their sum to an unused struct member.
This trick will satisfy GCC because the data arrays are used anyway,
but such data arrays will be dropped from the final binary because
the pointers to them are not used.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reported-by: Marek Vasut <marex@denx.de>
2016-10-18 14:06:46 +09:00
Simon Glass
df87e6b1b8 libfdt: Sync fdt_for_each_subnode() with upstream
The signature for this macro has changed. Bring in the upstream version and
adjust U-Boot's usages to suit.

Signed-off-by: Simon Glass <sjg@chromium.org>
Update to drivers/power/pmic/palmas.c:
Signed-off-by: Keerthy <j-keerthy@ti.com>

Change-Id: I6cc9021339bfe686f9df21d61a1095ca2b3776e8
2016-10-13 14:10:32 -06:00
Simon Glass
b02e4044ff libfdt: Bring in upstream stringlist functions
These have now landed upstream. The naming is different and in one case the
function signature has changed. Update the code to match.

This applies the following upstream commits by
Thierry Reding <treding@nvidia.com> :

   604e61e fdt: Add functions to retrieve strings
   8702bd1 fdt: Add a function to get the index of a string
   2218387 fdt: Add a function to count strings

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-10-13 13:54:10 -06:00
Stefan Agner
5a6f8d7b3b pinctrl: imx: do not announce driver initialization
It is not usual that drivers announce when they have been initialized.
use dev_dbg to announce device initialization.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-07 12:26:14 +02:00
Peng Fan
ca75159d8a pinctrl: imx6: support i.MX6ULL
There two iomuxc for i.MX6ULL. one iomuxc is compatible is i.MX6UL,
the other iomuxc is for SVNS usage, similar with the one in mx7.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2016-10-04 15:41:01 +02:00
Kever Yang
a2c08df381 pinctrl: add driver for rk3399
This patch add pinctrl driver for rk3399.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-09-22 07:32:22 -06:00
Masahiro Yamada
24572db909 pinctrl: uniphier: add UniPhier sLD3 pinctrl driver
Add pin-mux support for UniPhier sLD3 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:10:17 +09:00
Masahiro Yamada
bbb119800f pinctrl: uniphier: support 4bit-width pin-mux register capability
On LD4 SoC or later, the pin-mux registers are 8bit wide, while 4bit
wide on sLD3 SoC.  Support it for the sLD3 pinctrl driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:10:11 +09:00
Masahiro Yamada
cdc7e3cb32 pinctrl: uniphier: move register base macros from header to .c file
These macros are only referenced in pinctrl-uniphier-core.c, so
they need not reside in a header file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-14 22:54:19 +09:00
Masahiro Yamada
865a39a23f pinctrl: uniphier: add System Bus pin-mux settings
This is needed to get access to UniPhier System Bus (external bus).

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-14 22:54:19 +09:00
Beniamino Galvani
677b53580d pinctrl: add driver for meson-gxbb pin controller
Add a pin controller driver for Meson GXBB adapted from Linux kernel.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-09-06 13:18:19 -04:00
Beniamino Galvani
2c936374c8 pinctrl: generic: scan for "pins" and "groups" properties in sub-nodes
In cases where the pins and groups definitions are in a sub-node, as:

	uart_a {
		mux {
			groups = "uart_tx_a", "uart_rx_a";
			function = "uart_a";
		};
	};

pinctrl_generic_set_state_subnode() returns an error for the top-level
node and pinctrl_generic_set_state() fails. Instead, return success so
that the child nodes are tried.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-06 13:18:19 -04:00
Masahiro Yamada
f835706c29 pinctrl: fix typos in comment blocks of pinconfig_post_bind()
'-' is never used in function names.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-20 14:03:28 -04:00
Wenyou Yang
ac72e174f9 pinctrl: at91-pio4: Add pinctrl driver
AT91 PIO4 controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.

The pin configuration is performed on specific registers which
are shared along with the gpio controller. So regard the pinctrl
device as a child of atmel_pio4 device.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-08-15 22:58:03 +02:00
John Keeping
2b51784aef rockchip: rk3288: Fix pinctrl for GPIO bank 0
Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers
rather than the GRF registers.  In the GRF the top half of the register
is used as a mask so that some bits can be updated without affecting the
others, but in the PMU this feature is not provided and the top half of
the register is reserved.

Take the same approach as the Linux driver to update the value via
read-modify-write but setting the mask for only the bits that have
changed.  The PMU registers ignore the top 16 bits so this works for
both GRF and PMU iomux registers.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2016-07-31 07:24:20 -06:00
Simon Glass
911954859d dm: Use dm_scan_fdt_dev() directly where possible
Quite a few places have a bind() method which just calls dm_scan_fdt_dev().
We may as well call dm_scan_fdt_dev() directly. Update the code to do this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-27 14:15:54 -06:00
Simon Glass
2e3f1ff63f dm: Convert users from dm_scan_fdt_node() to dm_scan_fdt_dev()
This new function is more convenient for callers, and handles pre-relocation
situations automatically.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-27 14:15:07 -06:00
Heiko Stübner
041cdb5f3d cosmetic: rockchip: sort socs according to numbers
Having some sort of ordering proofed helpful in a lot of other places
already. So for a larger number of rockchip socs it might be helpful
as well instead of an ever increasing unsorted list.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:44:20 -06:00
Heiko Stübner
23c3042b10 cosmetic: rockchip: rk3036: pinctrl: fix config symbol naming
Rockchip socs are always named rkxxxx in all places, as also shown
by the naming of the rk3036 pinctrl file itself.
Therefore also name the config symbol according to this scheme.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:44:20 -06:00