3 commits

Author	SHA1	Message	Date
Ley Foon Tan	653f7c4467	cache: l2x0: Fix missing write to Auxiliary Control Register ... In commit f62782fb29 ("cache: l2x0: Fix write to incorrect shared-override bit") we removed writel to regs->pl310_aux_ctrl by accident. This commit restores it back. Fixes: f62782fb29 ("cache: l2x0: Fix write to incorrect shared-override bit") Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>	2020-05-06 15:12:48 -04:00
Ley Foon Tan	f62782fb29	cache: l2x0: Fix write to incorrect shared-override bit ... The existing code write bit-0 for shared attribute override enable bit. It should be bit-22 based on cache controller specification [1]. [1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246f/DDI0246F_l2c310_r3p2_trm.pdf Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>	2020-04-24 16:40:09 -04:00
Dinh Nguyen	88ebf5830f	dm: cache: add the pl310 cache controller driver ... Add a PL310 cache controller driver that is usually found on ARMv7(32-bit) devices. The driver configures the cache settings that can be found in the device tree files. This initial revision only configures basic settings(data & instruction prefetch, shared-override, data & tag latency). I believe these are the settings that affect performance the most. Comprehensive settings can be done by the OS. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>	2019-05-05 08:48:50 -04:00