The pinctrl supports to set any bit in input register on iMX6 if
the MSB of input value is 0xff. But the driver uses signed int for
input value, so when executing the codes below, it won't meet.
Because this is arithmetic right shift.
if (input_val >> 24 == 0xff)
Fix the issue by changing the input_val, config_val and mux_mode to u32.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The Serval SoC family has 32 pins. Currently there is no
support for Serval in Linux kernel.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The Servalt SoC family has 36 pins. Currently there is not support
for Servalt pinctrl in Linux kernel.
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
The Jaguar2 SOC family has 63 gpio pins therefore I extended mscc-common
to support new numbe of pins and remove any platform dependency from
mscc-common.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
This reverts commit a7f4b4b344.
As reported by Alex Kiernan the above optimization introduces a
regression in the below use case where:
1. Device has defined 'u-boot,dm-spl' property (@ eMMC DTS node)
2. The device downloads its MLO/SPL via UART (not eMMC - the eMMC pinmux
pins are NOT probed/configured in MLO/SPL).
3. The loaded via UART MLO/SPL wants to load Linux from eMMC. In this case
the DM core and pinctrl uclass checks 'u-boot,dm-spl' and don't
configure pins (as it thinks that those were initialized in MLO/SPL).
As we are very close to release - please revert this commit.
Reported-by: Alex Kiernan <alex.kiernan@gmail.com>
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Braces around the error-case for rk3399_pinctrl_set_pin_pupd lead to
an unconditional (and unintended) return from the function without it
ever setting pin-configurations.
Fix it.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds a Kconfig option to enable the full pinctrl driver
for the RK3399. This flag needs to be enabed in order to get the
features of the full pinctrl driver compiled in (i.e. a .set_state()
callback).
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The current pinctrl driver for the RK3399 has a range of qulity issues.
E.g. it only implements the .set_state_simple() callback, it
does not parse the available pinctrl information from the DTS
(instead uses hardcoded values), is not flexible enough to cover
devices without 'interrupt' field in the DTS (e.g. PWM),
is not written generic enough to make code reusable among other
rockchip SoCs...
This patch addresses these issues by reimplementing the whole driver
from scratch using the .set_state() callback.
The new implementation covers all featurese of the old code
(i.e. it supports pinmuxing and pullup/pulldown configuration).
This patch has been tested on a RK3399-Q7 SoM (Puma).
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
pinctrl_decode_pin_config_dm() is basically a feature-equivalent
implementation of pinctrl_decode_pin_config(), which operates
on struct udevice devices and uses the dev_read_*() API.
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit prevents from re-configuring pins if those were configured
before relocation.
Some pins - like UART or DDR must be setup before relocation
(as they have 'u-boot,dm-pre-reloc' property set in DTS). Without this
change, those pins are re-configured after relocation (pre_reloc_only = 0,
so we do not "continue").
Such behavior may be a problem for DDR PAD configuration, as they might
be already leveled/tuned with original setup).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This driver supports the pin and gpio controller found in the Ocelot and
Luton SoCs.
The driver was inspired from the pinctrl driver in Linux, but was
simplified and was modified to allow supporting an other SoCs (Luton).
For Ocelot and Luton the controller is the same, only the pins to program
differ.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
[changed to only descend into mscc/ dependent on CONFIG_PINCTRL_MSCC]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
- bad usage of clrsetbits_le32
- bad pin definition for AXG Family
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJcCkUAAAoJEHfc29rIyEnRqtAP/2BpLCNUqeZXzgaTueFbSp6z
JYPL45POLunaZrlTHVCrYTymcqr+AuS1cPjEIZI49RgVepDs6EWR/NcLWexiFKZ8
kdxSVP8FO6675sJ8KdYzGbgdBna5a2HPWZtYmX0OHGKgiPClL9HAkGrFWAwJtlHK
2zAQ+zRPt4TTwEgkmKK2/38Jz7rgkIpeXWoSuu9UEGmfkMhNFLGOPbzzNxHJTL3n
Ll7hLjLTBexgS6FQSHlNOj4XOnUubGTCchblCuMeVrEmUnvsgsXkzNMpRvfClzsZ
YsFgRHikTZG56QoUKErGu1XeJweF1DPQsYuxRQf4YJBjAiGHw0ASNgMy1cFmSfUp
rRCPDm4RHbSAvg/26iEU62FyFFLfrbtYuQJoxvp9iQbeamdXzFg/m8FyW4lNUeMU
xO42XobtsmEahsSlxPB9akIJEWOLNLXFt/HHCqHJZYGRu5wDK5ZysTp2E2sHCYF8
zttTi8WoPfiClmo8bLTIW/2SLylYILn48b9Gw6uZUq9B2uhsVeEro6Ya0d/fkFUd
IbtqGmcG/ejsh6R4V1BEHr96KEcpgXAzzWTW0IPGZIyQ4VHq+bOhL/YPm5eX2WVW
Wq/qMmhXuoJpZP/l/b3B4xRhQ5JWjWPtd8C2QBBTOX8uCSbmS0z+r6s0CTDzesD+
ODiWDH021RxK7WiJV4kN
=dvG1
-----END PGP SIGNATURE-----
Merge tag 'u-boot-amlogic-20181207' of git://git.denx.de/u-boot-amlogic
Two fixes for the Amlogic Pinctrl driver :
- bad usage of clrsetbits_le32
- bad pin definition for AXG Family
Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must
be updated.
stm32_pinctrl_get_gpio_dev() returns from a given pin selectors
the corresponding bank gpio device and the gpio_offset inside this
gpio bank.
Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Move gpio_dev list filling outside probe() to speed-up U-boot
boot sequence execution. This list is populated only when needed.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
The pin number (first and last) in the bank definition is missing the
pin base offset shifting. This is causing a miscalculation when
retrieving the register and pin offsets in the GPIO driver causing the
'gpio' command to drive the wrong pins / GPIOs in the second GPIO chip
(the AO bank is driven correctly because the shifting is already 0).
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Protect configuration registers with a hardware spinlock.
If a hwspinlock is defined in the device-tree node used it
to be sure that none of the others processors on the SoC could
change the configuration at the same time.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
The macros used to set the direction of the GPIO pins are misused,
resulting in a wrong behavior when trying to read the GPIO input level
from U-Boot.
A better macro is also used when setting the output direction.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This patch adds pinctrl support for MT7623 SoC. And most of the
structures are used to hold the hardware configuration for each
pin.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Tested-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds pinctrl support for MT7629 SoC. The IO core found on
the SoC has the registers for pinctrl, pinconf and gpio mixed up in
the same register range. Hence the driver also implements the gpio
functionality through UCLASS_GPIO.
This also creates a common file as there might be other chips that use
the same binding and driver, then being a little more abstract could
help in the long run.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds support for the Amlogic AXG SoC pinctrl and GPIO controller
using a specific set of pinctrl functions which differs from the GX SoCs.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Meson pinctrl needs generic pinctrl, rather than depending on it
select it
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
In preparation of supporting the new Amlogix AGX SoCs, we need to move
the Amlogic GX pinmux functions out of the common code to be able to
add a different set of SoC specific pinmux functions for AXG.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add get_pin_mux ops support to display the pin muxing
description of the sandbox_pins[]
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add get_pin_muxing() ops to obtain the pin muxing description
a given pin index.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add get_pin_name ops to obtain a pin name given a
pin index of a specified pin-controller.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add get_pins_count ops to obtain the number of pins
owns by a pin-controller.
On STM32 SoCs bindings, each pin-controller owns
several gpio banks. Each GPIO bank can own up to 16 pins.
To obtain the total pins count, walk through each sub-nodes
(ie GPIO banks) and sum each GPIO banks pins number. For that
in probe() we build a list with each GPIO device reference found.
This list will also be used with future get_pin_muxing and get_pin_name
ops to speed up and optimize walk through all GPIO banks.
As this code is common to all STM32 SoCs, this code is put
under SPL_BUILD compilation flag to avoid to increase SPL code size
for STM32F7 which is limited to 32Ko.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add pinctrl_get_pin_name() and pinctrl_get_pins_count() methods
to obtain pin's name and pin's muxing given a pin reference.
This will be used by the new pinmux command.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add get_pin_muxing() which allows to display the muxing
of a given pin belonging to a pin-controller.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.
To mitigate this potential impact, the following changes are
implemented:
- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
drivers that support both statically declared devices and
configuration from device tree
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add definition of the POCCTRL register and bits therein to R8A77990 E3
pincontrol driver. This allows the pincontrol driver to configure SDHI
pin voltage according to power-source DT property.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Use fixed 4bit size for generating the DRV register element mask,
not the size of the value, which can be smaller.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add pinctrl driver for i.MX8. The pads configuration is controlled
by SCU, so need to ask SCU to configure pads through scfw API.
Add pinctrl-scu to invoke sc_pad_set to configure pads.
Add a new flag IMX8_USE_SCU to differentiate i.MX8 from other platforms
which could directly configure pads from Acore side.
Add CONFIG_PINCTRL_IMX8 as the built gate.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Following build warning appears when pinctrl-single is built for ARM64:
In file included from drivers/pinctrl/pinctrl-single.c:10:0:
drivers/pinctrl/pinctrl-single.c: In function ‘single_configure_pins’:
./arch/arm/include/asm/io.h:43:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
#define __arch_getw(a) (*(volatile unsigned short *)(a))
Fix this by using phys_addr_t for variable reg instead of u32
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The sh_pfc_{read,write}() must operate on the register address directly
rather than on an offset, fix this to prevent illegal access.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This patch adds initial pinctrl driver to support for the R8A77990 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This follows the style of existion PORT_GP_X macros and
will be used by a follow-up patch for the r8a77990 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
When the pin control driver selects SD/eMMC function for
a pin group, there is additional configuration to be done
for this case - switch the PHY to work with SDHCI interface.
This patch adds the missing functionality into the pin
control driver.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Evan Wang <xswang@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
For pinctrl driver of mvebu, the compatible strings
supported are defined differently from Linux version.
The patch aligned the compatible string with
Linux 4.17-rc4.
Signed-off-by: Evan Wang <xswang@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Not all the udevice have a available DT node, eg. rksdmmc@ff500000.blk
which add by mmc_bind(), these device do not have/need set pinctrl
state.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The pinctrl bindings has changed for Amlogic Meson SoCs since Linux 4.13,
update the pinctrl driver to take this in account.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
