Commit graph

50791 commits

Author SHA1 Message Date
Kimmo Rautkoski
39b9e9bc72 sf: Add support for ISSI is25wp
Added support for is25wp032, is25wp064 and is25wp128.

Signed-off-by: Kimmo Rautkoski <ext-kimmo.rautkoski@vaisala.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-16 18:50:25 +05:30
Patrice Chotard
9938e068fa ARM: dts: stm32: Update qspi bindings for stm32f746
Align qspi bindings following kernel dt-bindings
Documentation/devicetree/bindings/mtd/stm32-quadspi.txt
from kernel v4.17-rc1.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-16 18:41:21 +05:30
Patrice Chotard
9582100eee ARM: dts: stm32: Add quadspi reset for stm32f746
Add missing reset property in quadspi node.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-16 18:41:21 +05:30
Patrice Chotard
5e46123bf3 spi: stm32_qspi: Add reset support
In some situation, QSPI controller is already configured by an early
boot stage, adding reset support will insure that QSPI controller is
started from a pristine state.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-16 18:41:21 +05:30
Patrice Chotard
2a6ca73691 spi: stm32_qspi: Use dev_read_xxx API
Use dev_read_xxx() instead of old manner fdt_xxx() API

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-16 18:41:21 +05:30
Christophe Kerello
495f3b2ae5 spi: stm32_qspi: Add chip select management
Quad-SPI interface is able to manage 2 spi nor devices.
FSEL bit selects the flash memory to be addressed in single flash mode.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-16 18:41:21 +05:30
Christophe Kerello
76afe56a44 spi: stm32_qspi: Add st, stm32f469-qspi compatible string
Add "st,stm32f469-qspi" compatible which is used on kernel side.
This will be necessary when DT will be synchronised from kernel.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-16 18:41:21 +05:30
Christophe Kerello
09e1772067 spi: stm32_qspi: Align reg-names with kernel 4.12 RC1
Align qspi bindings following kernel dt-bindings
Documentation/devicetree/bindings/mtd/stm32-quadspi.txt
from kernel v4.12-rc1.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-16 18:41:21 +05:30
Patrice Chotard
8c4592d278 spi: stm32_qspi: Sort include files alphabetically
Sort include files by alphabetical order

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-16 18:41:21 +05:30
Patrick Delaunay
936abadac8 spi: stm32_qspi: Solve issue detected by checkpatch
Fix parameters function alingemnt
Fix variable declaration

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-16 18:41:21 +05:30
Patrice Chotard
12e7c91a0b spi: stm32_qspi: Remove CONFIG_CLK flag
As all platforms which uses this driver have CONFIG_CLK flag
enable in their defconfig, we can remove it from driver code.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-16 18:41:21 +05:30
Kever Yang
f717b4c8e7 pinctrl: do not set_state for device without valid ofnode
Not all the udevice have a available DT node, eg. rksdmmc@ff500000.blk
which add by mmc_bind(), these device do not have/need set pinctrl
state.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-16 00:25:19 -06:00
Lothar Waßmann
409fc029c4 tools: buildman: Don't use the working dir as build dir
When the U-Boot base directory happens to have the same name as the branch
that buildman is directed to use via the '-b' option and no output
directory is specified with '-o', buildman happily starts removing the
whole U-Boot sources eventually only stopped with the error message:

OSError: [Errno 20] Not a directory: '../<branch-name>/boards.cfg

Add a check to avoid this and also deal with the case where '-o' points
to the source directory, or any subdirectory of it.

Finally, tidy up the confusing logic for removing the old tree when using
-b. This is only done when building a branch.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Lothar Waßmann <LW@KARO-electronics.de>
2018-05-16 00:25:19 -06:00
Jaehoon Chung
105e3d84e5 ARM: dts: exynos5: add the interrupt-parent property
Add the interrupt-parent property as gic.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2018-05-16 11:25:12 +09:00
Jaehoon Chung
631bacefb3 ARM: dts: exynos5: remove the duplicated nodes
Remove the duplicated gic and combiner nodes in exynos5.dtsi.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2018-05-16 11:25:12 +09:00
Bryan O'Donoghue
31dd8efeb6 usb: composite convert __set_bit to generic_set_bit
Compiling the f_mass_storage driver for an x86 target results in a
compilation error as set_bit and clear_bit are provided by bitops.h

To address that situation we discussed on the list moving to
genetic_set_bit() instead.

Doing a quick grep for similar situations in drivers/usb shows that the
composite device is using __set_bit().

This patch switches over to generic_set_bit to maintain consistency between
the two gadget drivers.

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marek Vasut <marex@denx.de>
2018-05-15 21:44:05 -04:00
Bryan O'Donoghue
5ac73f6879 usb: f_mass_storage: Fix set_bit and clear_bit usage
Compiling the f_mass_storage driver for an x86 target results in a
compilation error as set_bit and clear_bit are provided by bitops.h

Looking at the provenance of the current u-boot code and the git change
history in the kernel, it looks like we have a local copy of set_bit and
clear_bit as a hold-over from porting the Linux driver into u-boot.

These days __set_bit and __clear_bit are optionally provided by an arch and
can be used as inputs to generic_bit_set and generic_bit_clear.

This patch switches over to generic_set_bit and generic_clear_bit to
accommodate.

Tested on i.MX WaRP7 and Intel Edison

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marek Vasut <marex@denx.de>
2018-05-15 21:44:05 -04:00
Bryan O'Donoghue
73171c8d53 nds32: Define PLATFORM__CLEAR_BIT for generic_clear_bit()
nds2 bitops.h provides a __clear_bit() but does not define
PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the
architecturally provided __clear_bit().

This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in
nds32 bitops.h will be called whenever generic_clear_bit() is called - as
opposed to the default cross-platform generic_clear_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Macpaul Lin <macpaul@andestech.com>
2018-05-15 21:44:05 -04:00
Bryan O'Donoghue
76b916f233 nds32: Define PLATFORM__SET_BIT for generic_set_bit()
nds32 bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().

This patch defines PLATFORM__SET_BIT which means that __set_bit() in nds32
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Macpaul Lin <macpaul@andestech.com>
2018-05-15 21:44:05 -04:00
Bryan O'Donoghue
ff83066cc7 nios2: Define PLATFORM__CLEAR_BIT for generic_clear_bit()
nios2 bitops.h provides a __clear_bit() but does not define
PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the
architecturally provided __clear_bit().

This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in
nios2 bitops.h will be called whenever generic_clear_bit() is called - as
opposed to the default cross-platform generic_clear_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Thomas Chou <thomas@wytron.com.tw>
2018-05-15 21:44:05 -04:00
Bryan O'Donoghue
7ed4370bb9 nios2: Define PLATFORM__SET_BIT for generic_set_bit()
nios2 bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().

This patch defines PLATFORM__SET_BIT which means that __set_bit() in nios2
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Thomas Chou <thomas@wytron.com.tw>
2018-05-15 21:44:05 -04:00
Bryan O'Donoghue
accdce5f86 riscv: Define PLATFORM__CLEAR_BIT for generic_clear_bit()
riscv bitops.h provides a __clear_bit() but does not define
PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the
architecturally provided __clear_bit().

This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in
riscv bitops.h will be called whenever generic_clear_bit() is called - as
opposed to the default cross-platform generic_clear_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <green.hu@gmail.com>
2018-05-15 21:44:05 -04:00
Bryan O'Donoghue
820cba2ce8 riscv: Define PLATFORM__SET_BIT for generic_set_bit()
riscv bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().

This patch defines PLATFORM__SET_BIT which means that __set_bit() in x86
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <green.hu@gmail.com>
2018-05-15 21:44:05 -04:00
Bryan O'Donoghue
30fe8b05b3 x86: Define PLATFORM__SET_BIT for generic_set_bit()
x86 bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().

This patch defines PLATFORM__SET_BIT which means that __set_bit() in x86
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2018-05-15 21:44:05 -04:00
Chris Packham
0315d6959f ARM: mvebu: a38x: Add missing SPDX license identfier
mv_ddr_build_message.c is generated in Marvell's standalone mv_ddr code.
When imported into u-boot we need to add the appropriate SPDX tag and
re-format it slightly.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2018-05-15 09:08:00 -04:00
Tom Rini
c75990889d Merge branch 'master' of git://git.denx.de/u-boot-video 2018-05-15 08:29:24 -04:00
Vasily Khoruzhick
3ecec5aadd dts: sunxi: add PWM node for sun50i
Add PWM definition to sun50i-a64.dtsi

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2018-05-15 08:18:14 +02:00
Vasily Khoruzhick
1c353aea2b pwm: sunxi: add support for PWM found on Allwinner A64
This commit adds basic support for PWM found on Allwinner A64.
It can be used for pwm_backlight driver (e.g. for Pinebook)

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2018-05-15 08:18:09 +02:00
Vasily Khoruzhick
1005e4e5f6 video: dw_hdmi: fix HSYNC and VSYNC polarity settings
Currently dw_hdmi configures HSYNC polarity using VSYNC setting from
EDID and vice versa. Fix it, since it breaks displays where HSYNC
and VSYNC polarity differs

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
2018-05-15 08:03:42 +02:00
Vasily Khoruzhick
c7cb17e892 sunxi: video: HDMI: use correct bits for HSYNC and VSYNC polarity.
HSYNC is bit 8, and VSYNC is bit 9.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
2018-05-15 08:03:04 +02:00
Ramon Fried
b70fe965bb mmc: sdhci: Check that ops are defined
The check is necessary to avoid NULL pointer dereference.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2018-05-14 21:28:38 -04:00
Chris Packham
ed52ea507f net: add Kconfig for MVGBE
Add Kconfig for MVGBE and update boards to select this.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2018-05-14 21:28:38 -04:00
Chris Packham
edcf7eacbd net: mvgbe: remove CONFIG_DOVE
Nothing defines CONFIG_DOVE so remove the code that uses it.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-05-14 21:28:38 -04:00
Chris Packham
4b4dc5211e net: bootp: Fix compile error processing ntpserver option
When the following configuration is set

  # CONFIG_CMD_DHCP is not set
  CONFIG_CMD_BOOTP=y
  CONFIG_BOOTP_NTPSERVER=y

The following compile error is observed

  error: used struct type value where scalar is required
    if (net_ntp_server)
        ^~~~~~~~~~~~~~

Resolve this by checking net_ntp_server.s_addr instead.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-05-14 21:28:38 -04:00
Chris Packham
9b23c73d5e net: Add Kconfig option for BOOTP_NTPSERVER
Add a Kconfig option for BOOTP_NTPSERVER to enable the DHCP/BOOTP option
to configure the sntp server address.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-05-14 21:28:38 -04:00
Mario Six
a8ca5c8adb treewide: Move CONFIG_PHY_MARVELL to Kconfig
The CONFIG_PHY_MARVELL has already been migrated to Kconfig (some boards
already had it in their Kconfig), but had not been moved for older
boards.

Move it to the defconfigs for all boards.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-05-14 21:28:38 -04:00
Tom Rini
db6b0281ec Merge branch 'master' of git://git.denx.de/u-boot-rockchip 2018-05-14 18:13:59 -04:00
Jonathan Gray
ed1030e152 rockchip: clk: rk3288: handle clk_enable requests for GMAC
Since b0ba1e7e9d
(rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSIC)
Ethernet no longer probes on RK3288.

Add no-ops for GMAC clocks observed to be requested which match the
clk_enable cases in RK3368 and RK3399.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Cc: Wadim Egorov <w.egorov@phytec.de>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-05-14 17:30:40 +02:00
Jonathan Gray
b1959bd0b0 rockchip: set SYS_NS16550_MEM32 for all SoCs
Add back part of patch send out as
'rockchip: enable SYS_NS16550 for all SoCs by default' that seems to have
gotten lost when it got merged to set SYS_NS16550_MEM32.

Allows serial output to work on tinker-rk3288 again after
c3c0331db1.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-05-14 17:30:39 +02:00
Tom Rini
ca70cbabdc Merge git://git.denx.de/u-boot-marvell 2018-05-14 08:52:48 -04:00
Marek Behún
ca734a875d phy: marvell: a3700: Fix compatible string for ehci
The DTS file for armada-37xx uses the string "marvell,armada3700-ehci",
but the code searched for "marvell,armada-3700-ehci".

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14 10:01:56 +02:00
Chris Packham
db363dbce7 ARM: mvebu: a38x: use non-zero size for ddr scrubbing
Make ddr3_calc_mem_cs_size() global scope and use it in
ddr3_new_tip_ecc_scrub to correctly initialize all of DDR memory.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14 10:01:56 +02:00
Chris Packham
e6f61622d3 ARM: mvebu: a38x: restore support for setting timing
This restores support for configuring the timing mode based on the
ddr_topology. This was originally implemented in commit 90bcc3d38d
("driver/ddr: Add support for setting timing in hws_topology_map") but
was removed as part of the upstream sync.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14 10:01:56 +02:00
Chris Packham
2b4ffbf6b4 ARM: mvebu: a38x: sync ddr training code with upstream
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.

The upstream code is incorporated omitting the ddr4 and apn806 and
folding the nested a38x directory up one level. After that a
semi-automated step is used to drop unused features with unifdef

  find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
    xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
		-UCONFIG_APN806 -UCONFIG_MC_STATIC \
		-UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
		-UCONFIG_64BIT

INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE.

Some now empty files are removed and the ternary license is replaced
with a SPDX GPL-2.0+ identifier.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14 10:01:56 +02:00
Chris Packham
00a7767766 ARM: mvebu: a38x: remove some unused code
No in-tree code defines SUPPORT_STATIC_DUNIT_CONFIG or
STATIC_ALGO_SUPPORT. Remove ddr3_a38x_mc_static.h and use unifdef to
remove unused sections in the rest of the ddr/marvell/a38x code.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14 10:01:56 +02:00
Chris Packham
c4195d5553 ARM: mvebu: a38x: move sys_env_device_rev_get
Move sys_env_device_rev_get() from the ddr training code to
sys_env_lib.c (which currently resides with the serdes code). This
brings sys_env_device_rev_get() into line with sys_env_device_id_get()
and sys_env_model_get().

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14 10:01:56 +02:00
Chris Packham
e6fce12d14 ARM: mvebu: a38x: move definition of PEX_CFG_DIRECT_ACCESS
PEX_CFG_DIRECT_ACCESS was defined in ddr3_hws_hw_training_def.h despite
only being used in the serdes code. Move this definition to ctrl_pex.h
where all the other PEX defines are. Also remove the duplicate
definition of PEX_DEVICE_AND_VENDOR_ID which is already defined in
ctrl_pex.h.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14 10:01:56 +02:00
Marek Behún
80af1a9ef6 arm64: mvebu: Add basic support for the Turris Mox board
This adds basic support for the Turris Mox board from CZ.NIC, which is
currently being crowdfunded on Indiegogo.

Turris Mox is as modular router based on the Armada 3720 SOC (same as
EspressoBin).

The basic module can be extended by different modules. The device tree
binary for the kernel can be dependent on which modules are connected,
and in what order. Because of this, the board specific code creates
in U-Boot a variable called module_topology, which carries this
information.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14 10:00:15 +02:00
Marek Behún
2b69a67389 watchdog: Add support for Armada 37xx CPU watchdog
This adds support for the CPU watchdog found on Marvell Armada 37xx
SoCs.

There are 4 counters which can be set as CPU watchdog counters.
This driver uses the second counter (ID 1, counting from 0)
(Marvell's Linux also uses second counter by default).
In the future it could be adapted to use other counters, with
definition in the device tree.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14 10:00:15 +02:00
Marek Behún
cf2cf8510a net: mvneta: Fix fault when wrong device tree
The driver does not check id phy_connect failed (for example on wrong
property name in device tree). In such a case a fault occurs and the
CPU is restarted.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14 10:00:15 +02:00