Commit graph

7265 commits

Author SHA1 Message Date
Shinya Kuribayashi
36ede4d63e nios: Move README.nios_CONFIG_SYS_NIOS_CPU to doc/ dir
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2009-01-24 01:29:23 +01:00
Peter Korsgaard
c3284b030b common/main: support bootdelay=0 for CONFIG_AUTOBOOT_KEYED
Support bootdelay=0 in abortboot for the CONFIG_AUTOBOOT_KEYED case
similar to the CONFIG_ZERO_BOOTDELAY_CHECK support for the
!CONFIG_AUTOBOOT_KEYED case.

Do this by reversing the loop so we do at least one iteration before
checking for timeout.

Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
2009-01-24 01:24:15 +01:00
Niklaus Giger
94f9279f7b Added legacy flash ST Micro M29W040B 2009-01-24 01:22:22 +01:00
Graeme Russ
626d07348e Fixed off-by-one errors in lib_m68k/interrupts.c
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-01-24 01:19:23 +01:00
Graeme Russ
a5989c42ae Removed all references to CONFIG_SYS_RESET_GENERIC
Generic i386 reset - #define made redundant by weak function

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-01-24 01:15:33 +01:00
Graeme Russ
2b5360eb2b Remove #ifdef CONFIG_SC520 in source code
CONFIG_SC520 is now used for conditional compile

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-01-24 01:14:31 +01:00
Graeme Russ
ead056bc20 Added MMCR reset functionality
Reset function specific to AMD SC520 microcontroller - Is more of a
'hard reset' that the triple fault.

Requires CONFIG_SYS_RESET_SC520 to be defined in config

I would have liked to add this to a new file (cpu/i386/sc520/reset.c)
but ld requires that a object file in a library arhive MUST contain
at least one function which does not override a weak function (and is
called from outside the object file) in order for that object file to
be extracted from the archive. This would be the only function on the
new file, and hence, will never get linked in.

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-01-24 01:13:25 +01:00
Graeme Russ
3f5f18d12d Moved generic (triple fault) reset code
Moved from interrupts.c to cpu.c and made into a weak function to
allow vendor specific override

Vendor specific CPU reset (like the AMD SC520 MMCR reset) can now be
added to the vendor specific code without the need to remember to
#undef usage of the generic method and if you forget to include your
custom reset method, you will always get the default.

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-01-24 01:12:20 +01:00
Graeme Russ
9933d60902 Moved definition of set_vector() to new header file
This allows for future tidy ups and functionality that will require
set_vector ()

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-01-24 01:11:32 +01:00
Graeme Russ
407976185e Moved sc520 specific code into new cpu/i386/sc520 folder
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-01-24 01:10:20 +01:00
Graeme Russ
85ffbbd519 Renamed cpu/i386/reset.S to resetvec.S
Brings i386 in line with other CPUs with a reset vector and frees up reset.c
for CPU reset functions

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-01-24 01:06:25 +01:00
Wolfgang Denk
a3f4c123f5 Makefile: keep lists sorted.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-01-24 01:01:49 +01:00
Graeme Russ
c620c01e96 Added initial eNET board support
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-01-24 01:01:16 +01:00
Kim Phillips
833d94bcdc Merge branch 'next' 2009-01-23 17:48:24 -06:00
Gary Jennejohn
0c0ccf401e POWERPC 82xx: add the SCC as an HDLC controller
Right now this is only used by keymile.

Signed-off-by: Gary Jennejohn <garyj@denx.de>
2009-01-24 00:42:04 +01:00
Heiko Schocher
1e8f4e78ca powerpc, keymile boards: extract identical config options
This patch extracts the identical config options for the
keymile boards mgcoge, mgsuvd and kmeter1 in a new
common config file keymile-common.h.

Signed-off-by: Heiko Schocher <hs@denx.de>
2009-01-24 00:41:09 +01:00
Heiko Schocher
210c8c00aa powerpc: keymile: Add a check for the PIGGY debug board
Check the presence of the PIGGY on the keymile boards mgcoge,
mgsuvd and kmeter1. If the PIGGY is not present, dont register
this Ethernet device.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
2009-01-24 00:39:06 +01:00
Heiko Schocher
de0443614a powerpc: 83xx: add support for the kmeter1 board
This patch adds support for the kmeter1 board from Keymile,
based on a Freescale MPC8360 CPU.

- serial console on UART 1
- 256 MB DDR2 RAM
- 64 MB NOR Flash
- Ethernet RMII Mode over UCC4
- PHY SMSC LAN8700

Signed-off-by: Heiko Schocher <hs@denx.de>
2009-01-24 00:36:19 +01:00
Sergei Poselenov
3feb647f3f Add a do_div() wrapper macro, lldiv().
Add a do_div() wrapper, lldiv(). The new inline function doesn't modify
the dividend and returns the result of division, so it is useful
in complex expressions, i.e. "return(a/b)" -> "return(lldiv(a,b))"

Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2009-01-24 00:23:09 +01:00
Kumar Gala
18af1c5f0f 85xx: Add a 36-bit physical configuration for MPC8572DS
We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary
to allow for larger memory sizes.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-23 17:09:18 -06:00
Kumar Gala
c51fc5d53c 85xx: Handle eLBC difference w/36-bit physical
The eLBC only handles 32-bit physical address in systems with 36-bit
physical.  The previos generation of LBC handled 34-bit physical
address in 36-bit systems.  Added a new CONFIG option to convey
the difference between the LBC and eLBC.

Also added defines for XAM bits used in LBC for the extended 34-bit
support.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-23 17:08:28 -06:00
Kumar Gala
72a9414a8e 85xx: Use BR_ADDR macro for NAND chipselects
Use the new BR_ADDR macro to properly setup the address field of the
localbus chipselects used by NAND.

This allows us to deal with 36-bit phys on these boards in the future.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-23 17:08:28 -06:00
Haiying Wang
2fc7eb0cfc Add secondary CPUs processor frequency for e500 core
This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS,
and prints each CPU's frequency separately. It also fixes up each CPU's
frequency in "clock-frequency" of fdt blob.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2009-01-23 17:03:14 -06:00
Dave Liu
bf5b1f0c0d 85xx: enable the auto self refresh for wake up ARP
The wake up ARP feature need use the memory to process
wake up packet, we enable auto self refresh to support it.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:14 -06:00
Dave Liu
b4983e16d1 fsl-ddr: use the 1T timing as default configuration
For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:14 -06:00
Dave Liu
22cca7e1cd fsl-ddr: make the self refresh idle threshold configurable
Some 85xx processors have the advanced power management feature,
such as wake up ARP, that needs enable the automatic self refresh.

If the DDR controller pass the SR_IT (self refresh idle threshold)
idle cycles, it will automatically enter self refresh. However,
anytime one transaction is issued to the DDR controller, it will
reset the counter and exit self refresh state.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:14 -06:00
Dave Liu
22ff3d0134 fsl-ddr: clean up the ddr code for DDR3 controller
- The DDR3 controller is expanding the bits for timing config
- Add the DDR3 32-bit bus mode support

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:13 -06:00
Dave Liu
80ee3ce6d7 fsl-ddr: update the bit mask for DDR3 controller
According to the latest 8572 UM, the DDR3 controller
is expanding the bit mask, and we use the extend ACTTOPRE
mode when tRAS more than 19 MCLK.

Signed-off-by: Dave Liu <daveliu@freescale.com>
2009-01-23 17:03:13 -06:00
Kumar Gala
aca5f018a8 85xx: Introduce CONFIG_SYS_PCI*_IO_VIRT for FSL boards
Introduce a new define to seperate out the virtual address that PCI
IO space is at from the physical address.  In most situations these are
mapped 1:1.  However any code accessing the bus should use VIRT.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:13 -06:00
Kumar Gala
5af0fdd81c 85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards
Introduce a new define to seperate out the virtual address that PCI
memory is at from the physical address.  In most situations these are
mapped 1:1.  However any code accessing the bus should use VIRT.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:13 -06:00
Kumar Gala
a6e04c344a 85xx: Use CONFIG_SYS_{PCI*,RIO*}_MEM_PHYS for physical address on FSL boards
Use the _MEM_PHYS defines instead of _MEM_BUS for LAW and real address fields
of TLBs.  This is what we should have always been using from the start.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:13 -06:00
Kumar Gala
5f91ef6acd 85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boards
Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead
of _IO_BASE so we are more explicit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-23 17:03:13 -06:00
Kumar Gala
10795f42cb 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boards
Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead
of _MEM_BASE so we are more explicit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:13 -06:00
Kumar Gala
c953ddfd56 85xx: separate FLASH BASE virtual from physical address
Added a CONFIG_SYS_FLASH_BASE_PHYS for use as the physical address and
maintain CONFIG_SYS_FLASH_BASE as the virtual address of the flash.

This allows us to deal with 36-bit phys on these boards in the future.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:13 -06:00
Kumar Gala
52b565f5ad 85xx: separate PIXIS virtual from physical address
Added a PIXIS_BASE_PHYS for use as the physical address and maintain
PIXIS_BASE as the virtual address of the PIXIS fpga registers.

This allows us to deal with 36-bit phys on these boards in the future.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:13 -06:00
Haiying Wang
30837e5b21 Add README file for MPC8572DS board
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:12 -06:00
Mike Frysinger
6dadc9195a Blackfin: use common strmhz() in system output
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-23 22:59:16 +01:00
Wolfgang Denk
5df70e91c7 Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2009-01-23 22:48:06 +01:00
Wolfgang Denk
1ca1d3c866 Merge branch 'master' of git://git.denx.de/u-boot-microblaze 2009-01-23 22:47:25 +01:00
Ron Madrid
5bb907a492 mpc83xx: New board support for SIMPC8313
This patch will create a new board, SIMPC8313, from Sheldon Instruments.  This
board boots from NAND devices and is configureable for either large or small
page devices.  The board supports non-soldered DDR2, one ethernet port, a
Marvell 88E1118 PHY, and PCI host support.  The board also has a FPGA connected
to the eLBC providing glue logic to a TMS320C67xx DSP.

Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-23 11:31:18 -06:00
Mike Frysinger
d4bade8d77 nand: fixup printf modifiers to match types used
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-01-23 10:32:52 -06:00
Schlaegl Manfred jun
389e6620e2 nand read.jffs2 (nand_legacy) in common/cmd_nand.c
Error with CONFIG_NAND_LEGACY in common/cmd_nand.c:
With current code "nand read.jffs2s" (read and skip bad blocks) is always interpreted as
"nand read.jffs2" (read and fill bad blocks with 0xff). This is because ".jffs2" is
tested before ".jffs2s" and only the first two characters are compared.

Correction:
Test for ".jffs2s" first and compare the first 7 characters.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-01-23 10:32:52 -06:00
Wolfgang Grandegger
6c869637fe NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS
This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and
changes the default from 8 to 1 for the legacy and the new MTD
NAND layer. This allows to remove all NAND_MAX_CHIPS definitions
in the board config files because none of the boards use multi
chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440
define

 #define NAND_MAX_CHIPS          CONFIG_SYS_MAX_NAND_DEVICE

but that's bogus and did not work anyhow.

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-01-23 10:32:51 -06:00
Dave Liu
c70564e6b1 NAND: Fix cache and memory inconsistency issue
We load the secondary stage u-boot image from NAND to
system memory by nand_load, but we did not flush d-cache
to memory, nor invalidate i-cache before we jump to RAM.
When the system has cache enabled and the TLB/page attribute
of system memory is cacheable, it will cause issues.

- 83xx family is using the d-cache lock, so all of d-cache
  access is cache-inhibited. so you can't see the issue.
- 85xx family is using d-cache, i-cache enable, partial
  cache lock. you will see the issue.

This patch fixes the cache issue.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-01-23 10:32:50 -06:00
Nishanth Menon
50657c2732 NAND: Enable nand lock, unlock feature
Enable nand lock, unlock and status of lock feature.
Not every device and platform requires this, hence,
it is under define for CONFIG_CMD_NAND_LOCK_UNLOCK

Nand unlock and status operate on block boundary instead
of page boundary. Details in:
http://www.micron.com/products/partdetail?part=MT29C2G24MAKLAJG-6%20IT

Intial solution provided by Vikram Pandita <vikram.pandita@ti.com>
Includes preliminary suggestions from Scott Wood

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-01-23 10:32:49 -06:00
Mike Frysinger
69fb8be4fc NAND: move board_nand_init to nand.h
Rather than putting the function prototype for board_nand_init() in the one
place where it gets called, put it into nand.h so that every place that also
defines it gets the prototype.  Otherwise, errors can go silently unnoticed
such as using the wrong return value (void rather than int) when defining
the function.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-01-23 10:32:49 -06:00
Stefan Roese
1ae3986204 OneNAND: Additional sync with 2.6.27
- Add subpage write support
- Add onenand_oob_64/32 ecclayout

This has been missing and without it UBI has some incompatibilies issues
with the current (>= 2.6.27) Linux kernel version. vid_hdr_offset is
placed differently (2048 instead of 512) without this fix.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-01-23 10:32:48 -06:00
Kyungmin Park
1714f51a20 Add markbad function
Add missing markbad function
If not, it's hang when it entered the mtd->mark_bad().

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2009-01-23 10:32:47 -06:00
Stefan Roese
c438ea175d OneNAND: Bad block aware read/write command support
Update OneNAND command to support bad block awareness.
Also change the OneNAND command style to better match the
NAND version.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
2009-01-23 10:32:47 -06:00
Stefan Roese
8cf11f3aa7 OneNAND: Save version_id in onenand_chip struct
The version (ver_id) was not stored in the onenand_chip structure and
because of this the continuous locking scheme could be enabled on some
chips.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-01-23 10:32:46 -06:00