mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 15:37:23 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-microblaze
This commit is contained in:
Wolfgang Denk
commit
1ca1d3c866
12 changed files with 120 additions and 63 deletions
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@ -707,7 +707,7 @@ Yasushi Shoji <yashi@atmark-techno.com>
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Michal Simek <monstr@monstr.eu>
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ML401 MicroBlaze
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microblaze-generic MicroBlaze
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#########################################################################
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# Coldfire Systems: #
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6
MAKEALL
6
MAKEALL
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@ -697,9 +697,9 @@ LIST_nios2=" \
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## MicroBlaze Systems
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#########################################################################
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LIST_microblaze=" \
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ml401 \
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suzaku \
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LIST_microblaze=" \
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microblaze-generic \
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suzaku \
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"
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#########################################################################
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5
Makefile
5
Makefile
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@ -3170,10 +3170,9 @@ PCI5441_config : unconfig
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## Microblaze
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#========================================================================
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ml401_config: unconfig
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microblaze-generic_config: unconfig
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@mkdir -p $(obj)include
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@echo "#define CONFIG_ML401 1" > $(obj)include/config.h
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@$(MKCONFIG) -a $(@:_config=) microblaze microblaze ml401 xilinx
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@$(MKCONFIG) -a $(@:_config=) microblaze microblaze microblaze-generic xilinx
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suzaku_config: unconfig
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@mkdir -p $(obj)include
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@ -25,6 +25,8 @@
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* Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
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*/
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#define XILINX_BOARD_NAME microblaze-generic
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/* System Clock Frequency */
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#define XILINX_CLOCK_FREQ 100000000
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@ -25,8 +25,6 @@
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#include <common.h>
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#include <asm/asm.h>
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#if defined(CONFIG_CMD_CACHE)
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int dcache_status (void)
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{
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int i = 0;
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@ -62,4 +60,3 @@ void dcache_enable (void) {
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void dcache_disable(void) {
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MSRCLR(0x80);
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}
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#endif
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@ -25,32 +25,33 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include "../board/xilinx/ml401/xparameters.h"
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#include "../board/xilinx/microblaze-generic/xparameters.h"
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#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
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#define MICROBLAZE_V5 1
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#define CONFIG_ML401 1 /* ML401 Board */
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/* uart */
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#ifdef XILINX_UARTLITE_BASEADDR
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#define CONFIG_XILINX_UARTLITE
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#define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
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#define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
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#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
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#define CONFIG_XILINX_UARTLITE
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#define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
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#define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
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#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
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#define CONSOLE_ARG "console=console=ttyUL0,115200\0"
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#elif XILINX_UART16550_BASEADDR
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#define CONFIG_SYS_NS16550 1
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_COM1 (XILINX_UART16550_BASEADDR + 0x1000 + 0x3)
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#define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_NS16550 1
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_COM1 (XILINX_UART16550_BASEADDR + 0x1000 + 0x3)
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#define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ
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#define CONFIG_BAUDRATE 115200
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/* The following table includes the supported baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
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/* The following table includes the supported baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
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#define CONSOLE_ARG "console=console=ttyS0,115200\0"
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#else
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#error Undefined uart
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#error Undefined uart
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#endif
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/* setting reset address */
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@ -58,44 +59,44 @@
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/* ethernet */
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#ifdef XILINX_EMAC_BASEADDR
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#define CONFIG_XILINX_EMAC 1
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#define CONFIG_SYS_ENET
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#else
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#ifdef XILINX_EMACLITE_BASEADDR
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#define CONFIG_XILINX_EMACLITE 1
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#define CONFIG_SYS_ENET
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#endif
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#define CONFIG_XILINX_EMAC 1
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#define CONFIG_SYS_ENET
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#elif XILINX_EMACLITE_BASEADDR
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#define CONFIG_XILINX_EMACLITE 1
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#define CONFIG_SYS_ENET
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#elif XILINX_LLTEMAC_BASEADDR
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#define CONFIG_XILINX_LL_TEMAC 1
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#define CONFIG_SYS_ENET
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#endif
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#undef ET_DEBUG
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/* gpio */
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#ifdef XILINX_GPIO_BASEADDR
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#define CONFIG_SYS_GPIO_0 1
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#define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
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#define CONFIG_SYS_GPIO_0 1
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#define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
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#endif
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/* interrupt controller */
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#ifdef XILINX_INTC_BASEADDR
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#define CONFIG_SYS_INTC_0 1
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#define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
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#define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
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#define CONFIG_SYS_INTC_0 1
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#define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
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#define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
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#endif
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/* timer */
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#ifdef XILINX_TIMER_BASEADDR
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#if (XILINX_TIMER_IRQ != -1)
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#define CONFIG_SYS_TIMER_0 1
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#define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
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#define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
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#define FREQUENCE XILINX_CLOCK_FREQ
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#define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 )
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#endif
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#if (XILINX_TIMER_IRQ != -1)
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#define CONFIG_SYS_TIMER_0 1
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#define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
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#define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
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#define FREQUENCE XILINX_CLOCK_FREQ
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#define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 )
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#endif
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#elif XILINX_CLOCK_FREQ
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#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
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#else
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#ifdef XILINX_CLOCK_FREQ
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#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
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#else
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#error BAD CLOCK FREQ
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#endif
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#error BAD CLOCK FREQ
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#endif
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/* FSL */
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/* #define CONFIG_SYS_FSL_2 */
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@ -160,7 +161,7 @@
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* ?empty sector */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */
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#ifdef RAMENV
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@ -170,9 +171,9 @@
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#else /* !RAMENV */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
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#define CONFIG_ENV_SIZE 0x40000
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#define CONFIG_ENV_SIZE 0x20000
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#endif /* !RAMBOOT */
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#else /* !FLASH */
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/* ENV in RAM */
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@ -193,6 +194,18 @@
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#define CONFIG_DOS_PARTITION
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#endif
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#if defined(XILINX_USE_ICACHE)
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#define CONFIG_ICACHE
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#else
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#undef CONFIG_ICACHE
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#endif
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#if defined(XILINX_USE_DCACHE)
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#define CONFIG_DCACHE
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#else
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#undef CONFIG_DCACHE
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#endif
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/*
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* BOOTP options
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*/
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@ -207,9 +220,15 @@
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_MFSL
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#define CONFIG_CMD_ECHO
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#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
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#define CONFIG_CMD_CACHE
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#else
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#undef CONFIG_CMD_CACHE
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#endif
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#ifndef CONFIG_SYS_ENET
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#undef CONFIG_CMD_NET
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@ -233,7 +252,9 @@
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#define CONFIG_CMD_SAVES
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#endif
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#else
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_FLASH
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#undef CONFIG_CMD_JFFS2
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#endif
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#if defined(CONFIG_CMD_JFFS2)
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@ -253,11 +274,11 @@
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
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#define CONFIG_SYS_MAXARGS 15 /* max number of command args */
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_LOAD_ADDR 0x12000000 /* default load address */
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#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START /* default load address */
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#define CONFIG_BOOTDELAY 30
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#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
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#define CONFIG_BOOTARGS "root=romfs"
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#define CONFIG_HOSTNAME "ml401"
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#define CONFIG_HOSTNAME XILINX_BOARD_NAME
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#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
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#define CONFIG_IPADDR 192.168.0.3
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#define CONFIG_SERVERIP 192.168.0.5
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@ -268,7 +289,7 @@
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#define CONFIG_SYS_USR_EXCEP /* user exception */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo"
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#define CONFIG_PREBOOT "echo U-BOOT for $(hostname);setenv preboot;echo"
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#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\
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"nor0=ml401-0\0"\
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@ -111,6 +111,10 @@ void board_init (void)
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gd = (gd_t *) CONFIG_SYS_GBL_DATA_OFFSET;
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#if defined(CONFIG_CMD_FLASH)
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ulong flash_size = 0;
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#endif
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#if defined(CONFIG_CMD_NET)
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char *s, *e;
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int i;
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#endif
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asm ("nop"); /* FIXME gd is not initialize - wait */
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memset ((void *)gd, 0, CONFIG_SYS_GBL_DATA_SIZE);
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@ -132,11 +136,34 @@ void board_init (void)
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}
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}
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puts ("SDRAM :\n");
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printf ("\t\tIcache:%s\n", icache_status() ? "OK" : "FAIL");
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printf ("\t\tDcache:%s\n", dcache_status() ? "OK" : "FAIL");
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printf ("\tU-Boot Start:0x%08x\n", TEXT_BASE);
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#if defined(CONFIG_CMD_FLASH)
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puts ("FLASH: ");
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bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
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if (0 < (flash_size = flash_init ())) {
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bd->bi_flashsize = flash_size;
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bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + flash_size;
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# ifdef CONFIG_SYS_FLASH_CHECKSUM
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print_size (flash_size, "");
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/*
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* Compute and print flash CRC if flashchecksum is set to 'y'
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*
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* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
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*/
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s = getenv ("flashchecksum");
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if (s && (*s == 'y')) {
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printf (" CRC: %08X",
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crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size)
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);
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}
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putc ('\n');
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# else /* !CONFIG_SYS_FLASH_CHECKSUM */
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print_size (flash_size, "\n");
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# endif /* CONFIG_SYS_FLASH_CHECKSUM */
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} else {
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puts ("Flash init FAILED");
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bd->bi_flashstart = 0;
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@ -146,10 +173,9 @@ void board_init (void)
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#endif
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#if defined(CONFIG_CMD_NET)
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char *s, *e;
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int i;
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/* board MAC address */
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s = getenv ("ethaddr");
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printf ("MAC:%s\n",s);
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for (i = 0; i < 6; ++i) {
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bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
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if (s)
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@ -26,6 +26,18 @@
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void flush_cache (ulong addr, ulong size)
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{
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/* MicroBlaze have write thruough cache. nothing to do. */
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return;
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int i;
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for (i = 0; i < size; i += 4)
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asm volatile (
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#ifdef CONFIG_ICACHE
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"wic %0, r0;"
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#endif
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"nop;"
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#ifdef CONFIG_DCACHE
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"wdc %0, r0;"
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#endif
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"nop;"
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:
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: "r" (addr + i)
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: "memory");
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}
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