[backport from linux commit bedcf9d1dcf88ed38731f0ac9620e5a421e1e9d6]
Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the
name used in the RM is video_pll. So, let's rename "video_pll1" to
"video_pll" to be consistent with the RM and avoid misunderstandings.
No functional changes intended.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221219113127.528282-3-dario.binacchi@amarulasolutions.com
[backport from linux commit a429c60baefd95ab43a2ce7f25d5b2d7a2e431df]
The IMX8MN platform does not have any video processing unit (VPU), and
indeed in the reference manual (document IMX8MNRM Rev 2, 07/2022) there
is no occurrence of its pll. From an analysis of the code and the RM
itself, I think vpu pll is used instead of m7 alternate pll, probably
for copy and paste of code taken from modules of similar architectures.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221219113127.528282-2-dario.binacchi@amarulasolutions.com
This converts 7 usages of this option to the non-SPL form, since there is
no SPL_CMD_CLK defined in Kconfig
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
The QSPI clocks are only used when CONFIG_NXP_FSPI=y, so only build the
QSPI clocks in this case to reduce the final SPL binary size.
Signed-off-by: Fabio Estevam <festevam@denx.de>
The ecspi clocks are only used when CONFIG_DM_SPI=y, so only build the
ecspi clocks in this case to reduce the final SPL binary size.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Ethernet is not used inside SPL, so move the IMX8MM_CLK_ENET_AXI clock
inside the non-SPL block to reduce the final SPL binary size.
Signed-off-by: Fabio Estevam <festevam@denx.de>
PWM is not used inside SPL, so do not define the PWM clocks inside
SPL to reduce the final SPL binary size.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Add gpmi nand clock. Those clock can be used in mxs nand driver
to run nand to EDO mode 5, 4, ...
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Add shared counter in order to avoid to swich off clock that
are already used.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
The i.MXRT11 series has two new pll types but are variants of existing.
This patch adds the ability to read one of the pll types' frequency
as it can't be changed unlike the generic pll it also has the
division factors swapped.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Upstream commit 7a2c3be95a ("clk: imx8mp: Fill in DWC3 USB, USB PHY,
HSIOMIX clock") added usb_core_ref for USB Controller but never set it
to be used as a clock source, using rather "osc_32k" instead.
This produces following boot log message:
"clk_register: failed to get osc_32k device (parent of usb_root_clk)"
Fix the USB controller clock source by using usb_core_ref instead of
osc_32k.
Fixes: 7a2c3be95a ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock")
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Root clock name contained underscore, which does not match to the actual
clock name.
Correct the name to match what is present in the FDT.
Fixes: 87f958810f ("clk: imx8mp: Add ECSPI clocks")
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Fix registration of 24M and 32k clock, those got applied or rebased
incorrectly, so fill in the correct code.
Fixes: 7a2c3be95a ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
In Linux IMX and IMXRT use the device tree to hold the anatop address.
The anatop is used in clock drivers as it controls the internal PLLs
This will move the macro from asm/arch-imxrt to the device tree.
This presumably should also be done with the other IMX boards as well.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Add clock tables required to bring up DWC3 USB, USB PHY and HSIOMIX domain.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Re-factor the imx8m[nmpq] rate tables into the common pll1416x clock
driver.
43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure to common place")
Signed-off-by: Angus Ainslie <angus@akkea.ca>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mm-beacon
This is a DM clock driver based off the imx8mm u-boot driver and the linux
kernel driver.
All of the PLLs and clocks are initialized so the subsystems below are
functional and tested.
1) USB host and peripheral
2) ECSPI
3) UART
4) I2C all busses
5) USDHC for eMMC support
6) USB storage
7) GPIO
8) DRAM
Signed-off-by: Angus Ainslie <angus@akkea.ca>
Acked-by: Sean Anderson <seanga2@gmail.com>
This converts most CCF drivers to use generic ops. imx6q is the only
outlier, where we retain the existing functionality by moving the check to
request().
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com
[ fixed missing include for at91 ]
Signed-off-by: Sean Anderson <seanga2@gmail.com>
The clock composite is required when using the clock framework. So
select it automatically.
Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Usb needs IMXRT1050_CLK_USBOH3 clock to be enabled, so let's add it to
clock driver.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Lcd peripheral needs 2 different gates to be enable to work, so let's
introduce the missing one(LCDIF_PIX) and rename the existing one
(LCDIF_APB).
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
At present some drivers use -ENOSUPP to indicate that an unknown or
unsupported clock is used. Most use -EINVAL, indicating an invalid value,
so convert everything to that.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Add ECSPI clock entries to iMX8MN clock driver. Only make those entries
available in case SPI support in U-Boot is enabled at all to conserve
space, esp. in SPL.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Driver model: Rename U_BOOT_DEVICE et al.
dtoc: Tidy up and add more tests
ns16550 code clean-up
x86 and sandbox minor fixes for of-platdata
dtoc prepration for adding build-time instantiation
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Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into next
Driver model: make some udevice fields private
Driver model: Rename U_BOOT_DEVICE et al.
dtoc: Tidy up and add more tests
ns16550 code clean-up
x86 and sandbox minor fixes for of-platdata
dtoc prepration for adding build-time instantiation
In the spirit of using the same base name for all of these related macros,
rename this to have the operation at the end. This is not widely used so
the impact is fairly small.
Signed-off-by: Simon Glass <sjg@chromium.org>
This patch fixes this clk issue on I2C on imx8qm
=> i2c bus
Bus 3: i2c@5a830000
=> i2c dev 3
Setting bus to 3
Failed to enable ipg clk
Failure changing bus number (-524)
Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
After commit 673f659732 ("net: fec_mxc: support i.MX8M with CLK_CCF") all
NXP boards, which are not IMX8 and in the same time are supporting CCF need
to provide PTP clock.
On the i.MX6Q this clock is provided with IMX6QDL_CLK_ENET_REF in the Linux
kernel's CCF.
Code in this change models the simplest case when enet reference clock is
generated from 'osc' clock.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This code has been ported from Linux kernel v5.5.5 (tag) and has been
adjusted to U-Boot's DM.
It adds support for correct recognition of IMX_PLLV3_ENET flag in the
clk-pllv3.c driver.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
After commit 673f659732 ("net: fec_mxc: support i.MX8M with CLK_CCF") all
NXP boards, which are not IMX8 and in the same time are supporting CCF
need to provide IMX6QDL_CLK_ENET.
This change defines the missing clock in i.MX6Q's CCF.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
We use non-dm code to configure the clk settings in order to simplify
dm clk driver in future, so remove the duplicated code from clk driver
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add clocks for FEC and flexspi, and add set parent clock callback,
so DTS can assign clocks
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add USB relevant clocks to support usb clock settings for both
DM USB host and gadget drivers
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add set clock parent support.
Add ENET and flexspi related clocks to support assigned clocks
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
dev_read_addr_ptr had different semantics depending on whether OF_LIVE was
enabled. This patch converts both implementations to return NULL on error,
and converts all call sites which check for FDT_ADDR_T_NONE to check for
NULL instead. This patch also removes the call to map_physmem, since we
have dev_remap_addr* for those semantics.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
CCF clocks should always use the struct clock passed to their methods for
extracting the driver-specific clock information struct. Previously, many
functions would use the clk->dev->priv if the device was bound. This could
cause problems with composite clocks. The individual clocks in a composite
clock did not have the ->dev field filled in. This was fine, because the
device-specific clock information would be used. However, since there was
no ->dev, there was no way to get the parent clock. This caused the
recalc_rate method of the CCF divider clock to fail. One option would be to
use the clk->priv field to get the composite clock and from there get the
appropriate parent device. However, this would tie the implementation to
the composite clock. In general, different devices should not rely on the
contents of ->priv from another device.
The simple solution to this problem is to just always use the supplied
struct clock. The composite clock now fills in the ->dev pointer of its
child clocks. This allows child clocks to make calls like clk_get_parent()
without issue.
imx avoided the above problem by using a custom get_rate function with
composite clocks.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
LCDIF clock gate was wrong so set it according to RM.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Need to add set_parent() callback to allow dts assigned-clock-parents to
work so let's add it accordingly.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
