Commit graph

264 commits

Author SHA1 Message Date
Bin Meng
a187559e3d Use correct spelling of "U-Boot"
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-02-06 12:00:59 +01:00
Purna Chandra Mandal
7d514a7407 board: Enable ethernet, tftpboot support to pic32mzdask board.
This adds ethernet, TFTP support for PIC32MZ[DA] Starter Kit. Also
custom environment variables/scripts are added to help boot from network.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
2016-02-01 22:14:02 +01:00
Purna Chandra Mandal
c76eb72c43 board: add SDHCI support for PIC32MZDASK board.
Enable MMC, SDHCI, FAT_FS support for PIC32MZ[DA] StarterKit.
Also add custom scripts, rules to boot Linux from microSD card.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
2016-02-01 22:14:02 +01:00
Purna Chandra Mandal
44da3a176c board: Add Microchip PIC32MZ[DA]-Starter-Kit board.
This adds support for Microchip PIC32MZ[DA] StarterKit board
based on a PIC32MZ[DA] family of microcontroller.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01 22:14:01 +01:00
Purna Chandra Mandal
be961fa15b MIPS: Add support for Microchip PIC32MZ[DA] SoC family.
Add Microchip PIC32MZ[DA] SoC family support.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01 22:14:01 +01:00
Purna Chandra Mandal
9ffa7a35ef drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.
This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).

Signed-off-by: Paul Thacker <paul.thacker@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-01 22:14:01 +01:00
Purna Chandra Mandal
32c1a6eef8 MIPS: initial infrastructure for Microchip PIC32 architecture
Create initial directory, Kconfigs needed for PIC32 architecture
support. Also add PIC32 specific register definition required for drivers.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-02-01 22:14:00 +01:00
Paul Burton
05e342554e MIPS: Support dynamic I/O port base address
The existing mips_io_port_base variable isn't suitable for use early
during boot since it will be stored in the .data section which may not
be writable pre-relocation. Fix this by moving the I/O port base address
into struct arch_global_data. In order to avoid adding this field for
all targets, make this dependant upon a new Kconfig entry
CONFIG_DYNAMIC_IO_PORT_BASE. Malta is the only board which sets a
non-zero I/O port base, so select this option only for Malta.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-02-01 22:13:25 +01:00
Paul Burton
8ac493cd65 MIPS: Remove SLOW_DOWN_IO
CONF_SLOWDOWN_IO is never set for any target, so remove the dead code in
the SLOW_DOWN_IO macro. This is done in preparation for changes to
mips_io_port_base which can be avoided in this path by removing it
entirely.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-02-01 22:13:25 +01:00
Marek Vasut
fbb0de088b mips: cache: Bulletproof the code against cornercases
This patch makes sure that the flush/invalidate_dcache_range() functions
can handle corner-case calls like this -- invalidate_dcache_range(0, 0, 0);
This call is valid and is happily produced by USB EHCI code for example.
The expected behavior of the cache function(s) in this case is that they
will do no operation, since the size is zero.

The current implementation though has a problem where such invocation will
result in a hard CPU hang. This is because under such conditions, where the
start_addr = 0 and stop = 0, the addr = 0 and aend = 0xffffffe0 . The loop
will then try to iterate over the entire address space, which in itself is
wrong. But iterating over the entire address space might also hit some odd
address which will cause bus hang. The later happens on the Atheros MIPS.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Hans de Goede <hdegoede@redhat.com>
2016-02-01 22:13:24 +01:00
Daniel Schwierzeck
e26e8dc8f4 MIPS: start.S: fix and optimize instructions
Fix 32 vs 64 bit load/store instructions. Access CP0_WATCHHI as
32 Bit register. Use 64 Bit register access for clearing gd_data
and copying U-Boot.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01 22:13:24 +01:00
Purna Chandra Mandal
a62790997f MIPS: initialize board_init_f() argument to zero.
Argument boot_flags of board_init_f() should be set to 0 as
$a0 may be utilized in lowlevel_init() or mips_cache_reset()
or previous stage boot-loader.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01 22:13:24 +01:00
Tom Rini
d6ea6d8876 mips: asm/io.h: Add in <linux/bug.h>
As part of the bug.h / BUILD_BUG_* clean up, this file was missed.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-25 18:52:23 -05:00
Daniel Schwierzeck
0e0efb40b8 MIPS: implement bit manipulating I/O accessors
Add support for functions clrbits_X(), setbits_X() and clrsetbits_X()
on MIPS.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
898582bdee MIPS: fix SPDX license identifier in remaining arch header files
Add a SPDX license identifier to MIPS header files where it is
still missing.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
a3ab2ae7f6 MIPS: sync processor and register definitions with linux-4.4
Update definitions for processor, registers as well as assemby
macros.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
23ff8633fd MIPS: sync I/O related header files with linux-4.4
Mainly sync asm/io.h to get a working ioremap() implementation
as well as the full set of I/O accessors. Pull in additional
header files to make this work.

Furthermore port over the directory 'arch/mips/include/asm/mach-generic/'
with contains default definitions for I/O and memory spaces and default
implementations for mapping those spaces. All files in that directory
can be overwritten by a SoC/machine.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
f53830e74e MIPS: kconfig: add option for MIPS_L1_CACHE_SHIFT
Add Kconfig symbol for L1 cache shift like the kernel does.
The value of CONFIG_SYS_CACHELINE_SIZE is not a reliable source
for ARCH_DMA_MINALIGN anymore, because it is optional on MIPS.
If CONFIG_SYS_CACHELINE_SIZE is not defined by a board, the
cache sizes are automatically detected and ARCH_DMA_MINALIGN
would be set to 128 Bytes.

The default value for CONFIG_MIPS_L1_CACHE_SHIFT is 5 which
corresponds to 32 Bytes. All current MIPS boards already used
that value. While on it, fix the Malta board to use a value of 6
like the kernel port does.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
0315a28909 MIPS: Kconfig: optimize gcc -march and -mtune setup
Move setup of -march to arch/mips/Makefile and follow the design on ARM.
Also add a possibility to chose specific CPU tune options.

Signed-off-by: Wills Wang <wills.wang@live.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
76ada5f8b7 MIPS: au1x00: move SoC header files to arch/mips/mach-au1x00/include/mach/
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
6479b691d7 MIPS: Kconfig: refactor machine setup
Refactor machine setup like it is done on ARM. While on it,
also support "include <mach/file.h" for machine specific
header files.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
0fc13a9093 MIPS: add initial infrastructure for device-tree files
Prepare sub-folder for device-tree files. Make support for
device-tree on MIPS available in Kbuild/Kconfig.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
2016-01-16 21:06:45 +01:00
Daniel Schwierzeck
e92d9124f8 MIPS: do not build position-independent executables for SPL
SPL binaries are usually linked to a fixed address in SRAM.
Furthermore SPL binaries do not need to relocate itself. Thus
do not build them as position-independent binaries which helps
to largely reduce the size of SPL binaries.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:45 +01:00
Daniel Schwierzeck
5b6f357fe7 MIPS: create .text sub-sections for assembler functions
Put all functions coded in assembly in sub-sections of
section .text. This allows the linker to garbage collect
unused assembly functions too.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:45 +01:00
Daniel Schwierzeck
113492988b MIPS: fix annotation of _start and relocate_code
Correctly annotate _start and relocate_code as functions to
produce more readable disassembly code generated by objdump.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:45 +01:00
Purna Chandra Mandal
1a96780016 MIPS: add asm/gpio.h to fix compilation error with CONFIG_CMD_GPIO.
With CONFIG_CMD_GPIO compilation reports error.
common/cmd_gpio.c:13:22: fatal error: asm/gpio.h: No such file or directory
 #include <asm/gpio.h>
                      ^
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-16 21:06:45 +01:00
Ben Whitten
192bc6948b Fix GCC format-security errors and convert sprintfs.
With format-security errors turned on, GCC picks up the use of sprintf with
a format parameter not being a string literal.

Simple uses of sprintf are also converted to use strcpy.

Signed-off-by: Ben Whitten <ben.whitten@gmail.com>
Acked-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14 22:11:34 -05:00
Tom Rini
250ea267d8 Merge branch 'master' of git://git.denx.de/u-boot-mips 2015-11-06 09:17:17 -05:00
Daniel Schwierzeck
347ea94e2a MIPS: bootm: use CONFIG_IS_ENABLED() everywhere
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-11-06 13:27:28 +01:00
Daniel Schwierzeck
2bb5b63879 MIPS: bootm: rework and fix broken bootm code
The move to 'generic board' as well as changes in the generic
bootm code broke the boot of FIT uImage's. Especially uImage's
with additional initramfs images or FDT's do not work anymore.

Refactor the bootm code to work again with the generic bootm code.

Always relocate ramdisk and FDT in step 'bootm prep' because the
generic bootm code does this only for legacy uImage's.

Move the step 'bootm cmdline' to 'bootm prep' because the Linux
kernel parameters rd_start and rd_size have to be initialized after
the relocation of the ramdisk.

Furthermore support the step 'bootm fake'.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-06 13:27:28 +01:00
Fabio Estevam
b810aa1dd1 mips: Use the generic bitops headers
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-11-05 10:52:26 -05:00
Govindraj Raja
4adcb2380c MIPS: fix syntax for fdt_chosen/initrd.
The syntax for the fdt_chosen/initrd
functions seem to deprecated in usage
from MIPS bootm implementation.

Third parameter is no more used in these api's
Refer to : include/fdt_support.h

Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
2015-08-21 15:22:41 +02:00
Chris Packham
73a4152b25 mips: Use unsigned int when reading c0 registers
In commit a18a477 (MIPS: use common code from lib/time.c) MIPS platforms
started using common the common timer functions which are based around
the fact that many platforms have a 32-bit free running counter register
that can be used see commit 8dfafdd (Introduce common timer functions).

Even MIPS64 has such a 32-bit register (some have an additional 64-bit free
running counter, but that's something for another time).

The problem is that in __read_32bit_c0_register() we read the value from
this register into an _signed_ int and as it's returned up the call
chain to timer_read_counter() it gets assigned to an unsigned long. On a
32-bit system there is no problem. On a 64-bit system odd things happen,
sign extension seems to kick in and all of a sudden if the counter
register happens to have the MSb (i.e. the sign bit) set the negative
int gets sign extended into a very large unsigned long value. This in
turn throws out things from get_ticks() up.

Update __read_32bit_c0_register() and __read_32bit_c0_ctrl_register() to
use "unsigned int res;" instead of "int res;". There seems to be little
reason to treat these register values as signed. They are either
counters (which by definition are unsigned) or are made up of various
bit fields to be interpreted as per the CPU datasheet.

Reported-by: Sachin Surendran <sachin.surendran@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
2015-08-21 15:22:41 +02:00
Daniel Schwierzeck
b11c5d1dc2 MIPS: change 'extern inline' to 'static inline'
The kernel changed it a long time ago. Also this is now broken
on gcc-5.x.

Reported-by: Andy Kennedy <andy.kennedy@adtran.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-07-02 11:29:33 +02:00
Tony Wu
49bbdae318 MIPS: fix missing semicolon in cacheops.h
Fix missing semicolon in cacheops.h introduced in commit
2b8bcc5a2 (MIPS: avoid .set ISA for cache operations)

Signed-off-by: Tony Wu <tung7970@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
2015-07-02 11:29:33 +02:00
Joe Hershberger
c9bb942e2f Move default y configs out of arch/board Kconfig
Some archs/boards specify their own default by pre-defining the config
which causes the Kconfig system to mix up the order of the configs in
the defconfigs... This will cause merge pain if allowed to proliferate.

Remove the configs that behave this way from the archs.

A few configs still remain, but that is because they only exist as
defaults and do not have a proper Kconfig entry. Those appear to be:

SPIFLASH
DISPLAY_BOARDINFO

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
[trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates,
drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM]
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-06-25 22:17:55 -04:00
Joe Hershberger
a26cd04920 arch: Make board selection choices optional
By making the board selections optional, every defconfig will include
the board selection when running savedefconfig so if a new board is
added to the top of the list of choices the former top's defconfig will
still be correct.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Rini <trini@konsulko.com>
2015-05-12 18:10:02 -04:00
Daniel Schwierzeck
90b1c9fad7 MIPS: implement device-tree handover to Linux kernel
Add device-tree handover to Linux kernel conforming with MIPS UHI [1].
Register $a0 will be set to the reserved value -2. The address of
the device-tree blob will be stored as KSEG0 address in $a1. $a2 and
$a3 are set to zero.

[1] http://prplfoundation.org/wiki/MIPS_documentation

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-04-24 12:15:34 +02:00
Joe Hershberger
1fd92db83d net: cosmetic: Fix var naming net <-> eth drivers
Update the naming convention used in the network stack functions and
variables that Ethernet drivers use to interact with it.

This cleans up the temporary hacks that were added to this interface
along with the DM support.

This patch has a few remaining checkpatch.pl failures that would be out
of the scope of this patch to fix (drivers that are in gross violation
of checkpatch.pl).

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:33 -06:00
Joe Hershberger
8b2c9a7157 net: Provide a function to get the current MAC address
The current implementation exposes the eth_device struct to code that
needs to access the MAC address.  Add a wrapper function for this to
abstract away the pointer for this operation.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:10 -06:00
Masahiro Yamada
0a12e6872e generic-board: move __HAVE_ARCH_GENERIC_BOARD to Kconfig
Move the option to Kconfig renaming it to CONFIG_HAVE_GENERIC_BOARD.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-03-28 09:03:08 -04:00
Daniel Schwierzeck
eef88dfb3e MIPS: unify CPU code in arch/mips/cpu/
Unify and move code in arch/mips/cpu/mips[32|64]/ to arch/mips/cpu/.
The CPU specific config.mk files need to remain until
CONFIG_STANDALONE_LOAD_ADDR is converted to a global Kconfig symbol.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-30 14:19:58 +01:00
Daniel Schwierzeck
d9a4a6223c MIPS: move au1x00 SoC code to arch/mips/mach-au1x00
Move all au1x00 code out of arch/mips/cpu/mips32 to allow
unification of CPU code in a later patch. The reorganization
of the SoC specific header files will be done in a later patch
series.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
2015-01-30 14:19:58 +01:00
Paul Burton
f1c64a0810 MIPS: handle mips64 ST0_KX bit in mips32 start.S
In preparation for sharing a single copy of start.S between mips32 &
mips64, handle setting the KX bit of the cop0 Status register when the
mips32 start.S is built for mips64.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-30 14:19:58 +01:00
Paul Burton
ab0d002677 MIPS: handle mips64 relocs in mips32 start.S
In preparation for sharing a single copy of start.S between mips32 &
mips64, handle mips64 relocations in the mips32 start.S when built for
mips64.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-30 14:19:58 +01:00
Paul Burton
a39b1cb7f0 MIPS: use asm.h macros in mips32 start.S
Where the mips32 & mips64 implementations of start.S differ in terms of
access sizes & offsets, use the appropriate macros from asm.h to
abstract those differences away. This is in preparation for sharing a
single copy of start.S between mips32 & mips64.

The exception to this is loads of immediates to be written to the cop0
Config register, which is a 32bit register on mips64 and therefore
constants written to it can be loaded as such.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-30 14:19:57 +01:00
Paul Burton
ba21a453a5 malta: IDE support
This patch adds IDE support to the MIPS Malta board. The IDE controller
is enabled after probing the PCI bus and otherwise just makes use of
U-boot generic IDE support.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 13:11:02 +01:00
Paul Burton
8755d50706 MIPS: clear TagLo select 2 during cache init
Current MIPS cores from Imagination Technologies use TagLo select 2 for
the data cache. The architecture requires that it is safe for software
to write to this register even if it isn't present, so take the trivial
option of clearing both selects 0 & 2.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 12:55:01 +01:00
Paul Burton
dd7c72006e MIPS: allow systems to skip loads during cache init
Current MIPS systems do not require that loads be performed to force the
parity of cache lines, a simple invalidate by clearing the tag for each
line will suffice. Thus this patch makes the loads & subsequent second
invalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
option, and defines that for existing mips32 targets. Exceptions are
malta where this is known to be unnecessary, and qemu-mips where caches
are not implemented.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 12:55:01 +01:00
Paul Burton
ca4e833cd6 MIPS: inline mips_init_[id]cache functions
The mips_init_[id]cache functions are small & only called once from a
single callsite. Inlining them allows mips_cache_reset to avoid having
to bother moving arguments around & leaves it a leaf function which is
thus able to simply keep the return address live in the ra register
throughout, simplifying the code.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 12:55:01 +01:00