Commit graph

7 commits

Author SHA1 Message Date
Tom Rini
ac727577f0 Revert "drivers/ddr/fsl: Dual-license DDR driver"
Upon further review, not all code authors are in favour of this change.
This reverts commit ee3556bcaf.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-02-14 21:34:05 -05:00
York Sun
ee3556bcaf drivers/ddr/fsl: Dual-license DDR driver
To make this driver easier to be reused, dual-license DDR driver.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Simon Glass <sjg@chromium.org>
CC: Tom Rini <trini@konsulko.com>
CC: Heinrich Schuchardt <xypron.glpk@gmx.de>
CC: Thomas Schaefer <thomas.schaefer@kontron.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Robert P. J. Day <rpjday@crashcourse.ca>
CC: Alexander Merkle <alexander.merkle@lauterbach.com>
CC: Joakim Tjernlund <joakim.tjernlund@transmode.se>
CC: Curt Brune <curt@cumulusnetworks.com>
CC: Valentin Longchamp <valentin.longchamp@keymile.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Anatolij Gustschin <agust@denx.de>
CC: Ira W. Snyder <iws@ovro.caltech.edu>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Kyle Moffett <Kyle.D.Moffett@boeing.com>
CC: Sebastien Carlier <sebastien.carlier@gmail.com>
CC: Stefan Roese <sr@denx.de>
CC: Peter Tyser <ptyser@xes-inc.com>
CC: Paul Gortmaker <paul.gortmaker@windriver.com>
CC: Peter Tyser <ptyser@xes-inc.com>
CC: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2018-02-09 08:36:40 -08:00
Ashish Kumar
63b2316c5c fsl-layerscape: Consolidate registers space defination for CCI-400 bus
CoreLink Cache Coherent Interconnect (CCI) provides full cache
coherency between two clusters of multi-core CPUs and I/O coherency
for devices and I/O masters.

This patch add new config option SYS_FSL_HAS_CCI400 and moves
existing register space definaton of CCI-400 bus to fsl_immap to be
shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
in Kconfig.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message, squashed patches for armv8 and armv7]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
York Sun
b406731aa9 driver/ddr/fsl: Add more debug registers
32 more debug registers are added for newer DDR controllers.

Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2016-09-14 14:05:32 -07:00
York Sun
d9be24c92d driver/ddr/fsl: Remove deskew_cntrl register
This register is reserved and shouldn't have been exposed.
Accessing it may have unexpected result on different SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-05-20 10:34:09 -07:00
York Sun
34e026f9b1 driver/ddr/fsl: Add DDR4 support to Freescale DDR driver
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
York Sun
9a17eb5b7e Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx
Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
structure for 83xx, 85xx and 86xx.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:46 -08:00