Commit graph

12 commits

Author SHA1 Message Date
Ludwig Zenz
6e75cb237d ARM: imx6: DHCOM i.MX6 PDK: enable pad pull ups of SS lines of spi used for boot
It turned out that after a reset the boot process from the spi bootflash is
disturbed by other spi slave devices connected to DHCOM SPI1, which uses the
same spi interface with a different SS line.

Therefore the pad pull ups are enabled.

Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.com>
2019-07-19 20:32:24 +02:00
Yangbo Lu
e37ac717d7 Convert to use fsl_esdhc_imx for i.MX platforms
Converted to use fsl_esdhc_imx for i.MX platforms.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
Acked-by: Jason Liu <Jason.hui.liu@nxp.com>
2019-06-23 14:18:34 +08:00
Ludwig Zenz
aa34505653 ARM: imx6: DHCOM i.MX6 PDK: use Kconfig for inclusion of DDR calibration
The four x16 DDR3 are wired in T-topology. From NXP AN4467:
'Although not required, T-Topologies may also benefit from performing
Write Leveling as there are package delays on both the processor and DDR
devices that can be de-skewed by performing Write Leveling. Therefore,
Freescale recommends determining Write Leveling calibration parameters
for all boards, regardless of topology used.'
That is why write level calibration is also done.

Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.com>
2019-04-25 19:16:24 +02:00
Ludwig Zenz
a44ca1346d ARM: imx6: update 1GB DDR3 calibration for DHCOM i.MX6qd PDK
The existing calibration values were found to be incorrect
in comparison to newly determined values.

The new values were generated with the help of 5 boards. They have
been determined with the NXP Utility 'DDR Stress Test (2.9.0)'.

Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.com>
2019-04-25 19:16:24 +02:00
Ludwig Zenz
0481bef035 ARM: imx6: DHCOM i.MX6 PDK: ddr init for 32bit bus and 4GBit chips
Support 1GIB + 2GIB DDR3 with 64bit bus width and 512MIB + 1GIB with 32bit bus width

Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
2018-07-23 11:02:14 +02:00
Ludwig Zenz
659ca2dd08 ARM: imx6: configure ddrcode pins in spl DHCOM i.MX6 PDK
Preperation for conditional DDR3 initialization based on GPIO codes.

Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
2018-07-23 11:02:03 +02:00
Ludwig Zenz
3d81584d40 Revert "ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK"
This reverts commit a637fe6f27.

The DDR DRAM calibration was enhanced by write leveling correction code.
It can be used with T-topology now.

Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
2018-07-23 11:01:41 +02:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Tom Rini
d024236e5a Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:48 -04:00
Marek Vasut
a637fe6f27 ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK
The DDR DRAM calibration doesn't work on T-topology sometimes, so disable it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2017-12-29 11:18:59 +01:00
Marek Vasut
b979e35230 ARM: imx6: Adjust DDR DRAM settings on DHCOM i.MX6 PDK
The board uses T-topology for the four x16 DRAM chips, so remove
the write-leveling from the SPL as that is only usefly on fly-by
topology and can be harmful on T-topology. Also update the DRAM
timing with values from calibration on multiple boards.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2017-11-16 10:43:22 +01:00
Marek Vasut
0a333602df ARM: imx6: Add DHCOM i.MX6 PDK board support
Add support for the DHCOM i.MX6 PDK board. This board has:
- FEC ethernet
- EHCI USB host
- 3x SDMMC

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2017-10-12 18:01:06 +02:00