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https://github.com/AsahiLinux/u-boot
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ARM: imx6: DHCOM i.MX6 PDK: ddr init for 32bit bus and 4GBit chips
Support 1GIB + 2GIB DDR3 with 64bit bus width and 512MIB + 1GIB with 32bit bus width Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
This commit is contained in:
Ludwig Zenz
Stefano Babic
parent
659ca2dd08
commit
0481bef035
1 changed files with 173 additions and 18 deletions
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@ -136,7 +136,31 @@ static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
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.grp_b7ds = 0x00000030,
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};
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static const struct mx6_mmdc_calibration dhcom_mmdc_calib = {
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static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x4g_1066 = {
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.p0_mpwldectrl0 = 0x00150019,
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.p0_mpwldectrl1 = 0x001C000B,
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.p1_mpwldectrl0 = 0x00020018,
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.p1_mpwldectrl1 = 0x0002000C,
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.p0_mpdgctrl0 = 0x43140320,
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.p0_mpdgctrl1 = 0x03080304,
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.p1_mpdgctrl0 = 0x43180320,
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.p1_mpdgctrl1 = 0x03100254,
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.p0_mprddlctl = 0x4830383C,
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.p1_mprddlctl = 0x3836323E,
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.p0_mpwrdlctl = 0x3E444642,
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.p1_mpwrdlctl = 0x42344442,
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};
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static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = {
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.p0_mpwldectrl0 = 0x0040003C,
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.p0_mpwldectrl1 = 0x0032003E,
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.p0_mpdgctrl0 = 0x42350231,
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.p0_mpdgctrl1 = 0x021A0218,
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.p0_mprddlctl = 0x4B4B4E49,
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.p0_mpwrdlctl = 0x3F3F3035,
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};
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static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = {
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.p0_mpwldectrl0 = 0x0011000E,
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.p0_mpwldectrl1 = 0x000E001B,
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.p1_mpwldectrl0 = 0x00190015,
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@ -151,23 +175,89 @@ static const struct mx6_mmdc_calibration dhcom_mmdc_calib = {
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.p1_mpwrdlctl = 0x473E4A3B,
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};
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static const struct mx6_ddr3_cfg dhcom_mem_ddr = {
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static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = {
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.p0_mpwldectrl0 = 0x003A003A,
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.p0_mpwldectrl1 = 0x0030002F,
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.p1_mpwldectrl0 = 0x002F0038,
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.p1_mpwldectrl1 = 0x00270039,
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.p0_mpdgctrl0 = 0x420F020F,
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.p0_mpdgctrl1 = 0x01760175,
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.p1_mpdgctrl0 = 0x41640171,
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.p1_mpdgctrl1 = 0x015E0160,
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.p0_mprddlctl = 0x45464B4A,
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.p1_mprddlctl = 0x49484A46,
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.p0_mpwrdlctl = 0x40402E32,
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.p1_mpwrdlctl = 0x3A3A3231,
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};
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static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x2g_800 = {
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.p0_mpwldectrl0 = 0x0040003C,
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.p0_mpwldectrl1 = 0x0032003E,
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.p0_mpdgctrl0 = 0x42350231,
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.p0_mpdgctrl1 = 0x021A0218,
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.p0_mprddlctl = 0x4B4B4E49,
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.p0_mpwrdlctl = 0x3F3F3035,
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};
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/*
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* 2 Gbit DDR3 memory
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* - NANYA #NT5CC128M16IP-DII
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* - NANYA #NT5CB128M16FP-DII
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*/
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static const struct mx6_ddr3_cfg dhcom_mem_ddr_2g = {
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.mem_speed = 1600,
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.density = 2,
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.width = 64,
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.width = 16,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1312,
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.trcd = 1375,
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.trcmin = 5863,
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.trasmin = 3750,
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};
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static const struct mx6_ddr_sysinfo dhcom_ddr_info = {
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/*
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* 4 Gbit DDR3 memory
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* - Intelligent Memory #IM4G16D3EABG-125I
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*/
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static const struct mx6_ddr3_cfg dhcom_mem_ddr_4g = {
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.mem_speed = 1600,
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.density = 4,
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.width = 16,
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.banks = 8,
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.rowaddr = 15,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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/* DDR3 64bit */
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static const struct mx6_ddr_sysinfo dhcom_ddr_64bit = {
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/* width of data bus:0=16,1=32,2=64 */
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.dsize = 2,
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.cs_density = 16,
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.cs_density = 32,
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.ncs = 1, /* single chip select */
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.cs1_mirror = 1,
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.rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
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.rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
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.walat = 1, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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.refsel = 1, /* Refresh cycles at 32KHz */
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.refr = 3, /* 4 refresh commands per refresh cycle */
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};
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/* DDR3 32bit */
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static const struct mx6_ddr_sysinfo dhcom_ddr_32bit = {
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/* width of data bus:0=16,1=32,2=64 */
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.dsize = 1,
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.cs_density = 32,
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.ncs = 1, /* single chip select */
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.cs1_mirror = 1,
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.rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
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@ -392,6 +482,81 @@ static void setup_iomux_usb(void)
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SETUP_IOMUX_PADS(usb_pads);
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}
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/* DRAM */
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static void dhcom_spl_dram_init(void)
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{
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enum dhcom_ddr3_code ddr3_code = dhcom_get_ddr3_code();
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if (is_mx6dq()) {
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mx6dq_dram_iocfg(64, &dhcom6dq_ddr_ioregs,
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&dhcom6dq_grp_ioregs);
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switch (ddr3_code) {
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default:
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printf("imx6qd: unsupported ddr3 code %d\n", ddr3_code);
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printf(" choosing 1024 MB\n");
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/* fall through */
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case DH_DDR3_SIZE_1GIB:
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mx6_dram_cfg(&dhcom_ddr_64bit,
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&dhcom_mmdc_calib_4x2g_1066,
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&dhcom_mem_ddr_2g);
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break;
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case DH_DDR3_SIZE_2GIB:
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mx6_dram_cfg(&dhcom_ddr_64bit,
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&dhcom_mmdc_calib_4x4g_1066,
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&dhcom_mem_ddr_4g);
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break;
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}
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/* Perform DDR DRAM calibration */
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udelay(100);
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mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
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} else if (is_cpu_type(MXC_CPU_MX6DL)) {
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mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs,
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&dhcom6sdl_grp_ioregs);
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switch (ddr3_code) {
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default:
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printf("imx6dl: unsupported ddr3 code %d\n", ddr3_code);
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printf(" choosing 1024 MB\n");
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/* fall through */
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case DH_DDR3_SIZE_1GIB:
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mx6_dram_cfg(&dhcom_ddr_64bit,
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&dhcom_mmdc_calib_4x2g_800,
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&dhcom_mem_ddr_2g);
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break;
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}
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/* Perform DDR DRAM calibration */
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udelay(100);
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mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
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} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
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mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs,
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&dhcom6sdl_grp_ioregs);
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switch (ddr3_code) {
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default:
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printf("imx6s: unsupported ddr3 code %d\n", ddr3_code);
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printf(" choosing 512 MB\n");
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/* fall through */
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case DH_DDR3_SIZE_512MIB:
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mx6_dram_cfg(&dhcom_ddr_32bit,
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&dhcom_mmdc_calib_2x2g_800,
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&dhcom_mem_ddr_2g);
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break;
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case DH_DDR3_SIZE_1GIB:
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mx6_dram_cfg(&dhcom_ddr_32bit,
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&dhcom_mmdc_calib_2x4g_800,
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&dhcom_mem_ddr_4g);
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break;
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}
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/* Perform DDR DRAM calibration */
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udelay(100);
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mmdc_do_dqs_calibration(&dhcom_ddr_32bit);
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}
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}
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void board_init_f(ulong dummy)
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{
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/* setup AIPS and disable watchdog */
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@ -415,18 +580,8 @@ void board_init_f(ulong dummy)
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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/* Start the DDR DRAM */
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if (is_mx6dq())
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mx6dq_dram_iocfg(dhcom_mem_ddr.width, &dhcom6dq_ddr_ioregs,
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&dhcom6dq_grp_ioregs);
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else
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mx6sdl_dram_iocfg(dhcom_mem_ddr.width, &dhcom6sdl_ddr_ioregs,
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&dhcom6sdl_grp_ioregs);
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mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr);
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/* Perform DDR DRAM calibration */
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udelay(100);
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mmdc_do_dqs_calibration(&dhcom_ddr_info);
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/* DDR3 initialization */
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dhcom_spl_dram_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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