Commit graph

41 commits

Author SHA1 Message Date
Bin Meng
02be57caf7 riscv: qemu: Enable usb keyboard as an input device
This brings PCI xHCI support to QEMU RISC-V and uses a usb keyboard
as one of the input devices.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-02 16:32:44 +08:00
Bin Meng
124308e67b riscv: qemu: Remove out-of-date "riscv, kernel-start" handling
Commit 66ffe57 ("riscv: qemu: detect and boot the kernel passed by QEMU")
added some logic to handle "riscv,kernel-start" in DT and stored the
address to an environment variable kernel_start.

However this "riscv,kernel-start" has never been an upstream DT binding.
The upstream QEMU never generates such a DT either. Presumably U-Boot
development was based on a downstream QEMU fork.

Now we drop all codes in commit 66ffe57, except that BOARD_LATE_INIT
is kept for later use.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-02 16:32:41 +08:00
Bin Meng
608b80b5b8 riscv: qemu: Enable PRE_CONSOLE_BUFFER
By default the video console only outputs messages after it's ready.
Messages before that won't show on the video console, but U-Boot has
an option to buffer the console messages before it's ready.

Enable this support, and carefully select an address for the buffer.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-02 16:32:36 +08:00
Bin Meng
716161663e riscv: qemu: Enable Bochs video support
Enable video console using the emulated Bochs VGA card.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-02 16:31:52 +08:00
Tom Rini
f23f1b5307 MAINTAINERS: Add a number of "common" directories
A number of platforms have "common" directories that are in turn not
listed by the board MAINTAINERS file.  Add these directories in many
cases.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-07-25 12:44:47 -04:00
Simon Glass
984639039f Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE
and this makes it imposible to use CONFIG_VAL().

Rename it to resolve this problem.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-31 11:01:31 -04:00
Bin Meng
cb052d7712 riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+
Since OpenSBI commit bf3ef53bb7f5 ("firmware: Enable FW_PIC by default"),
OpenSBI runs directly at the load address without any code movement.
This causes the SPL version of QEMU 'virt' U-Boot does not boot Linux
kernel anymore. In that case, OpenSBI is loaded and runs at 0x81000000,
and it creates a 512KiB PMP window from that address. When booting
the Linux kernel, moving kernel to its linking address 0x80200000
overlaps the PMP window, and a PMP access failure is raised.

Update SPL_OPENSBI_LOAD_ADDR to load OpenSBI to a safe address.

Reported-by: Yangjie Zhang <pyjmstr@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Yangjie Zhang <pyjmstr@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2022-10-20 15:22:33 +08:00
Heinrich Schuchardt
22e324c638 riscv: enable CONFIG_CMD_SBI for QEMU boards
Let CONFIG_TARGET_QEMU_VIRT imply CONFIG_CMD_SBI.

The sbi command provides detailed information about the SBI.
It is useful to test the discovery of extensions.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2022-04-06 09:40:05 +08:00
Anup Patel
ef19131b80 riscv: qemu: Implement is_flash_available() for MTD NOR
Currently, if MTD NOR is enabled then U-Boot tries to issue flash
commands even when CFI flash DT node is not present. This causes
access fault on RISC-V emulators or ISS which do not emulate CFI
flash. To handle this issue, we implement is_flash_available() for
qemu-riscv board which will return 1 only if CFI flash DT node is
present.

Fixes: d248627f9d ("riscv: qemu: Enable MTD NOR flash support")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2022-02-10 11:18:13 +08:00
Anup Patel
be7ce1a818 riscv: qemu: Enable HTIF console support
Enable support for HTIF console so that we can use QEMU RISC-V U-Boot
on RISC-V emulators and ISS having it.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2022-02-10 11:18:12 +08:00
Simon Glass
239d22c795 fdt: Enable OF_HAS_PRIOR_STAGE for most boards with OF_BOARD
Use this new Kconfig instead of OF_BOARD, so we know for sure which boards
obtain their devicetree from a prior stage. Leave sandbox alone since it
does not. Also don't touch xilinx_versal_virt since it does not have a
specific TARGET Kconfig.

This option implies OF_BOARD for now, but with future work standard
passage may be used instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add rpi_4_32b and rpi_arm64 to the list of boards converted]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-23 11:19:17 -05:00
Ilias Apalodimas
e7fb789612 sandbox: Remove OF_HOSTFILE
OF_HOSTFILE is used on sandbox configs only.  Although it's pretty
unique and not causing any confusions,  we are better of having simpler
config options for the DTB.

So let's replace that with the existing OF_BOARD.  U-Boot would then
have only three config options for the DTB origin.
- OF_SEPARATE, build separately from U-Boot
- OF_BOARD, board specific way of providing the DTB
- OF_EMBED embedded in the u-boot binary(should not be used in production

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-27 16:38:26 -04:00
Ilias Apalodimas
2e8d2f8843 riscv: Remove OF_PRIOR_STAGE from RISC-V boards
At some point back in 2018 prior_stage_fdt_address and OF_PRIOR_STAGE got
introduced,  in order to support a DTB handed over by an earlier stage boo
loader.  However we have another option in the Kconfig (OF_BOARD) which has
identical semantics.

On RISC-V some of the boards pick up the DTB from a1 and copy it in their
private gd_t.  Apart from that they copy it to prior_stage_fdt_address,  if
the Kconfig option is selected, which is unnecessary.

So let's switch the config option for those boards to OF_BOARD and define
the required board_fdt_blob_setup() for them.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-10-18 13:19:50 -04:00
Simon Glass
3232bdf0b3 pci: Drop DM_PCI
This option has not effect now. Drop it, using PCI instead where needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13 18:23:13 -04:00
Bin Meng
d248627f9d riscv: qemu: Enable MTD NOR flash support
Enable support to the 2 NOR flashes on the QEMU RISC-V virt machine.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-08-11 10:36:10 +02:00
Heinrich Schuchardt
2873ca2a78 riscv: enable SATA disk on QEMU RISC-V
Allow attaching a virtual SATA disk to QEMU RISC-V by implying
AHCI, AHCI_PCI, CMD_SCSI, DM_SCSI, PCI_INIT_R, SCSI, SCSI_AHCI.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-11-17 15:09:16 +08:00
Heinrich Schuchardt
19dd274b56 riscv: sort SPECIFIC_OPTIONS
Sort implied options in BOARD_SPECIFIC_OPTIONS in the same sequence as in
.config.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-11-17 15:09:16 +08:00
Bin Meng
a0cc38ab44 riscv: qemu: Add syscon reboot and poweroff support
This adds syscon reboot and poweroff support to QEMU RISC-V.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-24 14:55:55 +08:00
Simon Glass
f7ae49fc4f common: Drop log.h from common header
Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:18 -04:00
Simon Glass
4d72caa5b9 common: Drop image.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Lukas Auer
846b612014 Revert "riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL"
The commit was added as a workaround required in QEMU when using BBL as
the supervisor binary interface (SBI) for Linux. We are now using
OpenSBI to provide the SBI, the workaround is therefore not required
anymore and can be removed.

This reverts commit 897206c5cc.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-23 10:13:35 +08:00
Simon Glass
5255932f01 common: Move some board functions out of common.h
A number of board function belong in init.h with the others. Move them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:21 -05:00
Bin Meng
44016bc598 riscv: qemu: Fix kconfig build warning
When 'make qemu-riscv64_defconfig', there is a build warning:

  board/emulation/qemu-riscv/Kconfig:24:
  warning: config symbol defined without type

Fix it by specifying the config symbol type to 'hex'.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-08-26 16:09:02 +08:00
Lukas Auer
e456a81935 riscv: qemu: add SPL configuration
Add two new configurations (qemu-riscv{32,64}_spl_defconfig) with SPL
enabled for RISC-V QEMU. QEMU does not require SPL to run U-Boot. The
configurations are meant to help the development of SPL on RISC-V.

The configurations enable RAM as the only SPL boot device. Images must
be loaded at address 0x80200000. In the default boot flow, U-Boot SPL
starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot
proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is
then started in supervisor mode by OpenSBI.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-26 16:07:42 +08:00
Simon Glass
c7694dd483 env: Move env_set_hex() to env.h
Move env_set_hex() over to the new header file along with env_set_addr()
which uses it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
David Abdurachmanov
1493b140e4 qemu-riscv: enable VIRTIO_PCI
libvirt v.5.3.0 with QEMU 4.0.0 or above uses PCI automatically and
thus devices (network, storage, etc) are connected via PCI.

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-18 11:31:28 -04:00
Bin Meng
e64db0d92e riscv: qemu: Enable e1000 and nvme support
Since we have added the PCI support to the 'virt' target, enable
e1000 and NVME as alternate network and storage devices for these
virtio based devices.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-06-05 13:19:15 +08:00
Bin Meng
cd6b6199ea riscv: qemu: Enable PCI host ECAM generic driver
QEMU 4.0.0 'virt' target integrates a generic ECAM PCI host.
Enable the driver for it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-06-05 13:19:15 +08:00
Anup Patel
8aa278df0a riscv: qemu: Use correct SYS_TEXT_BASE for S-mode on 32bit system
For 32bit system, the OpenSBI (or BBL) will jump to 0x80400000 address
in S-mode whereas for 64bit system it will jump to 0x80200000 address
in S-mode.

Currently, the S-mode U-Boot sets SYS_TEXT_BASE to 0x80200000 for both
32bit and 64bit system. This breaks S-mode U-Boot for 32bit system.

This patch sets different SYS_TEXT_BASE for 32bit and 64bit system so
that S-mode U-Boot works fine for both.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Tested-by: Karsten Merker <merker@debian.org>
2019-05-09 16:46:24 +08:00
Lukas Auer
d0a8fd3e4d riscv: qemu: enable SMP
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08 09:44:26 +08:00
Anup Patel
fdff1f96a6 riscv: Rename cpu/qemu to cpu/generic
The QEMU CPU support under arch/riscv is pretty much generic
and works fine for SiFive Unleashed as well. In fact, there
will be quite a few RISC-V SOCs for which QEMU CPU support
will work fine.

This patch renames cpu/qemu to cpu/generic to indicate the
above fact. If there are SOC specific errata workarounds
required in cpu/generic then those can be done at runtime
in cpu/generic based on CPU vendor specific DT compatible
string.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27 09:12:33 +08:00
Anup Patel
9acaf60bfd riscv: qemu: Imply SIFIVE_SERIAL for emulation
This patch enables SiFive UART driver for QEMU RISC-V emulation
by implying SIFIVE_SERIAL on BOARD_SPECIFIC_OPTIONS.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18 09:56:54 +08:00
Bin Meng
84304d4866 riscv: qemu: Add platform-specific Kconfig options
Add the QEMU RISC-V platform-specific Kconfig options, to include
CPU and timer drivers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Anup Patel
4c60113647 riscv: Add S-mode defconfigs for QEMU virt machine
This patch adds S-mode defconfigs for QEMU virt machine so
that we can run u-boot in S-mode on QEMU using M-mode runtime
firmware (BBL or equivalent).

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-05 14:14:04 +08:00
Anup Patel
ef8c3d3fce riscv: qemu: Use different SYS_TEXT_BASE for S-mode
When u-boot runs in S-mode, the M-mode runtime firmware
(BBL or equivalent) uses memory range in 0x80000000 to
0x80200000. Due to this, we cannot use 0x80000000 as
SYS_TEXT_BASE when running in S-mode. Instead for S-mode,
we use 0x80200000 as SYS_TEXT_BASE.

Even Linux RISC-V kernel ignores/reserves memory range
0x80000000 to 0x80200000 because it runs in S-mode.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-05 14:13:59 +08:00
Lukas Auer
897206c5cc riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL
QEMU specifies the location of Linux (supplied with the -kernel
argument) in the device tree using the riscv,kernel-start and
riscv,kernel-end properties. We currently rely on the SBI implementation
of BBL to run Linux and therefore embed Linux as payload in BBL. This
causes an issue, because BBL detects the kernel properties in the device
tree and ignores the Linux payload as a result.
Work around this issue by clearing the kernel properties in the device
tree before booting Linux.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26 13:57:33 +08:00
Lukas Auer
66ffe5783b riscv: qemu: detect and boot the kernel passed by QEMU
QEMU embeds the location of the kernel image in the device tree. Store
this address in the environment as variable kernel_start. It is used in
the board-local distro boot command QEMU to boot the kernel with the
U-Boot device tree. The QEMU boot command is added as the first boot
target device.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
2018-11-26 13:57:33 +08:00
Lukas Auer
6e10e94ff7 riscv: qemu: use device tree passed by prior boot stage
QEMU provides a device tree, which is passed to U-Boot using register
a1. We are now able to directly select the device tree with the
configuration CONFIG_OF_PRIOR_STAGE. Replace the hard-coded address in
qemu-riscv with it.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:32 +08:00
Bin Meng
440d9a47f7 riscv: qemu: Include some useful commands
With the virtio net and blk drivers, we can do more stuff with some
useful commands. Imply those in the board Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-14 09:16:27 -08:00
Bin Meng
3c5196dca5 riscv: qemu: Enumerate virtio bus during early boot
Currently devices on the virtio bus is not automatically enumerated,
which means peripherals on the virtio bus are not discovered by their
drivers. This uses board_init() to do the virtio enumeration.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-14 09:16:27 -08:00
Bin Meng
510e379c49 riscv: Add QEMU virt board support
This adds QEMU RISC-V 'virt' board target support, with the hope of
helping people easily test U-Boot on RISC-V.

The QEMU virt machine models a generic RISC-V virtual machine with
support for the VirtIO standard networking and block storage devices.
It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and
it also uses device-tree to pass configuration information to guest
software. It implements RISC-V privileged architecture spec v1.10.

Both 32-bit and 64-bit builds are supported. Support is pretty much
preliminary, only booting to U-Boot shell with the UART driver on
a single core. Booting Linux is not supported yet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:48:37 +08:00