mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 13:43:28 +00:00
Convert CONFIG_ENABLE_36BIT_PHYS to Kconfig
This converts the following to Kconfig: CONFIG_ENABLE_36BIT_PHYS Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
parent
69a2bb6321
commit
fbc3621fb5
95 changed files with 84 additions and 22 deletions
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@ -1185,6 +1185,9 @@ config SYS_FSL_LBC_CLK_DIV
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Defines divider of platform clock(clock input to
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eLBC controller).
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config ENABLE_36BIT_PHYS
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bool "Enable 36bit physical address space support"
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config SYS_MPC85XX_NO_RESETVEC
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bool "Discard resetvec section and move bootpg section up"
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depends on MPC85xx
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@ -10,6 +10,7 @@ CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_MPC8548CDS=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_PHYS_64BIT=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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@ -10,6 +10,7 @@ CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_MPC8548CDS=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_DYNAMIC_SYS_CLK_FREQ=y
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@ -10,6 +10,7 @@ CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_MPC8548CDS=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_TARGET_MPC8548CDS_LEGACY=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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@ -14,6 +14,7 @@ CONFIG_SPL_DRIVERS_MISC=y
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CONFIG_SPL=y
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P1010RDB_PA=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PHYS_64BIT=y
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@ -8,6 +8,7 @@ CONFIG_ENV_ADDR=0xEFF20000
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P1010RDB_PA=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PHYS_64BIT=y
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CONFIG_FIT=y
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@ -13,6 +13,7 @@ CONFIG_SPL_DRIVERS_MISC=y
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CONFIG_SPL=y
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P1010RDB_PA=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PHYS_64BIT=y
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@ -15,6 +15,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI=y
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P1010RDB_PA=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PHYS_64BIT=y
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@ -14,6 +14,7 @@ CONFIG_SPL_DRIVERS_MISC=y
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CONFIG_SPL=y
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P1010RDB_PA=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_FIT=y
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@ -8,6 +8,7 @@ CONFIG_ENV_ADDR=0xEFF20000
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P1010RDB_PA=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -13,6 +13,7 @@ CONFIG_SPL_DRIVERS_MISC=y
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CONFIG_SPL=y
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P1010RDB_PA=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_FIT=y
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@ -15,6 +15,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI=y
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P1010RDB_PA=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_FIT=y
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@ -14,6 +14,7 @@ CONFIG_SPL_DRIVERS_MISC=y
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CONFIG_SPL=y
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P1010RDB_PB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PHYS_64BIT=y
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@ -8,6 +8,7 @@ CONFIG_ENV_ADDR=0xEFF20000
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P1010RDB_PB=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PHYS_64BIT=y
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CONFIG_FIT=y
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@ -13,6 +13,7 @@ CONFIG_SPL_DRIVERS_MISC=y
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CONFIG_SPL=y
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P1010RDB_PB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PHYS_64BIT=y
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@ -15,6 +15,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI=y
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P1010RDB_PB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PHYS_64BIT=y
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@ -14,6 +14,7 @@ CONFIG_SPL_DRIVERS_MISC=y
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CONFIG_SPL=y
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P1010RDB_PB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_FIT=y
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@ -8,6 +8,7 @@ CONFIG_ENV_ADDR=0xEFF20000
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P1010RDB_PB=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -13,6 +13,7 @@ CONFIG_SPL_DRIVERS_MISC=y
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CONFIG_SPL=y
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P1010RDB_PB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_FIT=y
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@ -15,6 +15,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI=y
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P1010RDB_PB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_FIT=y
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@ -14,6 +14,7 @@ CONFIG_SPL=y
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CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P1020RDB_PC=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PHYS_64BIT=y
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@ -13,6 +13,7 @@ CONFIG_SPL=y
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CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P1020RDB_PC=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PHYS_64BIT=y
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@ -15,6 +15,7 @@ CONFIG_SPL_SPI=y
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CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P1020RDB_PC=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PHYS_64BIT=y
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@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P1020RDB_PC=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PHYS_64BIT=y
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CONFIG_MP=y
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@ -14,6 +14,7 @@ CONFIG_SPL=y
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CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P1020RDB_PC=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_MP=y
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@ -13,6 +13,7 @@ CONFIG_SPL=y
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CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P1020RDB_PC=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_MP=y
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@ -15,6 +15,7 @@ CONFIG_SPL_SPI=y
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CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P1020RDB_PC=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_MP=y
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@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P1020RDB_PC=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_MP=y
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CONFIG_FIT=y
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@ -14,6 +14,7 @@ CONFIG_SPL=y
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CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P1020RDB_PD=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_MP=y
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@ -13,6 +13,7 @@ CONFIG_SPL=y
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CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P1020RDB_PD=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_MP=y
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@ -15,6 +15,7 @@ CONFIG_SPL_SPI=y
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CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P1020RDB_PD=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_MP=y
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@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P1020RDB_PD=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_MP=y
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CONFIG_FIT=y
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@ -14,6 +14,7 @@ CONFIG_SPL=y
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CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P2020RDB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PHYS_64BIT=y
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@ -13,6 +13,7 @@ CONFIG_SPL=y
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CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P2020RDB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PHYS_64BIT=y
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@ -15,6 +15,7 @@ CONFIG_SPL_SPI=y
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CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P2020RDB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PHYS_64BIT=y
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@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P2020RDB=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_PHYS_64BIT=y
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CONFIG_MP=y
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@ -14,6 +14,7 @@ CONFIG_SPL=y
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CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P2020RDB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_MP=y
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@ -13,6 +13,7 @@ CONFIG_SPL=y
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CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P2020RDB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_MP=y
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@ -15,6 +15,7 @@ CONFIG_SPL_SPI=y
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CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P2020RDB=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_MP=y
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@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P2020RDB=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_MPC85XX_NO_RESETVEC=y
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CONFIG_MP=y
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CONFIG_FIT=y
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@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P2041RDB=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P2041RDB=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P2041RDB=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -8,6 +8,7 @@ CONFIG_ENV_ADDR=0xEFF20000
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P2041RDB=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
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CONFIG_MPC85xx=y
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CONFIG_TARGET_P3041DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P3041DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P3041DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -8,6 +8,7 @@ CONFIG_ENV_ADDR=0xEFF20000
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P3041DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P4080DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P4080DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -8,6 +8,7 @@ CONFIG_ENV_ADDR=0xEFF20000
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P4080DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P5040DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P5040DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P5040DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -8,6 +8,7 @@ CONFIG_ENV_ADDR=0xEFF20000
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P5040DS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -12,6 +12,7 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T1024RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
|
|
|
@ -13,6 +13,7 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T1024RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
|
|
|
@ -15,6 +15,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
|||
CONFIG_SPL_SPI=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T1024RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
|
|
|
@ -8,6 +8,7 @@ CONFIG_ENV_ADDR=0xEFF20000
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T1024RDB=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -11,6 +11,7 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T1042D4RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -12,6 +12,7 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T1042D4RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
|
|
|
@ -14,6 +14,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
|||
CONFIG_SPL_SPI=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T1042D4RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
|
|
|
@ -7,6 +7,7 @@ CONFIG_ENV_ADDR=0xEFF20000
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T1042D4RDB=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -18,6 +18,7 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080QDS=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -19,6 +19,7 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080QDS=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
|
|
|
@ -13,6 +13,7 @@ CONFIG_FSL_QIXIS=y
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080QDS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
|
|
|
@ -21,6 +21,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
|||
CONFIG_SPL_SPI=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080QDS=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
|
|
|
@ -13,6 +13,7 @@ CONFIG_ENV_ADDR=0xFFE20000
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080QDS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SRIO_PCIE_BOOT_SLAVE=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
|
|
|
@ -14,6 +14,7 @@ CONFIG_ENV_ADDR=0xEFF20000
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080QDS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -15,6 +15,7 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
|
|
|
@ -16,6 +16,7 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
|
|
|
@ -18,6 +18,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
|||
CONFIG_SPL_SPI=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
|
|
|
@ -11,6 +11,7 @@ CONFIG_ENV_ADDR=0xEFF20000
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080RDB=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -15,6 +15,7 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_T2080RDB_REV_D=y
|
||||
|
|
|
@ -16,6 +16,7 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_T2080RDB_REV_D=y
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
|
|
|
@ -18,6 +18,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
|||
CONFIG_SPL_SPI=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_T2080RDB_REV_D=y
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
|
|
|
@ -11,6 +11,7 @@ CONFIG_ENV_ADDR=0xEFF20000
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T2080RDB=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_T2080RDB_REV_D=y
|
||||
CONFIG_SYS_MEMTEST_START=0x00200000
|
||||
CONFIG_SYS_MEMTEST_END=0x00400000
|
||||
|
|
|
@ -16,6 +16,7 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T4240RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
|
|
|
@ -11,6 +11,7 @@ CONFIG_ENV_ADDR=0xEFF20000
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T4240RDB=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -10,6 +10,7 @@ CONFIG_ENV_ADDR=0xebf20000
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_KMCENT2=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_KM_DEF_NETDEV="eth2"
|
||||
CONFIG_KM_IVM_BUS=2
|
||||
CONFIG_MP=y
|
||||
|
|
|
@ -6,6 +6,7 @@ CONFIG_SYS_CLK_FREQ=33000000
|
|||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_QEMU_PPCE500=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
|
@ -9,6 +9,7 @@ CONFIG_ENV_ADDR=0xFFF40000
|
|||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_SOCRATES=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
|
|
|
@ -34,7 +34,6 @@
|
|||
/*
|
||||
* Only possible on E500 Version 2 or newer cores.
|
||||
*/
|
||||
#define CONFIG_ENABLE_36BIT_PHYS 1
|
||||
|
||||
#define CONFIG_SYS_CCSRBAR 0xe0000000
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
|
||||
|
|
|
@ -108,9 +108,6 @@
|
|||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
|
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_SYS_DDR_RAW_TIMING
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 1
|
||||
|
|
|
@ -58,8 +58,6 @@
|
|||
#define CONFIG_SYS_CACHE_STASHING
|
||||
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
|
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
|
||||
|
||||
/*
|
||||
|
|
|
@ -15,7 +15,6 @@
|
|||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
|
||||
|
|
|
@ -83,8 +83,6 @@
|
|||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
|
||||
#endif
|
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
/*
|
||||
* Config the L3 Cache as L3 SRAM
|
||||
*/
|
||||
|
|
|
@ -22,7 +22,6 @@
|
|||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
|
||||
|
|
|
@ -17,7 +17,6 @@
|
|||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
|
||||
|
|
|
@ -56,8 +56,6 @@
|
|||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
|
||||
#endif
|
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
/*
|
||||
* Config the L3 Cache as L3 SRAM
|
||||
*/
|
||||
|
|
|
@ -62,8 +62,6 @@
|
|||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
|
||||
#endif
|
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
|
||||
|
||||
/*
|
||||
|
|
|
@ -152,8 +152,6 @@
|
|||
#define CONFIG_SYS_CACHE_STASHING
|
||||
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
|
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
/* POST memory regions test */
|
||||
#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS
|
||||
|
||||
|
|
|
@ -111,8 +111,6 @@
|
|||
*/
|
||||
#define CONFIG_L2_CACHE
|
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
#define CONFIG_SYS_CCSRBAR 0xffe00000
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
|
||||
|
||||
|
|
|
@ -11,8 +11,6 @@
|
|||
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
/* Needed to fill the ccsrbar pointer */
|
||||
|
||||
/* Virtual address to CCSRBAR */
|
||||
|
|
|
@ -22,7 +22,6 @@
|
|||
/*
|
||||
* Only possible on E500 Version 2 or newer cores.
|
||||
*/
|
||||
#define CONFIG_ENABLE_36BIT_PHYS 1
|
||||
|
||||
/*
|
||||
* sysclk for MPC85xx
|
||||
|
|
Loading…
Reference in a new issue