mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 07:31:15 +00:00
arm: dts: imx8mp: Sync with linux-next 20231019
Sync imx8mp.dtsi and imx8mp-clock.h with linux-next 20231019. Signed-off-by: Fabio Estevam <festevam@denx.de>
This commit is contained in:
Fabio Estevam
Fabio Estevam
parent
05dffb9fb1
commit
f319766891
2 changed files with 526 additions and 19 deletions
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@ -202,6 +202,60 @@
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clock-output-names = "clk_ext4";
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};
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funnel {
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/*
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* non-configurable funnel don't show up on the AMBA
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* bus. As such no need to add "arm,primecell".
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*/
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compatible = "arm,coresight-static-funnel";
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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ca_funnel_in_port0: endpoint {
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remote-endpoint = <&etm0_out_port>;
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};
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};
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port@1 {
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reg = <1>;
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ca_funnel_in_port1: endpoint {
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remote-endpoint = <&etm1_out_port>;
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};
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};
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port@2 {
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reg = <2>;
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ca_funnel_in_port2: endpoint {
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remote-endpoint = <&etm2_out_port>;
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};
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};
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port@3 {
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reg = <3>;
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ca_funnel_in_port3: endpoint {
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remote-endpoint = <&etm3_out_port>;
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};
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};
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};
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out-ports {
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port {
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ca_funnel_out_port0: endpoint {
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remote-endpoint = <&hugo_funnel_in_port0>;
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};
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};
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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@ -304,6 +358,153 @@
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nvmem-cells = <&imx8mp_uid>;
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nvmem-cell-names = "soc_unique_id";
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etm0: etm@28440000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x28440000 0x1000>;
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cpu = <&A53_0>;
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clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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etm0_out_port: endpoint {
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remote-endpoint = <&ca_funnel_in_port0>;
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};
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};
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};
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};
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etm1: etm@28540000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x28540000 0x1000>;
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cpu = <&A53_1>;
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clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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etm1_out_port: endpoint {
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remote-endpoint = <&ca_funnel_in_port1>;
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};
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};
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};
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};
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etm2: etm@28640000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x28640000 0x1000>;
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cpu = <&A53_2>;
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clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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etm2_out_port: endpoint {
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remote-endpoint = <&ca_funnel_in_port2>;
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};
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};
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};
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};
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etm3: etm@28740000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x28740000 0x1000>;
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cpu = <&A53_3>;
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clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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etm3_out_port: endpoint {
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remote-endpoint = <&ca_funnel_in_port3>;
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};
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};
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};
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};
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funnel@28c03000 {
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0x28c03000 0x1000>;
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clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
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clock-names = "apb_pclk";
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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hugo_funnel_in_port0: endpoint {
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remote-endpoint = <&ca_funnel_out_port0>;
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};
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};
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port@1 {
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reg = <1>;
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hugo_funnel_in_port1: endpoint {
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/* M7 input */
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};
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};
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port@2 {
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reg = <2>;
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hugo_funnel_in_port2: endpoint {
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/* DSP input */
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};
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};
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/* the other input ports are not connect to anything */
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};
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out-ports {
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port {
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hugo_funnel_out_port0: endpoint {
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remote-endpoint = <&etf_in_port>;
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};
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};
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};
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};
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etf@28c04000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x28c04000 0x1000>;
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clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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etf_in_port: endpoint {
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remote-endpoint = <&hugo_funnel_out_port0>;
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};
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};
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};
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out-ports {
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port {
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etf_out_port: endpoint {
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remote-endpoint = <&etr_in_port>;
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};
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};
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};
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};
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etr@28c06000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x28c06000 0x1000>;
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clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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etr_in_port: endpoint {
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remote-endpoint = <&etf_out_port>;
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};
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};
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};
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};
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aips1: bus@30000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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reg = <0x30000000 0x400000>;
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@ -497,7 +698,7 @@
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snvs_rtc: snvs-rtc-lp {
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compatible = "fsl,sec-v4.0-mon-rtc-lp";
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regmap =<&snvs>;
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regmap = <&snvs>;
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offset = <0x34>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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@ -534,26 +735,16 @@
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<&clk IMX8MP_CLK_A53_CORE>,
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<&clk IMX8MP_CLK_NOC>,
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<&clk IMX8MP_CLK_NOC_IO>,
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<&clk IMX8MP_CLK_GIC>,
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<&clk IMX8MP_CLK_AUDIO_AHB>,
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<&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
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<&clk IMX8MP_AUDIO_PLL1>,
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<&clk IMX8MP_AUDIO_PLL2>;
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<&clk IMX8MP_CLK_GIC>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
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<&clk IMX8MP_ARM_PLL_OUT>,
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<&clk IMX8MP_SYS_PLL2_1000M>,
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<&clk IMX8MP_SYS_PLL1_800M>,
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<&clk IMX8MP_SYS_PLL2_500M>,
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<&clk IMX8MP_SYS_PLL1_800M>,
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<&clk IMX8MP_SYS_PLL1_800M>;
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<&clk IMX8MP_SYS_PLL2_500M>;
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assigned-clock-rates = <0>, <0>,
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<1000000000>,
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<800000000>,
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<500000000>,
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<400000000>,
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<800000000>,
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<393216000>,
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<361267200>;
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<500000000>;
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};
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src: reset-controller@30390000 {
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@ -595,6 +786,19 @@
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reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
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};
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pgc_audio: power-domain@5 {
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#power-domain-cells = <0>;
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reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
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clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
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<&clk IMX8MP_CLK_AUDIO_AXI>;
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assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
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<&clk IMX8MP_CLK_AUDIO_AXI_SRC>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
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<&clk IMX8MP_SYS_PLL1_800M>;
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assigned-clock-rates = <400000000>,
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<600000000>;
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};
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pgc_gpu2d: power-domain@6 {
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#power-domain-cells = <0>;
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reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
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@ -653,7 +857,7 @@
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pgc_vpumix: power-domain@19 {
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#power-domain-cells = <0>;
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reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
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clocks =<&clk IMX8MP_CLK_VPU_ROOT>;
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clocks = <&clk IMX8MP_CLK_VPU_ROOT>;
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};
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pgc_vpu_g1: power-domain@20 {
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@ -1147,6 +1351,198 @@
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};
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};
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aips5: bus@30c00000 {
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compatible = "fsl,aips-bus", "simple-bus";
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reg = <0x30c00000 0x400000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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spba-bus@30c00000 {
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compatible = "fsl,spba-bus", "simple-bus";
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reg = <0x30c00000 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sai1: sai@30c10000 {
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compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
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reg = <0x30c10000 0x10000>;
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#sound-dai-cells = <0>;
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clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>,
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<&clk IMX8MP_CLK_DUMMY>,
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<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>,
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<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>,
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<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>;
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clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
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dma-names = "rx", "tx";
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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sai2: sai@30c20000 {
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compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
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reg = <0x30c20000 0x10000>;
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#sound-dai-cells = <0>;
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clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>,
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<&clk IMX8MP_CLK_DUMMY>,
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<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>,
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<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>,
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<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>;
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clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
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dma-names = "rx", "tx";
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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sai3: sai@30c30000 {
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compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
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reg = <0x30c30000 0x10000>;
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#sound-dai-cells = <0>;
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clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>,
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<&clk IMX8MP_CLK_DUMMY>,
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<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>,
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<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>,
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<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>;
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clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
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dma-names = "rx", "tx";
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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sai5: sai@30c50000 {
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compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
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reg = <0x30c50000 0x10000>;
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#sound-dai-cells = <0>;
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clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>,
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<&clk IMX8MP_CLK_DUMMY>,
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<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>,
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<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>,
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<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>;
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clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
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dma-names = "rx", "tx";
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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sai6: sai@30c60000 {
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compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
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reg = <0x30c60000 0x10000>;
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#sound-dai-cells = <0>;
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clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>,
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<&clk IMX8MP_CLK_DUMMY>,
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<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>,
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<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>,
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<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>;
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clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
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dma-names = "rx", "tx";
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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sai7: sai@30c80000 {
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compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
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reg = <0x30c80000 0x10000>;
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#sound-dai-cells = <0>;
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clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>,
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<&clk IMX8MP_CLK_DUMMY>,
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<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>,
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<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>,
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<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>;
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clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
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dma-names = "rx", "tx";
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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easrc: easrc@30c90000 {
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compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc";
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reg = <0x30c90000 0x10000>;
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interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_ASRC_IPG>;
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clock-names = "mem";
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dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
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<&sdma2 18 23 0> , <&sdma2 19 23 0>,
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<&sdma2 20 23 0> , <&sdma2 21 23 0>,
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<&sdma2 22 23 0> , <&sdma2 23 23 0>;
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dma-names = "ctx0_rx", "ctx0_tx",
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"ctx1_rx", "ctx1_tx",
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"ctx2_rx", "ctx2_tx",
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"ctx3_rx", "ctx3_tx";
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firmware-name = "imx/easrc/easrc-imx8mn.bin";
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fsl,asrc-rate = <8000>;
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fsl,asrc-format = <2>;
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status = "disabled";
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};
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micfil: audio-controller@30ca0000 {
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compatible = "fsl,imx8mp-micfil";
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reg = <0x30ca0000 0x10000>;
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#sound-dai-cells = <0>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_IPG>,
|
||||
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_SEL>,
|
||||
<&clk IMX8MP_AUDIO_PLL1_OUT>,
|
||||
<&clk IMX8MP_AUDIO_PLL2_OUT>,
|
||||
<&clk IMX8MP_CLK_EXT3>;
|
||||
clock-names = "ipg_clk", "ipg_clk_app",
|
||||
"pll8k", "pll11k", "clkext3";
|
||||
dmas = <&sdma2 24 25 0x80000000>;
|
||||
dma-names = "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
sdma3: dma-controller@30e00000 {
|
||||
compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
|
||||
reg = <0x30e00000 0x10000>;
|
||||
#dma-cells = <3>;
|
||||
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>,
|
||||
<&clk IMX8MP_CLK_AUDIO_ROOT>;
|
||||
clock-names = "ipg", "ahb";
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
|
||||
};
|
||||
|
||||
sdma2: dma-controller@30e10000 {
|
||||
compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
|
||||
reg = <0x30e10000 0x10000>;
|
||||
#dma-cells = <3>;
|
||||
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>,
|
||||
<&clk IMX8MP_CLK_AUDIO_ROOT>;
|
||||
clock-names = "ipg", "ahb";
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
|
||||
};
|
||||
|
||||
audio_blk_ctrl: clock-controller@30e20000 {
|
||||
compatible = "fsl,imx8mp-audio-blk-ctrl";
|
||||
reg = <0x30e20000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
|
||||
<&clk IMX8MP_CLK_SAI1>,
|
||||
<&clk IMX8MP_CLK_SAI2>,
|
||||
<&clk IMX8MP_CLK_SAI3>,
|
||||
<&clk IMX8MP_CLK_SAI5>,
|
||||
<&clk IMX8MP_CLK_SAI6>,
|
||||
<&clk IMX8MP_CLK_SAI7>;
|
||||
clock-names = "ahb",
|
||||
"sai1", "sai2", "sai3",
|
||||
"sai5", "sai6", "sai7";
|
||||
power-domains = <&pgc_audio>;
|
||||
};
|
||||
};
|
||||
|
||||
noc: interconnect@32700000 {
|
||||
compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
|
||||
reg = <0x32700000 0x100000>;
|
||||
|
|
@ -1174,6 +1570,118 @@
|
|||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
isi_0: isi@32e00000 {
|
||||
compatible = "fsl,imx8mp-isi";
|
||||
reg = <0x32e00000 0x4000>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
|
||||
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
|
||||
clock-names = "axi", "apb";
|
||||
fsl,blk-ctrl = <&media_blk_ctrl>;
|
||||
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
isi_in_0: endpoint {
|
||||
remote-endpoint = <&mipi_csi_0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
isi_in_1: endpoint {
|
||||
remote-endpoint = <&mipi_csi_1_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dewarp: dwe@32e30000 {
|
||||
compatible = "nxp,imx8mp-dw100";
|
||||
reg = <0x32e30000 0x10000>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
|
||||
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
|
||||
clock-names = "axi", "ahb";
|
||||
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
|
||||
};
|
||||
|
||||
mipi_csi_0: csi@32e40000 {
|
||||
compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
|
||||
reg = <0x32e40000 0x10000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <500000000>;
|
||||
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
|
||||
<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
|
||||
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
|
||||
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
|
||||
clock-names = "pclk", "wrap", "phy", "axi";
|
||||
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
|
||||
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
|
||||
assigned-clock-rates = <500000000>;
|
||||
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mipi_csi_0_out: endpoint {
|
||||
remote-endpoint = <&isi_in_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mipi_csi_1: csi@32e50000 {
|
||||
compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
|
||||
reg = <0x32e50000 0x10000>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <266000000>;
|
||||
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
|
||||
<&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
|
||||
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
|
||||
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
|
||||
clock-names = "pclk", "wrap", "phy", "axi";
|
||||
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
|
||||
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
|
||||
assigned-clock-rates = <266000000>;
|
||||
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mipi_csi_1_out: endpoint {
|
||||
remote-endpoint = <&isi_in_1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mipi_dsi: dsi@32e60000 {
|
||||
compatible = "fsl,imx8mp-mipi-dsim";
|
||||
reg = <0x32e60000 0x400>;
|
||||
|
|
@ -1382,8 +1890,8 @@
|
|||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
|
||||
<0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
|
||||
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
|
||||
<0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
|
||||
num-lanes = <1>;
|
||||
num-viewport = <4>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
|
|||
|
|
@ -130,7 +130,7 @@
|
|||
#define IMX8MP_CLK_SAI1 123
|
||||
#define IMX8MP_CLK_SAI2 124
|
||||
#define IMX8MP_CLK_SAI3 125
|
||||
#define IMX8MP_CLK_SAI4 126
|
||||
/* #define IMX8MP_CLK_SAI4 126 */
|
||||
#define IMX8MP_CLK_SAI5 127
|
||||
#define IMX8MP_CLK_SAI6 128
|
||||
#define IMX8MP_CLK_ENET_QOS 129
|
||||
|
|
@ -376,7 +376,6 @@
|
|||
#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36
|
||||
#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37
|
||||
#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38
|
||||
#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42
|
||||
|
|
|
|||
Loading…
Reference in a new issue