mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-26 14:40:41 +00:00
BUBINGA405EP port fixed.
This commit is contained in:
stroese
parent
4e5ca3eb67
commit
b828dda657
4 changed files with 138 additions and 35 deletions
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@ -23,7 +23,6 @@
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long int spd_sdram (void);
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#include <common.h>
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#include "bubinga405ep.h"
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#include <asm/processor.h>
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@ -82,18 +81,11 @@ int checkboard (void)
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unsigned char *s = getenv ("serial#");
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unsigned char *e;
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puts ("Board: ");
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puts ("Board: IBM 405EP Eval Board");
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if (!s || strncmp (s, "BUBINGA405EP", 9)) {
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puts ("### No HW ID - assuming WALNUT405");
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} else {
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for (e = s; *e; ++e) {
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if (*e == ' ')
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break;
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}
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for (; s < e; ++s) {
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putc (*s);
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}
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if (s != NULL) {
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puts (", serial# ");
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puts (s);
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}
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putc ('\n');
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@ -101,6 +101,11 @@ unsigned long flash_init (void)
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FLASH_BASE0_PRELIM,
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FLASH_BASE0_PRELIM+CFG_MONITOR_LEN-1,
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&flash_info[0]);
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/* Also protect sector containing initial power-up instruction */
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(void)flash_protect(FLAG_PROTECT_SET,
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0xFFFFFFFC,
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0xFFFFFFFF,
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&flash_info[0]);
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size_b1 = 0 ;
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flash_info[0].size = size_b0;
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}
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@ -143,6 +148,16 @@ unsigned long flash_init (void)
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base_b0+size_b0-CFG_MONITOR_LEN,
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base_b0+size_b0-1,
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&flash_info[0]);
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/* Also protect sector containing initial power-up instruction */
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/* (flash_protect() checks address range - other call ignored) */
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(void)flash_protect(FLAG_PROTECT_SET,
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0xFFFFFFFC,
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0xFFFFFFFF,
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&flash_info[0]);
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(void)flash_protect(FLAG_PROTECT_SET,
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0xFFFFFFFC,
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0xFFFFFFFF,
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&flash_info[1]);
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if (size_b1) {
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/* Re-do sizing to get full correct info */
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@ -493,18 +508,18 @@ int wait_for_DQ7(flash_info_t *info, int sect)
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volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
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start = get_timer (0);
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last = start;
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while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
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if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
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printf ("Timeout\n");
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return -1;
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last = 0;
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while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
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if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
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printf ("Timeout\n");
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return -1;
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}
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/* show that we're waiting */
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if ((now - last) > 1000) { /* every second */
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putc ('.');
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last = now;
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}
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}
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/* show that we're waiting */
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if ((now - last) > 1000) { /* every second */
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putc ('.');
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last = now;
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}
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}
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return 0;
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}
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@ -1384,14 +1384,94 @@ trap_reloc:
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/**************************************************************************/
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#ifdef CONFIG_405EP
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ppc405ep_init:
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#ifdef CONFIG_BUBINGA405EP
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/*
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* Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
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* function) to support FPGA and NVRAM accesses below.
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*/
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lis r3,GPIO0_OSRH@h /* config GPIO output select */
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ori r3,r3,GPIO0_OSRH@l
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lis r4,CFG_GPIO0_OSRH@h
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ori r4,r4,CFG_GPIO0_OSRH@l
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stw r4,0(r3)
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lis r3,GPIO0_OSRL@h
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ori r3,r3,GPIO0_OSRL@l
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lis r4,CFG_GPIO0_OSRL@h
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ori r4,r4,CFG_GPIO0_OSRL@l
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stw r4,0(r3)
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lis r3,GPIO0_ISR1H@h /* config GPIO input select */
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ori r3,r3,GPIO0_ISR1H@l
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lis r4,CFG_GPIO0_ISR1H@h
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ori r4,r4,CFG_GPIO0_ISR1H@l
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stw r4,0(r3)
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lis r3,GPIO0_ISR1L@h
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ori r3,r3,GPIO0_ISR1L@l
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lis r4,CFG_GPIO0_ISR1L@h
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ori r4,r4,CFG_GPIO0_ISR1L@l
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stw r4,0(r3)
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lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
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ori r3,r3,GPIO0_TSRH@l
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lis r4,CFG_GPIO0_TSRH@h
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ori r4,r4,CFG_GPIO0_TSRH@l
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stw r4,0(r3)
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lis r3,GPIO0_TSRL@h
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ori r3,r3,GPIO0_TSRL@l
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lis r4,CFG_GPIO0_TSRL@h
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ori r4,r4,CFG_GPIO0_TSRL@l
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stw r4,0(r3)
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lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
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ori r3,r3,GPIO0_TCR@l
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lis r4,CFG_GPIO0_TCR@h
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ori r4,r4,CFG_GPIO0_TCR@l
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stw r4,0(r3)
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li r3,pb1ap /* program EBC bank 1 for RTC access */
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mtdcr ebccfga,r3
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lis r3,CFG_EBC_PB1AP@h
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ori r3,r3,CFG_EBC_PB1AP@l
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mtdcr ebccfgd,r3
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li r3,pb1cr
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mtdcr ebccfga,r3
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lis r3,CFG_EBC_PB1CR@h
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ori r3,r3,CFG_EBC_PB1CR@l
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mtdcr ebccfgd,r3
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li r3,pb1ap /* program EBC bank 1 for RTC access */
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mtdcr ebccfga,r3
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lis r3,CFG_EBC_PB1AP@h
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ori r3,r3,CFG_EBC_PB1AP@l
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mtdcr ebccfgd,r3
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li r3,pb1cr
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mtdcr ebccfga,r3
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lis r3,CFG_EBC_PB1CR@h
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ori r3,r3,CFG_EBC_PB1CR@l
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mtdcr ebccfgd,r3
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li r3,pb4ap /* program EBC bank 4 for FPGA access */
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mtdcr ebccfga,r3
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lis r3,CFG_EBC_PB4AP@h
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ori r3,r3,CFG_EBC_PB4AP@l
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mtdcr ebccfgd,r3
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li r3,pb4cr
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mtdcr ebccfga,r3
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lis r3,CFG_EBC_PB4CR@h
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ori r3,r3,CFG_EBC_PB4CR@l
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mtdcr ebccfgd,r3
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#endif
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addi r3,0,CPC0_PCI_HOST_CFG_EN
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#ifdef CONFIG_BUBINGA405EP
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/*
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!-----------------------------------------------------------------------
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! Check FPGA for PCI internal/external arbitration
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! If board is set to internal arbitration, update cpc0_pci
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!-----------------------------------------------------------------------
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*/
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addi r3,0,CPC0_PCI_HOST_CFG_EN
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#ifdef CONFIG_BUBINGA405EP
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addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
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ori r5,r5,FPGA_REG1@l
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lbz r5,0x0(r5) /* read to get PCI arb selection */
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@ -30,6 +30,7 @@
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/* Debug options */
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/*#define __DEBUG_START_FROM_SRAM__ */
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/*#define DEBUG 1*/
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/*
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@ -148,13 +149,21 @@
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*/
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_PCI | \
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CFG_CMD_CACHE | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_EEPROM | \
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CFG_CMD_ELF | \
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CFG_CMD_I2C | \
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CFG_CMD_IRQ | \
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CFG_CMD_KGDB | \
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CFG_CMD_DHCP | \
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CFG_CMD_DATE | \
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CFG_CMD_DATE | \
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CFG_CMD_ELF )
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CFG_CMD_MII | \
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CFG_CMD_NET | \
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CFG_CMD_PCI | \
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CFG_CMD_PING | \
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CFG_CMD_REGINFO | \
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CFG_CMD_SDRAM | \
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0 )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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@ -207,6 +216,14 @@
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
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#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
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#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
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#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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#endif
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/*-----------------------------------------------------------------------
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* PCI stuff
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@ -220,9 +237,11 @@
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
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#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
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#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
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#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
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#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
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#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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@ -291,7 +310,7 @@
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#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
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#ifdef CFG_ENV_IS_IN_NVRAM
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#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
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#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
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#define CFG_ENV_ADDR \
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(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
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#endif
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@ -314,9 +333,6 @@
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#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
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/* Configuration Port location */
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#define CONFIG_PORT_ADDR 0xF0000500
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in data cache)
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*/
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