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Merge branch 'next_soc/v3x' of https://source.denx.de/u-boot/custodians/u-boot-sh into next

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This commit is contained in:
Tom Rini 2023-06-09 10:30:26 -04:00
commit ac7ca69209
32 changed files with 1618 additions and 244 deletions
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2
arch/arm/dts/Makefile
View file

@ -1050,7 +1050,9 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a77965-ulcb-u-boot.dtb \
r8a77965-salvator-x-u-boot.dtb \
r8a77970-eagle-u-boot.dtb \
r8a77970-v3msk-u-boot.dtb \
r8a77980-condor-u-boot.dtb \
r8a77980-v3hsk-u-boot.dtb \
r8a77990-ebisu-u-boot.dtb \
r8a77995-draak-u-boot.dtb

65
arch/arm/dts/r8a77970-v3msk-u-boot.dts Normal file
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@ -0,0 +1,65 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot for the V3MSK board
*
* Copyright (C) 2019 Cogent Embedded, Inc.
*/
#include "r8a77970-v3msk.dts"
#include "r8a77970-u-boot.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
spi0 = &rpc;
};
cpld {
compatible = "renesas,v3msk-cpld";
status = "okay";
gpio-mdc = <&gpio1 21 0>;
gpio-mosi = <&gpio1 22 0>;
gpio-miso = <&gpio1 23 0>;
gpio-enablez = <&gpio1 19 0>;
/* Disable V3MSK Videobox Mini CANFD PHY */
gpios = <&gpio0 12 0>, <&gpio0 14 0>;
};
};
&avb {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
};
&phy0 {
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
&pfc {
avb0_pins: avb {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
function = "avb0";
};
};
};
&rpc {
num-cs = <1>;
status = "okay";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
flash0: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
reg = <0>;
status = "okay";
};
};

303
arch/arm/dts/r8a77970-v3msk.dts Normal file
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@ -0,0 +1,303 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the V3M Starter Kit board
*
* Copyright (C) 2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
*/
/dts-v1/;
#include "r8a77970.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas V3M Starter Kit board";
compatible = "renesas,v3msk", "renesas,r8a77970";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
serial0 = &scif0;
};
chosen {
stdout-path = "serial0:115200n8";
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&vcc_d3_3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
osc5_clk: osc5-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
vcc_d1_8v: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "VCC_D1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
vcc_d3_3v: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "VCC_D3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_vddq_vin0: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "VCC_VDDQ_VIN0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
rx-internal-delay-ps = <1800>;
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&osc5_clk>;
clock-names = "du.0", "dclkin.0";
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
hdmi@39{
compatible = "adi,adv7511w";
#sound-dai-cells = <0>;
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&vcc_d1_8v>;
dvdd-supply = <&vcc_d1_8v>;
pvdd-supply = <&vcc_d1_8v>;
bgvdd-supply = <&vcc_d1_8v>;
dvdd-3v-supply = <&vcc_d3_3v>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_d3_3v>;
vqmmc-supply = <&vcc_vddq_vin0>;
bus-width = <8>;
non-removable;
status = "okay";
};
&pfc {
avb_pins: avb0 {
groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
function = "avb0";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
mmc_pins: mmc_3_3v {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
power-source = <3300>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
cr7@40000 {
reg = <0x00040000 0x080000>;
read-only;
};
cert_header_sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
bl2@140000 {
reg = <0x00140000 0x040000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x460000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x0c0000>;
read-only;
};
uboot-env@700000 {
reg = <0x00700000 0x040000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
status = "okay";
};

42
arch/arm/dts/r8a77980-v3hsk-u-boot.dts Normal file
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@ -0,0 +1,42 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot for the Eagle board
*
* Copyright (C) 2019 Cogent Embedded, Inc.
*/
#include "r8a77980-v3hsk.dts"
#include "r8a77980-u-boot.dtsi"
/ {
aliases {
spi0 = &rpc;
};
};
&rpc {
num-cs = <1>;
status = "okay";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
flash0: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
reg = <0>;
status = "okay";
};
};
&i2c0 {
cpld {
compatible = "renesas,v3hsk-cpld";
reg = <0x70>;
u-boot,i2c-offset-len = <2>;
};
};

292
arch/arm/dts/r8a77980-v3hsk.dts Normal file
View file

@ -0,0 +1,292 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the V3H Starter Kit board
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
*/
/dts-v1/;
#include "r8a77980.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas V3H Starter Kit board";
compatible = "renesas,v3hsk", "renesas,r8a77980";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
serial0 = &scif0;
ethernet0 = &gether;
};
chosen {
stdout-path = "serial0:115200n8";
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&vcc3v3_d5>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0 0x48000000 0 0x78000000>;
};
osc1_clk: osc1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
vcc1v8_d4: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "VCC1V8_D4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
vcc3v3_d5: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "VCC3V3_D5";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&osc1_clk>;
clock-names = "du.0", "dclkin.0";
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&gether {
pinctrl-0 = <&gether_pins>;
pinctrl-names = "default";
phy-mode = "rgmii";
phy-handle = <&phy0>;
renesas,no-ether-link;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupt-parent = <&gpio4>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
};
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
hdmi@39 {
compatible = "adi,adv7511w";
#sound-dai-cells = <0>;
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&vcc1v8_d4>;
dvdd-supply = <&vcc1v8_d4>;
pvdd-supply = <&vcc1v8_d4>;
bgvdd-supply = <&vcc1v8_d4>;
dvdd-3v-supply = <&vcc3v3_d5>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&pfc {
gether_pins: gether {
groups = "gether_mdio_a", "gether_rgmii",
"gether_txcrefclk", "gether_txcrefclk_mega";
function = "gether";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_b";
function = "scif_clk";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
cr7@40000 {
reg = <0x00040000 0x080000>;
read-only;
};
cert_header_sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
bl2@140000 {
reg = <0x00140000 0x040000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x460000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x0c0000>;
read-only;
};
uboot-env@700000 {
reg = <0x00700000 0x040000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};

12
arch/arm/mach-rmobile/Kconfig.rcar3
View file

@ -99,6 +99,11 @@ config TARGET_CONDOR
help
Support for Renesas R-Car Gen3 Condor platform
config TARGET_V3HSK
bool "V3HSK board"
help
Support for Renesas R-Car Gen3 V3HSK platform
config TARGET_DRAAK
bool "Draak board"
imply R8A77995
@ -111,6 +116,11 @@ config TARGET_EAGLE
help
Support for Renesas R-Car Gen3 Eagle platform
config TARGET_V3MSK
bool "V3MSK board"
help
Support for Renesas R-Car Gen3 V3MSK platform
config TARGET_EBISU
bool "Ebisu board"
imply R8A77990
@ -166,6 +176,8 @@ source "board/renesas/eagle/Kconfig"
source "board/renesas/ebisu/Kconfig"
source "board/renesas/salvator-x/Kconfig"
source "board/renesas/ulcb/Kconfig"
source "board/renesas/v3hsk/Kconfig"
source "board/renesas/v3msk/Kconfig"
source "board/beacon/beacon-rzg2m/Kconfig"
source "board/hoperun/hihope-rzg2/Kconfig"
source "board/silinux/ek874/Kconfig"

2
board/renesas/condor/Makefile
View file

@ -9,5 +9,5 @@
ifdef CONFIG_SPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := condor.o ../rcar-common/common.o
obj-y := ../rcar-common/common.o
endif

47
board/renesas/condor/condor.c
View file

@ -1,47 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* board/renesas/condor/condor.c
* This file is Condor board support.
*
* Copyright (C) 2019 Marek Vasut <marek.vasut+renesas@gmail.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <hang.h>
#include <init.h>
#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
return 0;
}
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
#define RST_RSTOUTCR (RST_BASE + 0x58)
#define RST_CA57_CODE 0xA5A5000F
#define RST_CA53_CODE 0x5A5A000F
void reset_cpu(void)
{
unsigned long midr, cputype;
asm volatile("mrs %0, midr_el1" : "=r" (midr));
cputype = (midr >> 4) & 0xfff;
if (cputype == 0xd03)
writel(RST_CA53_CODE, RST_CA53RESCNT);
else if (cputype == 0xd07)
writel(RST_CA57_CODE, RST_CA57RESCNT);
else
hang();
}

9
board/renesas/draak/draak.c
View file

@ -67,12 +67,3 @@ int board_init(void)
return 0;
}
#define RST_BASE 0xE6160000
#define RST_CA53RESCNT (RST_BASE + 0x44)
#define RST_CA53_CODE 0x5A5A000F
void reset_cpu(void)
{
writel(RST_CA53_CODE, RST_CA53RESCNT);
}

2
board/renesas/eagle/Kconfig
View file

@ -10,6 +10,6 @@ config SYS_VENDOR
default "renesas"
config SYS_CONFIG_NAME
default "eagle"
default "rcar-gen3-common"
endif

2
board/renesas/eagle/Makefile
View file

@ -9,5 +9,5 @@
ifdef CONFIG_SPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := eagle.o ../rcar-common/common.o
obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o
endif

92
board/renesas/eagle/eagle.c
View file

@ -1,92 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* board/renesas/eagle/eagle.c
* This file is Eagle board support.
*
* Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
*/
#include <common.h>
#include <clock_legacy.h>
#include <cpu_func.h>
#include <hang.h>
#include <init.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/sh_sdhi.h>
#include <i2c.h>
#include <mmc.h>
DECLARE_GLOBAL_DATA_PTR;
#define CPGWPR 0xE6150900
#define CPGWPCR 0xE6150904
/* PLL */
#define PLL0CR 0xE61500D8
#define PLL0_STC_MASK 0x7F000000
#define PLL0_STC_OFFSET 24
#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
u32 stc;
/* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 0.8GHz */
stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
}
int board_early_init_f(void)
{
/* Unlock CPG access */
writel(0xA5A5FFFF, CPGWPR);
writel(0x5A5A0000, CPGWPCR);
return 0;
}
int board_init(void)
{
return 0;
}
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
#define RST_RSTOUTCR (RST_BASE + 0x58)
#define RST_CA57_CODE 0xA5A5000F
#define RST_CA53_CODE 0x5A5A000F
void reset_cpu(void)
{
unsigned long midr, cputype;
asm volatile("mrs %0, midr_el1" : "=r" (midr));
cputype = (midr >> 4) & 0xfff;
if (cputype == 0xd03)
writel(RST_CA53_CODE, RST_CA53RESCNT);
else if (cputype == 0xd07)
writel(RST_CA57_CODE, RST_CA57RESCNT);
else
hang();
}

2
board/renesas/ebisu/Makefile
View file

@ -9,5 +9,5 @@
ifdef CONFIG_SPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := ebisu.o ../rcar-common/common.o
obj-y := ../rcar-common/common.o
endif

45
board/renesas/ebisu/ebisu.c
View file

@ -1,45 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* board/renesas/ebisu/ebisu.c
* This file is Ebisu board support.
*
* Copyright (C) 2018 Marek Vasut <marek.vasut+renesas@gmail.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <hang.h>
#include <init.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/sh_sdhi.h>
#include <i2c.h>
#include <mmc.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
return 0;
}
#define RST_BASE 0xE6160000
#define RST_CA53RESCNT (RST_BASE + 0x44)
#define RST_CA53_CODE 0x5A5A000F
void reset_cpu(void)
{
writel(RST_CA53_CODE, RST_CA53RESCNT);
}

7
board/renesas/falcon/falcon.c
View file

@ -84,8 +84,6 @@ int board_early_init_f(void)
}
#define RST_BASE 0xE6160000 /* Domain0 */
#define RST_SRESCR0 (RST_BASE + 0x18)
#define RST_SPRES 0x5AA58000
#define RST_WDTRSTCR (RST_BASE + 0x10)
#define RST_RWDT 0xA55A8002
@ -103,8 +101,3 @@ int board_init(void)
return 0;
}
void reset_cpu(void)
{
writel(RST_SPRES, RST_SRESCR0);
}

42
board/renesas/rcar-common/common.c
View file

@ -10,8 +10,10 @@
#include <common.h>
#include <dm.h>
#include <fdt_support.h>
#include <hang.h>
#include <init.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/uclass-internal.h>
#include <asm/arch/rmobile.h>
#include <linux/libfdt.h>
@ -47,6 +49,46 @@ int dram_init_banksize(void)
return 0;
}
int __weak board_init(void)
{
return 0;
}
#if defined(CONFIG_RCAR_GEN3)
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
#define RST_RSTOUTCR (RST_BASE + 0x58)
#define RST_CA57_CODE 0xA5A5000F
#define RST_CA53_CODE 0x5A5A000F
void __weak reset_cpu(void)
{
unsigned long midr, cputype;
asm volatile("mrs %0, midr_el1" : "=r" (midr));
cputype = (midr >> 4) & 0xfff;
if (cputype == 0xd03)
writel(RST_CA53_CODE, RST_CA53RESCNT);
else if (cputype == 0xd07)
writel(RST_CA57_CODE, RST_CA57RESCNT);
else
hang();
}
#elif defined(CONFIG_RCAR_GEN4)
#define RST_BASE 0xE6160000 /* Domain0 */
#define RST_SRESCR0 (RST_BASE + 0x18)
#define RST_SPRES 0x5AA58000
void __weak reset_cpu(void)
{
writel(RST_SPRES, RST_SRESCR0);
}
#else
#error Neither CONFIG_RCAR_GEN3 nor CONFIG_RCAR_GEN4 are set
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
static int is_mem_overlap(void *blob, int first_mem_node, int curr_mem_node)
{

41
board/renesas/rcar-common/v3-common.c Normal file
View file

@ -0,0 +1,41 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017-2023 Marek Vasut <marek.vasut+renesas@mailbox.org>
*/
#include <common.h>
#include <clock_legacy.h>
#include <asm/io.h>
#define CPGWPR 0xE6150900
#define CPGWPCR 0xE6150904
/* PLL */
#define PLL0CR 0xE61500D8
#define PLL0_STC_MASK 0x7F000000
#define PLL0_STC_OFFSET 24
#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
u32 stc;
/* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 0.8GHz */
stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
}
int board_early_init_f(void)
{
/* Unlock CPG access */
writel(0xA5A5FFFF, CPGWPR);
writel(0x5A5A0000, CPGWPCR);
return 0;
}

13
board/renesas/salvator-x/salvator-x.c
View file

@ -67,21 +67,12 @@ int board_init(void)
return 0;
}
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
#define RST_RSTOUTCR (RST_BASE + 0x58)
#define RST_CODE 0xA5A5000F
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
void reset_cpu(void)
{
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
#else
/* only CA57 ? */
writel(RST_CODE, RST_CA57RESCNT);
#endif
}
#endif
#ifdef CONFIG_MULTI_DTB_FIT
int board_fit_config_name_match(const char *name)

5
board/renesas/spider/spider.c
View file

@ -65,8 +65,3 @@ int board_init(void)
return 0;
}
void reset_cpu(void)
{
writel(RST_SPRES, RST_SRESCR0);
}

15
board/renesas/v3hsk/Kconfig Normal file
View file

@ -0,0 +1,15 @@
if TARGET_V3HSK
config SYS_SOC
default "rmobile"
config SYS_BOARD
default "v3hsk"
config SYS_VENDOR
default "renesas"
config SYS_CONFIG_NAME
default "v3hsk"
endif

15
board/renesas/v3hsk/Makefile Normal file
View file

@ -0,0 +1,15 @@
#
# board/renesas/v3hsk/Makefile
#
# Copyright (C) 2019 Renesas Electronics Corporation
# Copyright (C) 2019 Cogent Embedded, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o
obj-$(CONFIG_SYSRESET) += cpld.o
endif

180
board/renesas/v3hsk/cpld.c Normal file
View file

@ -0,0 +1,180 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* V3HSK board CPLD access support
*
* Copyright (C) 2019 Renesas Electronics Corporation
* Copyright (C) 2019 Cogent Embedded, Inc.
*
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <i2c.h>
#include <linux/err.h>
#include <sysreset.h>
#include <command.h>
#define CPLD_ADDR_PRODUCT_0 0x0000 /* R */
#define CPLD_ADDR_PRODUCT_1 0x0001 /* R */
#define CPLD_ADDR_PRODUCT_2 0x0002 /* R */
#define CPLD_ADDR_PRODUCT_3 0x0003 /* R */
#define CPLD_ADDR_CPLD_VERSION_D 0x0004 /* R */
#define CPLD_ADDR_CPLD_VERSION_M 0x0005 /* R */
#define CPLD_ADDR_CPLD_VERSION_Y_0 0x0006 /* R */
#define CPLD_ADDR_CPLD_VERSION_Y_1 0x0007 /* R */
#define CPLD_ADDR_MODE_SET_0 0x0008 /* R */
#define CPLD_ADDR_MODE_SET_1 0x0009 /* R */
#define CPLD_ADDR_MODE_SET_2 0x000A /* R */
#define CPLD_ADDR_MODE_SET_3 0x000B /* R */
#define CPLD_ADDR_MODE_SET_4 0x000C /* R */
#define CPLD_ADDR_MODE_LAST_0 0x0018 /* R */
#define CPLD_ADDR_MODE_LAST_1 0x0019 /* R */
#define CPLD_ADDR_MODE_LAST_2 0x001A /* R */
#define CPLD_ADDR_MODE_LAST_3 0x001B /* R */
#define CPLD_ADDR_MODE_LAST_4 0x001C /* R */
#define CPLD_ADDR_DIPSW4 0x0020 /* R */
#define CPLD_ADDR_DIPSW5 0x0021 /* R */
#define CPLD_ADDR_RESET 0x0024 /* R/W */
#define CPLD_ADDR_POWER_CFG 0x0025 /* R/W */
#define CPLD_ADDR_PERI_CFG_0 0x0030 /* R/W */
#define CPLD_ADDR_PERI_CFG_1 0x0031 /* R/W */
#define CPLD_ADDR_PERI_CFG_2 0x0032 /* R/W */
#define CPLD_ADDR_PERI_CFG_3 0x0033 /* R/W */
#define CPLD_ADDR_LEDS 0x0034 /* R/W */
#define CPLD_ADDR_LEDS_CFG 0x0035 /* R/W */
#define CPLD_ADDR_UART_CFG 0x0036 /* R/W */
#define CPLD_ADDR_UART_STATUS 0x0037 /* R */
#define CPLD_ADDR_PCB_VERSION_0 0x1000 /* R */
#define CPLD_ADDR_PCB_VERSION_1 0x1001 /* R */
#define CPLD_ADDR_SOC_VERSION_0 0x1002 /* R */
#define CPLD_ADDR_SOC_VERSION_1 0x1003 /* R */
#define CPLD_ADDR_PCB_SN_0 0x1004 /* R */
#define CPLD_ADDR_PCB_SN_1 0x1005 /* R */
static u16 cpld_read(struct udevice *dev, u16 addr)
{
u8 data[2];
/* Random flash reads require 2 reads: first read is unreliable */
if (addr >= CPLD_ADDR_PCB_VERSION_0)
dm_i2c_read(dev, addr, data, 2);
/* Only the second byte read is valid */
dm_i2c_read(dev, addr, data, 2);
return data[1];
}
static void cpld_write(struct udevice *dev, u16 addr, u8 data)
{
dm_i2c_write(dev, addr, &data, 1);
}
static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
{
struct udevice *dev;
u16 addr, val;
int ret;
ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
DM_DRIVER_GET(sysreset_renesas_v3hsk),
&dev);
if (ret)
return ret;
if (argc == 2 && strcmp(argv[1], "info") == 0) {
printf("Product: 0x%08x\n",
(cpld_read(dev, CPLD_ADDR_PRODUCT_3) << 24) |
(cpld_read(dev, CPLD_ADDR_PRODUCT_2) << 16) |
(cpld_read(dev, CPLD_ADDR_PRODUCT_1) << 8) |
cpld_read(dev, CPLD_ADDR_PRODUCT_0));
printf("CPLD version: 0x%08x\n",
(cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y_1) << 24) |
(cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y_0) << 16) |
(cpld_read(dev, CPLD_ADDR_CPLD_VERSION_M) << 8) |
cpld_read(dev, CPLD_ADDR_CPLD_VERSION_D));
printf("Mode setting (MD0..26): 0x%08x\n",
(cpld_read(dev, CPLD_ADDR_MODE_LAST_3) << 24) |
(cpld_read(dev, CPLD_ADDR_MODE_LAST_2) << 16) |
(cpld_read(dev, CPLD_ADDR_MODE_LAST_1) << 8) |
cpld_read(dev, CPLD_ADDR_MODE_LAST_0));
printf("DIPSW (SW4, SW5): 0x%02x, 0x%x\n",
cpld_read(dev, CPLD_ADDR_DIPSW4) ^ 0xff,
(cpld_read(dev, CPLD_ADDR_DIPSW5) ^ 0xff) & 0xf);
printf("Power config: 0x%08x\n",
cpld_read(dev, CPLD_ADDR_POWER_CFG));
printf("Periferals config: 0x%08x\n",
(cpld_read(dev, CPLD_ADDR_PERI_CFG_3) << 24) |
(cpld_read(dev, CPLD_ADDR_PERI_CFG_2) << 16) |
(cpld_read(dev, CPLD_ADDR_PERI_CFG_1) << 8) |
cpld_read(dev, CPLD_ADDR_PERI_CFG_0));
printf("PCB version: %d.%d\n",
cpld_read(dev, CPLD_ADDR_PCB_VERSION_1),
cpld_read(dev, CPLD_ADDR_PCB_VERSION_0));
printf("SOC version: %d.%d\n",
cpld_read(dev, CPLD_ADDR_SOC_VERSION_1),
cpld_read(dev, CPLD_ADDR_SOC_VERSION_0));
printf("PCB S/N: %d\n",
(cpld_read(dev, CPLD_ADDR_PCB_SN_1) << 8) |
cpld_read(dev, CPLD_ADDR_PCB_SN_0));
return 0;
}
if (argc < 3)
return CMD_RET_USAGE;
addr = simple_strtoul(argv[2], NULL, 16);
if (!(addr >= CPLD_ADDR_PRODUCT_0 && addr <= CPLD_ADDR_UART_STATUS)) {
printf("cpld invalid addr\n");
return CMD_RET_USAGE;
}
if (argc == 3 && strcmp(argv[1], "read") == 0) {
printf("0x%x\n", cpld_read(dev, addr));
} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
val = simple_strtoul(argv[3], NULL, 16);
cpld_write(dev, addr, val);
}
return 0;
}
U_BOOT_CMD(cpld, 4, 1, do_cpld,
"CPLD access",
"info\n"
"cpld read addr\n"
"cpld write addr val\n"
);
static int renesas_v3hsk_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
cpld_write(dev, CPLD_ADDR_RESET, 1);
return -EINPROGRESS;
}
static int renesas_v3hsk_sysreset_probe(struct udevice *dev)
{
if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
return -EPROTONOSUPPORT;
return 0;
}
static struct sysreset_ops renesas_v3hsk_sysreset = {
.request = renesas_v3hsk_sysreset_request,
};
static const struct udevice_id renesas_v3hsk_sysreset_ids[] = {
{ .compatible = "renesas,v3hsk-cpld" },
{ /* sentinel */ }
};
U_BOOT_DRIVER(sysreset_renesas_v3hsk) = {
.name = "renesas_v3hsk_sysreset",
.id = UCLASS_SYSRESET,
.ops = &renesas_v3hsk_sysreset,
.probe = renesas_v3hsk_sysreset_probe,
.of_match = renesas_v3hsk_sysreset_ids,
};

15
board/renesas/v3msk/Kconfig Normal file
View file

@ -0,0 +1,15 @@
if TARGET_V3MSK
config SYS_SOC
default "rmobile"
config SYS_BOARD
default "v3msk"
config SYS_VENDOR
default "renesas"
config SYS_CONFIG_NAME
default "rcar-gen3-common"
endif

6
board/renesas/v3msk/MAINTAINERS Normal file
View file

@ -0,0 +1,6 @@
V3MSK BOARD
M: Cogent Embedded, Inc. <source@cogentembedded.com>
S: Maintained
F: board/renesas/v3msk/
F: include/configs/v3msk.h
F: configs/r8a77970_v3msk_defconfig

15
board/renesas/v3msk/Makefile Normal file
View file

@ -0,0 +1,15 @@
#
# board/renesas/v3msk/Makefile
#
# Copyright (C) 2019 Renesas Electronics Corporation
# Copyright (C) 2019 Cogent Embedded, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o
obj-$(CONFIG_SYSRESET) += cpld.o
endif

368
board/renesas/v3msk/cpld.c Normal file
View file

@ -0,0 +1,368 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* V3MSK board CPLD access support
*
* Copyright (C) 2019 Renesas Electronics Corporation
* Copyright (C) 2019 Cogent Embedded, Inc.
*
*/
#include <common.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <dm.h>
#include <errno.h>
#include <linux/err.h>
#include <sysreset.h>
#include <linux/delay.h>
#include <command.h>
#define CPLD_ADDR_PRODUCT_L 0x000 /* R */
#define CPLD_ADDR_PRODUCT_H 0x001 /* R */
#define CPLD_ADDR_CPLD_VERSION_D 0x002 /* R */
#define CPLD_ADDR_CPLD_VERSION_Y 0x003 /* R */
#define CPLD_ADDR_MODE_SET_L 0x004 /* R/W */
#define CPLD_ADDR_MODE_SET_H 0x005 /* R/W */
#define CPLD_ADDR_MODE_APPLIED_L 0x006 /* R */
#define CPLD_ADDR_MODE_APPLIED_H 0x007 /* R */
#define CPLD_ADDR_DIPSW 0x008 /* R */
#define CPLD_ADDR_RESET 0x00A /* R/W */
#define CPLD_ADDR_POWER_CFG 0x00B /* R/W */
#define CPLD_ADDR_PERI_CFG1 0x00C /* R/W */
#define CPLD_ADDR_PERI_CFG2 0x00D /* R/W */
#define CPLD_ADDR_LEDS 0x00E /* R/W */
#define CPLD_ADDR_PCB_VERSION 0x300 /* R */
#define CPLD_ADDR_SOC_VERSION 0x301 /* R */
#define CPLD_ADDR_PCB_SN_L 0x302 /* R */
#define CPLD_ADDR_PCB_SN_H 0x303 /* R */
#define MDIO_DELAY 10 /* microseconds */
#define CPLD_MAX_GPIOS 2
struct renesas_v3msk_sysreset_priv {
struct gpio_desc miso;
struct gpio_desc mosi;
struct gpio_desc mdc;
struct gpio_desc enablez;
/*
* V3MSK Videobox Mini board has CANFD PHY connected
* we must shutdown this chip to use bb pins
*/
struct gpio_desc gpios[CPLD_MAX_GPIOS];
};
static void mdio_bb_active_mdio(struct renesas_v3msk_sysreset_priv *priv)
{
dm_gpio_set_dir_flags(&priv->mosi, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
}
static void mdio_bb_tristate_mdio(struct renesas_v3msk_sysreset_priv *priv)
{
dm_gpio_set_dir_flags(&priv->mosi, GPIOD_IS_IN);
}
static void mdio_bb_set_mdio(struct renesas_v3msk_sysreset_priv *priv, int val)
{
dm_gpio_set_value(&priv->mosi, val);
}
static int mdio_bb_get_mdio(struct renesas_v3msk_sysreset_priv *priv)
{
return dm_gpio_get_value(&priv->miso);
}
static void mdio_bb_set_mdc(struct renesas_v3msk_sysreset_priv *priv, int val)
{
dm_gpio_set_value(&priv->mdc, val);
}
static void mdio_bb_delay(void)
{
udelay(MDIO_DELAY);
}
/* Send the preamble, address, and register (common to read and write) */
static void mdio_bb_pre(struct renesas_v3msk_sysreset_priv *priv,
u8 op, u8 addr, u8 reg)
{
int i;
/* 32-bit preamble */
mdio_bb_active_mdio(priv);
mdio_bb_set_mdio(priv, 1);
for (i = 0; i < 32; i++) {
mdio_bb_set_mdc(priv, 0);
mdio_bb_delay();
mdio_bb_set_mdc(priv, 1);
mdio_bb_delay();
}
/* send the ST (2-bits of '01') */
mdio_bb_set_mdio(priv, 0);
mdio_bb_set_mdc(priv, 0);
mdio_bb_delay();
mdio_bb_set_mdc(priv, 1);
mdio_bb_delay();
mdio_bb_set_mdio(priv, 1);
mdio_bb_set_mdc(priv, 0);
mdio_bb_delay();
mdio_bb_set_mdc(priv, 1);
mdio_bb_delay();
/* send the OP (2-bits of Opcode: '10'-read, '01'-write) */
mdio_bb_set_mdio(priv, op >> 1);
mdio_bb_set_mdc(priv, 0);
mdio_bb_delay();
mdio_bb_set_mdc(priv, 1);
mdio_bb_delay();
mdio_bb_set_mdio(priv, op & 1);
mdio_bb_set_mdc(priv, 0);
mdio_bb_delay();
mdio_bb_set_mdc(priv, 1);
mdio_bb_delay();
/* send the PA5 (5-bits of PHY address) */
for (i = 0; i < 5; i++) {
mdio_bb_set_mdio(priv, addr & 0x10); /* MSB first */
mdio_bb_set_mdc(priv, 0);
mdio_bb_delay();
mdio_bb_set_mdc(priv, 1);
mdio_bb_delay();
addr <<= 1;
}
/* send the RA5 (5-bits of register address) */
for (i = 0; i < 5; i++) {
mdio_bb_set_mdio(priv, reg & 0x10); /* MSB first */
mdio_bb_set_mdc(priv, 0);
mdio_bb_delay();
mdio_bb_set_mdc(priv, 1);
mdio_bb_delay();
reg <<= 1;
}
}
static int mdio_bb_read(struct renesas_v3msk_sysreset_priv *priv,
u8 addr, u8 reg)
{
int i;
u16 data = 0;
mdio_bb_pre(priv, 2, addr, reg);
/* tri-state MDIO */
mdio_bb_tristate_mdio(priv);
/* read TA (2-bits of turn-around, last bit must be '0') */
mdio_bb_set_mdc(priv, 0);
mdio_bb_delay();
mdio_bb_set_mdc(priv, 1);
mdio_bb_delay();
mdio_bb_set_mdc(priv, 0);
mdio_bb_delay();
mdio_bb_set_mdc(priv, 1);
mdio_bb_delay();
/* check the turnaround bit: the PHY should drive line to zero */
if (mdio_bb_get_mdio(priv) != 0) {
printf("PHY didn't drive TA low\n");
for (i = 0; i < 32; i++) {
mdio_bb_set_mdc(priv, 0);
mdio_bb_delay();
mdio_bb_set_mdc(priv, 1);
mdio_bb_delay();
}
/* There is no PHY, set value to 0xFFFF */
return 0xFFFF;
}
mdio_bb_set_mdc(priv, 0);
mdio_bb_delay();
/* read 16-bits of data */
for (i = 0; i < 16; i++) {
mdio_bb_set_mdc(priv, 1);
mdio_bb_delay();
data <<= 1;
data |= mdio_bb_get_mdio(priv);
mdio_bb_set_mdc(priv, 0);
mdio_bb_delay();
}
mdio_bb_set_mdc(priv, 1);
mdio_bb_delay();
mdio_bb_set_mdc(priv, 0);
mdio_bb_delay();
mdio_bb_set_mdc(priv, 1);
mdio_bb_delay();
debug("cpld_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, data);
return data;
}
static void mdio_bb_write(struct renesas_v3msk_sysreset_priv *priv,
u8 addr, u8 reg, u16 val)
{
int i;
mdio_bb_pre(priv, 1, addr, reg);
/* send the TA (2-bits of turn-around '10') */
mdio_bb_set_mdio(priv, 1);
mdio_bb_set_mdc(priv, 0);
mdio_bb_delay();
mdio_bb_set_mdc(priv, 1);
mdio_bb_delay();
mdio_bb_set_mdio(priv, 0);
mdio_bb_set_mdc(priv, 0);
mdio_bb_delay();
mdio_bb_set_mdc(priv, 1);
mdio_bb_delay();
/* write 16-bits of data */
for (i = 0; i < 16; i++) {
mdio_bb_set_mdio(priv, val & 0x8000); /* MSB first */
mdio_bb_set_mdc(priv, 0);
mdio_bb_delay();
mdio_bb_set_mdc(priv, 1);
mdio_bb_delay();
val <<= 1;
}
/* tri-state MDIO */
mdio_bb_tristate_mdio(priv);
mdio_bb_set_mdc(priv, 0);
mdio_bb_delay();
mdio_bb_set_mdc(priv, 1);
mdio_bb_delay();
}
static u16 cpld_read(struct udevice *dev, u16 addr)
{
struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev);
/* random flash reads require 2 reads: first read is unreliable */
if (addr >= CPLD_ADDR_PCB_VERSION)
mdio_bb_read(priv, addr >> 5, addr & 0x1f);
return mdio_bb_read(priv, addr >> 5, addr & 0x1f);
}
static void cpld_write(struct udevice *dev, u16 addr, u16 data)
{
struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev);
mdio_bb_write(priv, addr >> 5, addr & 0x1f, data);
}
static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
{
struct udevice *dev;
u16 addr, val;
int ret;
ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
DM_DRIVER_GET(sysreset_renesas_v3msk),
&dev);
if (ret)
return ret;
if (argc == 2 && strcmp(argv[1], "info") == 0) {
printf("Product: 0x%08x\n",
(cpld_read(dev, CPLD_ADDR_PRODUCT_H) << 16) |
cpld_read(dev, CPLD_ADDR_PRODUCT_L));
printf("CPLD version: 0x%08x\n",
(cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y) << 16) |
cpld_read(dev, CPLD_ADDR_CPLD_VERSION_D));
printf("Mode setting (MD0..26): 0x%08x\n",
(cpld_read(dev, CPLD_ADDR_MODE_APPLIED_H) << 16) |
cpld_read(dev, CPLD_ADDR_MODE_APPLIED_L));
printf("DIPSW (SW4, SW5): 0x%02x, 0x%x\n",
(cpld_read(dev, CPLD_ADDR_DIPSW) & 0xff) ^ 0xff,
(cpld_read(dev, CPLD_ADDR_DIPSW) >> 8) ^ 0xf);
printf("Power config: 0x%08x\n",
cpld_read(dev, CPLD_ADDR_POWER_CFG));
printf("Periferals config: 0x%08x\n",
(cpld_read(dev, CPLD_ADDR_PERI_CFG2) << 16) |
cpld_read(dev, CPLD_ADDR_PERI_CFG1));
printf("PCB version: %d.%d\n",
cpld_read(dev, CPLD_ADDR_PCB_VERSION) >> 8,
cpld_read(dev, CPLD_ADDR_PCB_VERSION) & 0xff);
printf("SOC version: %d.%d\n",
cpld_read(dev, CPLD_ADDR_SOC_VERSION) >> 8,
cpld_read(dev, CPLD_ADDR_SOC_VERSION) & 0xff);
printf("PCB S/N: %d\n",
(cpld_read(dev, CPLD_ADDR_PCB_SN_H) << 16) |
cpld_read(dev, CPLD_ADDR_PCB_SN_L));
return 0;
}
if (argc < 3)
return CMD_RET_USAGE;
addr = simple_strtoul(argv[2], NULL, 16);
if (!(addr >= CPLD_ADDR_PRODUCT_L && addr <= CPLD_ADDR_LEDS)) {
printf("cpld invalid addr\n");
return CMD_RET_USAGE;
}
if (argc == 3 && strcmp(argv[1], "read") == 0) {
printf("0x%x\n", cpld_read(dev, addr));
} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
val = simple_strtoul(argv[3], NULL, 16);
cpld_write(dev, addr, val);
}
return 0;
}
U_BOOT_CMD(cpld, 4, 1, do_cpld,
"CPLD access",
"info\n"
"cpld read addr\n"
"cpld write addr val\n"
);
static int renesas_v3msk_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
cpld_write(dev, CPLD_ADDR_RESET, 1);
return -EINPROGRESS;
}
static int renesas_v3msk_sysreset_probe(struct udevice *dev)
{
struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev);
if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso,
GPIOD_IS_IN))
return -EINVAL;
if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi,
GPIOD_IS_OUT))
return -EINVAL;
if (gpio_request_by_name(dev, "gpio-mdc", 0, &priv->mdc,
GPIOD_IS_OUT))
return -EINVAL;
if (gpio_request_by_name(dev, "gpio-enablez", 0, &priv->enablez,
GPIOD_IS_OUT))
return -EINVAL;
/* V3MSK Videobox Mini board has CANFD PHY connected
* we must shutdown this chip to use bb pins
*/
gpio_request_list_by_name(dev, "gpios", priv->gpios, CPLD_MAX_GPIOS,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
return 0;
}
static struct sysreset_ops renesas_v3msk_sysreset = {
.request = renesas_v3msk_sysreset_request,
};
static const struct udevice_id renesas_v3msk_sysreset_ids[] = {
{ .compatible = "renesas,v3msk-cpld" },
{ /* sentinel */ }
};
U_BOOT_DRIVER(sysreset_renesas_v3msk) = {
.name = "renesas_v3msk_sysreset",
.id = UCLASS_SYSRESET,
.ops = &renesas_v3msk_sysreset,
.probe = renesas_v3msk_sysreset_probe,
.of_match = renesas_v3msk_sysreset_ids,
.priv_auto = sizeof(struct renesas_v3msk_sysreset_priv),
};

5
board/renesas/whitehawk/whitehawk.c
View file

@ -65,8 +65,3 @@ int board_init(void)
return 0;
}
void reset_cpu(void)
{
writel(RST_SPRES, RST_SRESCR0);
}

87
configs/r8a77970_v3msk_defconfig Normal file
View file

@ -0,0 +1,87 @@
CONFIG_ARM=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x700000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77970-v3msk-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_R8A77970=y
CONFIG_TARGET_V3MSK=y
CONFIG_SPL_STACK=0xe6304000
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_LTO=y
CONFIG_REMAKE_ELF=y
CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_DEFAULT_FDT_FILE="r8a77970-v3msk.dtb"
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0xe631f000
CONFIG_SPL_BSS_MAX_SIZE=0x1000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DFU=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_OF_DTB_PROPS_REMOVE=y
CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_RENESAS_RAVB=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_RENESAS_RPC_SPI=y
CONFIG_SYSRESET=y

83
configs/r8a77980_v3hsk_defconfig Normal file
View file

@ -0,0 +1,83 @@
CONFIG_ARM=y
CONFIG_COUNTER_FREQUENCY=16666666
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x700000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77980-v3hsk-u-boot"
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_R8A77980=y
CONFIG_TARGET_V3HSK=y
CONFIG_SPL_STACK=0xe6304000
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_LTO=y
CONFIG_REMAKE_ELF=y
CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_DEFAULT_FDT_FILE="r8a77980-v3hsk.dtb"
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_SYS_MALLOC_BOOTPARAMS=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0xe631f000
CONFIG_SPL_BSS_MAX_SIZE=0x1000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_PBSIZE=2068
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_OF_DTB_PROPS_REMOVE=y
CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_SH_ETHER=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_RENESAS_RPC_SPI=y
CONFIG_SYSRESET=y

1
doc/README.rmobile
View file

@ -35,6 +35,7 @@ Currently the following boards are supported:
| R8A77965 M3-N | Renesas Electronics ULCB | r8a77965_ulcb
|---------------+----------------------------------------+-------------------
| R8A77970 V3M | Renesas Electronics Eagle | r8a77970_eagle_defconfig
| R8A77970 V3M | Renesas Electronics V3MSK | r8a77970_v3msk_defconfig
|---------------+----------------------------------------+-------------------
| R8A77995 D3 | Renesas Electronics Draak | r8a77995_draak_defconfig
'===============+========================================+===================

19
include/configs/eagle.h
View file

@ -1,19 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* include/configs/eagle.h
* This file is Eagle board configuration.
*
* Copyright (C) 2015 Renesas Electronics Corporation
*/
#ifndef __EAGLE_H
#define __EAGLE_H
#include "rcar-gen3-common.h"
/* Environment compatibility */
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#endif /* __EAGLE_H */

28
include/configs/v3hsk.h Normal file
View file

@ -0,0 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* include/configs/v3hsk.h
* This file is V3HSK board configuration.
*
* Copyright (C) 2019 Renesas Electronics Corporation
* Copyright (C) 2019 Cogent Embedded, Inc.
*/
#ifndef __V3HSK_H
#define __V3HSK_H
#include "rcar-gen3-common.h"
/* Environment compatibility */
/* SH Ether */
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x0
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID
#define CFG_SH_ETHER_CACHE_WRITEBACK
#define CFG_SH_ETHER_CACHE_INVALIDATE
#define CFG_SH_ETHER_ALIGNE_SIZE 64
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#endif /* __V3HSK_H */