mirror of
https://github.com/AsahiLinux/u-boot
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7576ab2fac
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. It is hardware compatible with classic MicroBlaze processor. The patch contains initial wiring and configuration for initial HW design with memory, cpu, interrupt controller, timers and uartlite console (interrupt controller is listed but U-Boot is not using it). Provided DT is just describing one configuration and should be taken only as example. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
106 lines
2.1 KiB
Text
106 lines
2.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for AMD MicroBlaze V
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*
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* (C) Copyright 2023, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "AMD MicroBlaze V 32bit";
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compatible = "amd,mbv";
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <102000000>;
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cpu_0: cpu@0 {
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compatible = "amd,mbv32", "riscv";
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device_type = "cpu";
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reg = <0>;
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riscv,isa = "rv32imafdc";
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i-cache-size = <32768>;
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d-cache-size = <32768>;
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clock-frequency = <102000000>;
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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};
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aliases {
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serial0 = &uart0;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@20000000 {
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device_type = "memory";
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reg = <0x20000000 0x20000000>;
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};
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clk102: clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <102000000>;
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};
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axi: axi {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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bootph-all;
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axi_intc: interrupt-controller@41200000 {
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compatible = "xlnx,xps-intc-1.00.a";
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reg = <0x41200000 0x1000>;
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interrupt-controller;
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interrupt-parent = <&cpu0_intc>;
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#interrupt-cells = <2>;
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kind-of-intr = <0>;
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};
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xlnx_timer0: timer@41c00000 {
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compatible = "xlnx,xps-timer-1.00.a";
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reg = <0x41c00000 0x1000>;
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interrupt-parent = <&axi_intc>;
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interrupts = <1 2>;
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bootph-all;
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xlnx,one-timer-only = <0>;
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clock-names = "s_axi_aclk";
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clocks = <&clk102>;
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};
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xlnx_timer1: timer@41c20000 {
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compatible = "xlnx,xps-timer-1.00.a";
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reg = <0x41c20000 0x1000>;
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interrupt-parent = <&axi_intc>;
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interrupts = <0 2>;
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xlnx,one-timer-only = <0>;
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clock-names = "s_axi_aclk";
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clocks = <&clk102>;
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};
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uart0: serial@40600000 {
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compatible = "xlnx,xps-uartlite-1.00.a";
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reg = <0x40600000 0x1000>;
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interrupt-parent = <&axi_intc>;
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interrupts = <2 2>;
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bootph-all;
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clocks = <&clk102>;
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current-speed = <115200>;
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xlnx,data-bits = <8>;
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xlnx,use-parity = <0>;
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};
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};
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};
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