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https://github.com/AsahiLinux/u-boot
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Remove unused files
[1] arch/arm/include/asm/arch-at91/at91_shdwn.h The top9000 was the last board to use this header file. It was removed by commitd58a9451e7(ppc/arm: zap EMK boards). [2] board/matrix_vision/common/* Some Matrix Vision boards were dropped by commite7a565638a(powerpc: mpc83xx: remove board support for MERGERBOX and MVBLM7) and commitaf55e35d33(powerpc: mpc5xxx: remove board support for MVBC_P and MVSMR). Since then these files have been unused. [3] include/usb/omap1510_udc.h The omap5912osk was the last board to use this header file. It was removed by commit62d636aa2a(omap: remove omap5912osk board support). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-By: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Masahiro Yamada
Anatolij Gustschin
parent
2ed8c878eb
commit
9ea7f3a6d8
5 changed files with 0 additions and 338 deletions
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@ -1,35 +0,0 @@
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/*
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* Copyright (C) 2010
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* Reinhard Meyer, reinhard.meyer@emk-elektronik.de
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*
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* Shutdown Controller
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* Based on AT91SAM9XE datasheet
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef AT91_SHDWN_H
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#define AT91_SHDWN_H
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#ifndef __ASSEMBLY__
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struct at91_shdwn {
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u32 cr; /* Control Rer. WO */
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u32 mr; /* Mode Register RW 0x00000003 */
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u32 sr; /* Status Register RO 0x00000000 */
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};
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#endif /* __ASSEMBLY__ */
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#define AT91_SHDW_CR_KEY 0xa5000000
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#define AT91_SHDW_CR_SHDW 0x00000001
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#define AT91_SHDW_MR_RTTWKEN 0x00010000
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#define AT91_SHDW_MR_CPTWK0 0x000000f0
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#define AT91_SHDW_MR_WKMODE0H2L 0x00000002
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#define AT91_SHDW_MR_WKMODE0L2H 0x00000001
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#define AT91_SHDW_SR_RTTWK 0x00010000
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#define AT91_SHDW_SR_WAKEUP0 0x00000001
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#endif
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = mv_common.o
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@ -1,112 +0,0 @@
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/*
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* (C) Copyright 2008
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* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <environment.h>
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#include <fpga.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_ENV_IS_NOWHERE
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static char* entries_to_keep[] = {
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"serial#", "ethaddr", "eth1addr", "model_info", "sensor_cnt",
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"fpgadatasize", "ddr_size", "use_dhcp", "use_static_ipaddr",
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"static_ipaddr", "static_netmask", "static_gateway",
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"syslog", "watchdog", "netboot", "evo8serialnumber" };
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#define MV_MAX_ENV_ENTRY_LENGTH 64
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#define MV_KEEP_ENTRIES ARRAY_SIZE(entries_to_keep)
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void mv_reset_environment(void)
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{
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int i;
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char *s[MV_KEEP_ENTRIES];
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char entries[MV_KEEP_ENTRIES][MV_MAX_ENV_ENTRY_LENGTH];
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printf("\n*** RESET ENVIRONMENT ***\n");
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memset(entries, 0, MV_KEEP_ENTRIES * MV_MAX_ENV_ENTRY_LENGTH);
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for (i = 0; i < MV_KEEP_ENTRIES; i++) {
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s[i] = getenv(entries_to_keep[i]);
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if (s[i]) {
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printf("save '%s' : %s\n", entries_to_keep[i], s[i]);
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strncpy(entries[i], s[i], MV_MAX_ENV_ENTRY_LENGTH);
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}
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}
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gd->env_valid = 0;
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env_relocate();
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for (i = 0; i < MV_KEEP_ENTRIES; i++) {
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if (s[i]) {
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printf("restore '%s' : %s\n", entries_to_keep[i], s[i]);
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setenv(entries_to_keep[i], s[i]);
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}
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}
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saveenv();
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}
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#endif
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int mv_load_fpga(void)
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{
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int result;
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size_t data_size = 0;
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void *fpga_data = NULL;
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char *datastr = getenv("fpgadata");
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char *sizestr = getenv("fpgadatasize");
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if (getenv("skip_fpga")) {
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printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
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return -1;
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}
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printf("loading FPGA\n");
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if (datastr)
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fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
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if (sizestr)
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data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
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if (!data_size) {
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printf("fpgadatasize invalid -> FPGA _not_ loaded !\n");
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return -1;
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}
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result = fpga_load(0, fpga_data, data_size, BIT_FULL);
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if (!result)
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bootstage_mark(BOOTSTAGE_ID_START);
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return result;
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}
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u8 *dhcp_vendorex_prep(u8 *e)
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{
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char *ptr;
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/* DHCP vendor-class-identifier = 60 */
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if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
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*e++ = 60;
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*e++ = strlen(ptr);
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while (*ptr)
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*e++ = *ptr++;
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}
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/* DHCP_CLIENT_IDENTIFIER = 61 */
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if ((ptr = getenv("dhcp_client_id"))) {
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*e++ = 61;
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*e++ = strlen(ptr);
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while (*ptr)
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*e++ = *ptr++;
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}
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return e;
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}
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u8 *dhcp_vendorex_proc(u8 *popt)
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{
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return NULL;
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}
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@ -1,9 +0,0 @@
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/*
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* Copyright 2008 Matrix Vision GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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extern int mv_load_fpga(void);
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extern void mv_reset_environment(void);
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@ -1,174 +0,0 @@
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/*
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* (C) Copyright 2003
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* Gerry Hamel, geh@ti.com, Texas Instruments
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*
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* Based on
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* linux/drivers/usb/device/bi/omap.h
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* Register definitions for TI OMAP1510 USB bus interface driver
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*
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* Author: MontaVista Software, Inc.
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* source@mvista.com
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*
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* 2003 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef __USBDCORE_OMAP1510_H__
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#define __USBDCORE_OMAP1510_H__
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/*
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* 13.2 MPU Register Map
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*/
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/* Table 13-1. USB Function Module Registers (endpoint) */
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#define UDC_BASE 0xFFFB4000
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#define UDC_OFFSET(offset) (UDC_BASE + (offset))
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#define UDC_REV UDC_OFFSET(0x0) /* Revision */
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#define UDC_EP_NUM UDC_OFFSET(0x4) /* Endpoint selection */
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#define UDC_DATA UDC_OFFSET(0x08) /* Data */
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#define UDC_CTRL UDC_OFFSET(0x0C) /* Control */
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#define UDC_STAT_FLG UDC_OFFSET(0x10) /* Status flag */
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#define UDC_RXFSTAT UDC_OFFSET(0x14) /* Receive FIFO status */
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#define UDC_SYSCON1 UDC_OFFSET(0x18) /* System configuration 1 */
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#define UDC_SYSCON2 UDC_OFFSET(0x1C) /* System configuration 2 */
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#define UDC_DEVSTAT UDC_OFFSET(0x20) /* Device status */
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#define UDC_SOF UDC_OFFSET(0x24) /* Start of frame */
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#define UDC_IRQ_EN UDC_OFFSET(0x28) /* Interrupt enable */
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#define UDC_DMA_IRQ_EN UDC_OFFSET(0x2C) /* DMA interrupt enable */
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#define UDC_IRQ_SRC UDC_OFFSET(0x30) /* Interrupt source */
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#define UDC_EPN_STAT UDC_OFFSET(0x34) /* Endpoint interrupt status */
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#define UDC_DMAN_STAT UDC_OFFSET(0x3C) /* DMA endpoint interrupt status */
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/* IRQ_EN register fields */
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#define UDC_Sof_IE (1 << 7) /* Start-of-frame interrupt enabled */
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#define UDC_EPn_RX_IE (1 << 5) /* Receive endpoint interrupt enabled */
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#define UDC_EPn_TX_IE (1 << 4) /* Transmit endpoint interrupt enabled */
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#define UDC_DS_Chg_IE (1 << 3) /* Device state changed interrupt enabled */
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#define UDC_EP0_IE (1 << 0) /* EP0 transaction interrupt enabled */
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/* IRQ_SRC register fields */
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#define UDC_TXn_Done (1 << 10) /* Transmit DMA channel n done */
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#define UDC_RXn_Cnt (1 << 9) /* Receive DMA channel n transactions count */
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#define UDC_RXn_EOT (1 << 8) /* Receive DMA channel n end of transfer */
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#define UDC_SOF_Flg (1 << 7) /* Start-of-frame interrupt flag */
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#define UDC_EPn_RX (1 << 5) /* Endpoint n OUT transaction */
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#define UDC_EPn_TX (1 << 4) /* Endpoint n IN transaction */
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#define UDC_DS_Chg (1 << 3) /* Device state changed */
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#define UDC_Setup (1 << 2) /* Setup transaction */
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#define UDC_EP0_RX (1 << 1) /* EP0 OUT transaction */
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#define UDC_EP0_TX (1 << 0) /* EP0 IN transaction */
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/* DEVSTAT register fields, 14.2.9 */
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#define UDC_R_WK_OK (1 << 6) /* Remote wakeup granted */
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#define UDC_USB_Reset (1 << 5) /* USB reset signalling is active */
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#define UDC_SUS (1 << 4) /* Suspended state */
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#define UDC_CFG (1 << 3) /* Configured state */
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#define UDC_ADD (1 << 2) /* Addressed state */
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#define UDC_DEF (1 << 1) /* Default state */
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#define UDC_ATT (1 << 0) /* Attached state */
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/* SYSCON1 register fields */
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#define UDC_Cfg_Lock (1 << 8) /* Device configuration locked */
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#define UDC_Nak_En (1 << 4) /* NAK enable */
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#define UDC_Self_Pwr (1 << 2) /* Device is self-powered */
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#define UDC_Soff_Dis (1 << 1) /* Shutoff disabled */
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#define UDC_Pullup_En (1 << 0) /* External pullup enabled */
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/* SYSCON2 register fields */
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#define UDC_Rmt_Wkp (1 << 6) /* Remote wakeup */
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#define UDC_Stall_Cmd (1 << 5) /* Stall endpoint */
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#define UDC_Dev_Cfg (1 << 3) /* Device configured */
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#define UDC_Clr_Cfg (1 << 2) /* Clear configured */
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/*
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* Select and enable endpoints
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*/
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/* Table 13-1. USB Function Module Registers (endpoint configuration) */
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#define UDC_EPBASE UDC_OFFSET(0x80) /* Endpoints base address */
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#define UDC_EP0 UDC_EPBASE /* Control endpoint configuration */
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#define UDC_EP_RX_BASE UDC_OFFSET(0x84) /* Receive endpoints base address */
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#define UDC_EP_RX(endpoint) (UDC_EP_RX_BASE + ((endpoint) - 1) * 4)
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#define UDC_EP_TX_BASE UDC_OFFSET(0xC4) /* Transmit endpoints base address */
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#define UDC_EP_TX(endpoint) (UDC_EP_TX_BASE + ((endpoint) - 1) * 4)
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/* EP_NUM register fields */
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#define UDC_Setup_Sel (1 << 6) /* Setup FIFO select */
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#define UDC_EP_Sel (1 << 5) /* TX/RX FIFO select */
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#define UDC_EP_Dir (1 << 4) /* Endpoint direction */
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/* CTRL register fields */
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#define UDC_Clr_Halt (1 << 7) /* Clear halt endpoint */
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#define UDC_Set_Halt (1 << 6) /* Set halt endpoint */
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#define UDC_Set_FIFO_En (1 << 2) /* Set FIFO enable */
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#define UDC_Clr_EP (1 << 1) /* Clear endpoint */
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#define UDC_Reset_EP (1 << 0) /* Reset endpoint */
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/* STAT_FLG register fields */
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#define UDC_Miss_In (1 << 14)
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#define UDC_Data_Flush (1 << 13)
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#define UDC_ISO_Err (1 << 12)
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#define UDC_ISO_FIFO_Empty (1 << 9)
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#define UDC_ISO_FIFO_Full (1 << 8)
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#define UDC_EP_Halted (1 << 6)
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#define UDC_STALL (1 << 5)
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#define UDC_NAK (1 << 4)
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#define UDC_ACK (1 << 3)
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#define UDC_FIFO_En (1 << 2)
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#define UDC_Non_ISO_FIFO_Empty (1 << 1)
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#define UDC_Non_ISO_FIFO_Full (1 << 0)
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/* EPn_RX register fields */
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#define UDC_EPn_RX_Valid (1 << 15) /* valid */
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#define UDC_EPn_RX_Db (1 << 14) /* double-buffer */
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#define UDC_EPn_RX_Iso (1 << 11) /* isochronous */
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/* EPn_TX register fields */
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#define UDC_EPn_TX_Valid (1 << 15) /* valid */
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#define UDC_EPn_TX_Db (1 << 14) /* double-buffer */
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#define UDC_EPn_TX_Iso (1 << 11) /* isochronous */
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#define EP0_PACKETSIZE 0x40
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/* physical to logical endpoint mapping
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* Physical endpoints are an index into device->bus->endpoint_array.
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* Logical endpoints are endpoints 0 to 15 IN and OUT as defined in
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* the USB specification.
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*
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* physical ep logical ep direction endpoint_address
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* 0 0 IN and OUT 0x00
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* 1 to 15 1 to 15 OUT 0x01 to 0x0f
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* 16 to 30 1 to 15 IN 0x81 to 0x8f
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*/
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#define PHYS_EP_TO_EP_ADDR(ep) (((ep) < 16) ? (ep) : (((ep) - 15) | 0x80))
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#define EP_ADDR_TO_PHYS_EP(a) (((a) & 0x80) ? (((a) & ~0x80) + 15) : (a))
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/* MOD_CONF_CTRL_0 bits (FIXME: move to board hardware.h ?) */
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#define CONF_MOD_USB_W2FC_VBUS_MODE_R (1 << 17)
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/* Other registers (may be) related to USB */
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#define CLOCK_CTRL (0xFFFE0830)
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#define APLL_CTRL (0xFFFE084C)
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#define DPLL_CTRL (0xFFFE083C)
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#define SOFT_REQ (0xFFFE0834)
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#define STATUS_REQ (0xFFFE0840)
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/* FUNC_MUX_CTRL_0 bits related to USB */
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#define UDC_VBUS_CTRL (1 << 19)
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#define UDC_VBUS_MODE (1 << 18)
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/* OMAP Endpoint parameters */
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#define UDC_OUT_PACKET_SIZE 64
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#define UDC_IN_PACKET_SIZE 64
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#define UDC_INT_PACKET_SIZE 16
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#define UDC_BULK_PACKET_SIZE 16
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#define UDC_INT_ENDPOINT 5
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#define UDC_OUT_ENDPOINT 2
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#define UDC_IN_ENDPOINT 1
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#endif
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