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Merge git://git.denx.de/u-boot-fsl-qoriq

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This commit is contained in:
Tom Rini 2017-09-12 12:02:50 -04:00
commit 8a33cb8b6b
67 changed files with 3970 additions and 226 deletions
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13
README
View file

@ -312,6 +312,19 @@ Many of the options are named exactly as the corresponding Linux
kernel configuration options. The intention is to make it easier to
build a config tool - later.
- ARM Platform Bus Type(CCI):
CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
provides full cache coherency between two clusters of multi-core
CPUs and I/O coherency for devices and I/O masters
CONFIG_SYS_FSL_HAS_CCI400
Defined For SoC that has cache coherent interconnect
CCN-400
CONFIG_SYS_FSL_HAS_CCN504
Defined for SoC that has cache coherent interconnect CCN-504
The following options need to be configured:

27
arch/arm/Kconfig
View file

@ -808,6 +808,19 @@ config TARGET_LS2080A_SIMU
development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
config TARGET_LS1088AQDS
bool "Support ls1088aqds"
select ARCH_LS1088A
select ARM64
select ARMV8_MULTIENTRY
select ARCH_MISC_INIT
select BOARD_LATE_INIT
help
Support for NXP LS1088AQDS platform
The LS1088A Development System (QDS) is a high-performance
development platform that supports the QorIQ LS1088A
Layerscape Architecture processor.
config TARGET_LS2080AQDS
bool "Support ls2080aqds"
select ARCH_LS2080A
@ -909,6 +922,19 @@ config TARGET_LS1012AFRDM
development platform that supports the QorIQ LS1012A
Layerscape Architecture processor.
config TARGET_LS1088ARDB
bool "Support ls1088ardb"
select ARCH_LS1088A
select ARM64
select ARMV8_MULTIENTRY
select ARCH_MISC_INIT
select BOARD_LATE_INIT
help
Support for NXP LS1088ARDB platform.
The LS1088A Reference design board (RDB) is a high-performance
development platform that supports the QorIQ LS1088A
Layerscape Architecture processor.
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select BOARD_LATE_INIT
@ -1192,6 +1218,7 @@ source "board/creative/xfi3/Kconfig"
source "board/freescale/ls2080a/Kconfig"
source "board/freescale/ls2080aqds/Kconfig"
source "board/freescale/ls2080ardb/Kconfig"
source "board/freescale/ls1088a/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"

36
arch/arm/cpu/armv7/ls102xa/Kconfig
View file

@ -2,9 +2,14 @@ config ARCH_LS1021A
bool
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008407
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_HAS_CCI400
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@ -49,9 +54,40 @@ config SECURE_BOOT
Enable Freescale Secure Boot feature. Normally selected
by defconfig. If unsure, do not change.
config SYS_CCI400_OFFSET
hex "Offset for CCI400 base"
depends on SYS_FSL_HAS_CCI400
default 0x180000
help
Offset for CCI400 base.
CCI400 base addr = CCSRBAR + CCI400_OFFSET
config SYS_FSL_ERRATUM_A008997
bool
help
Workaround for USB PHY erratum A008997
config SYS_FSL_ERRATUM_A009007
bool
help
Workaround for USB PHY erratum A009007
config SYS_FSL_ERRATUM_A009008
bool
help
Workaround for USB PHY erratum A009008
config SYS_FSL_ERRATUM_A009798
bool
help
Workaround for USB PHY erratum A009798
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
config SYS_FSL_HAS_CCI400
bool
config SYS_FSL_SRDS_1
bool

53
arch/arm/cpu/armv7/ls102xa/soc.c
View file

@ -60,6 +60,50 @@ unsigned int get_soc_major_rev(void)
return major;
}
static void erratum_a009008(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
clrsetbits_be32(scfg + SCFG_USB3PRM1CR / 4,
0xF << 6,
SCFG_USB_TXVREFTUNE << 6);
#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
}
static void erratum_a009798(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
clrbits_be32(scfg + SCFG_USB3PRM1CR / 4,
SCFG_USB_SQRXTUNE_MASK << 23);
#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
}
static void erratum_a008997(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
clrsetbits_be32(scfg + SCFG_USB3PRM2CR / 4,
SCFG_USB_PCSTXSWINGFULL_MASK,
SCFG_USB_PCSTXSWINGFULL_VAL);
#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
}
static void erratum_a009007(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);
out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);
out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);
out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4);
#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
}
void s_init(void)
{
}
@ -80,7 +124,8 @@ void erratum_a010315(void)
int arch_soc_init(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
@ -146,6 +191,12 @@ int arch_soc_init(void)
*/
out_be32(&scfg->eddrtqcfg, 0x63b20042);
/* Erratum */
erratum_a009008();
erratum_a009798();
erratum_a008997();
erratum_a009007();
return 0;
}

1
arch/arm/cpu/armv8/Kconfig
View file

@ -88,6 +88,7 @@ config PSCI_RESET
depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
!TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
!TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
!TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
!TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \

113
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View file

@ -16,8 +16,12 @@ config ARCH_LS1043A
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008850
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009660
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009929
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
@ -39,6 +43,10 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A008336
select SYS_FSL_ERRATUM_A008511
select SYS_FSL_ERRATUM_A008850
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009801
select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942
@ -50,6 +58,32 @@ config ARCH_LS1046A
select BOARD_EARLY_INIT_F
imply SCSI
config ARCH_LS1088A
bool
select ARMV8_SET_SMPEN
select FSL_LSCH3
select SYS_FSL_DDR
select SYS_FSL_DDR_LE
select SYS_FSL_DDR_VER_50
select SYS_FSL_EC1
select SYS_FSL_EC2
select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A008511
select SYS_FSL_ERRATUM_A008850
select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_DDR4
select SYS_FSL_HAS_RGMII
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
select SYS_FSL_SRDS_1
select SYS_FSL_SRDS_2
select FSL_TZASC_1
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
config ARCH_LS2080A
bool
select ARMV8_SET_SMPEN
@ -61,6 +95,7 @@ config ARCH_LS2080A
select SYS_FSL_DDR
select SYS_FSL_DDR_LE
select SYS_FSL_DDR_VER_50
select SYS_FSL_HAS_CCN504
select SYS_FSL_HAS_DP_DDR
select SYS_FSL_HAS_SEC
select SYS_FSL_HAS_DDR4
@ -73,8 +108,12 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A008511
select SYS_FSL_ERRATUM_A008514
select SYS_FSL_ERRATUM_A008585
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009635
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009801
select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942
@ -85,6 +124,7 @@ config ARCH_LS2080A
config FSL_LSCH2
bool
select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_BE
@ -98,7 +138,7 @@ config FSL_LSCH3
config FSL_MC_ENET
bool "Management Complex network"
depends on ARCH_LS2080A
depends on ARCH_LS2080A || ARCH_LS1088A
default y
select RESV_RAM
help
@ -114,6 +154,7 @@ config FSL_PCIE_COMPAT
default "fsl,ls1043a-pcie" if ARCH_LS1043A
default "fsl,ls1046a-pcie" if ARCH_LS1046A
default "fsl,ls2080a-pcie" if ARCH_LS2080A
default "fsl,ls1088a-pcie" if ARCH_LS1088A
help
This compatible is used to find pci controller node in Kernel DT
to complete fixup.
@ -182,6 +223,7 @@ config SYS_LS_PPA_FW_ADDR
default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
default 0x400000 if SYS_LS_PPA_FW_IN_MMC
default 0x400000 if SYS_LS_PPA_FW_IN_NAND
@ -195,12 +237,13 @@ config SYS_LS_PPA_FW_ADDR
config SYS_LS_PPA_ESBC_ADDR
hex "hdr address of PPA firmware loading from"
depends on FSL_LS_PPA && CHAIN_OF_TRUST
default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
default 0x700000 if SYS_LS_PPA_FW_IN_MMC
default 0x700000 if SYS_LS_PPA_FW_IN_NAND
default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
default 0x680000 if SYS_LS_PPA_FW_IN_MMC
default 0x680000 if SYS_LS_PPA_FW_IN_NAND
help
If the PPA header firmware locate at XIP flash, such as NOR or
QSPI flash, this address is a directly memory-mapped.
@ -217,6 +260,20 @@ config LS_PPA_ESBC_HDR_SIZE
endmenu
config SYS_FSL_ERRATUM_A008997
bool "Workaround for USB PHY erratum A008997"
config SYS_FSL_ERRATUM_A009007
bool
help
Workaround for USB PHY erratum A009007
config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
@ -228,6 +285,7 @@ config MAX_CPUS
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
default 16 if ARCH_LS2080A
default 8 if ARCH_LS1088A
default 1
help
Set this number to the maximum number of possible CPUs in the SoC.
@ -248,12 +306,27 @@ config QSPI_AHB_INIT
But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
bus for those flashes to support the full QSPI flash size.
config SYS_CCI400_OFFSET
hex "Offset for CCI400 base"
depends on SYS_FSL_HAS_CCI400
default 0x3090000 if ARCH_LS1088A
default 0x180000 if FSL_LSCH2
help
Offset for CCI400 base
CCI400 base addr = CCSRBAR + CCI400_OFFSET
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
default 8 if ARCH_LS2080A
default 8 if ARCH_LS2080A || ARCH_LS1088A
config SYS_FSL_HAS_CCI400
bool
config SYS_FSL_HAS_CCN504
bool
config SYS_FSL_HAS_DP_DDR
bool
@ -296,6 +369,7 @@ config SYS_FSL_PCLK_DIV
int "Platform clock divider"
default 1 if ARCH_LS1043A
default 1 if ARCH_LS1046A
default 1 if ARCH_LS1088A
default 2
help
This is the divider that is used to derive Platform clock from
@ -362,6 +436,18 @@ config RESV_RAM
be at the high end of physical memory. The reserve RAM may be
excluded from memory bank(s) passed to OS, or marked as reserved.
config SYS_FSL_EC1
bool
help
Ethernet controller 1, this is connected to MAC3.
Provides DPAA2 capabilities
config SYS_FSL_EC2
bool
help
Ethernet controller 2, this is connected to MAC4.
Provides DPAA2 capabilities
config SYS_FSL_ERRATUM_A008336
bool
@ -386,10 +472,17 @@ config SYS_FSL_ERRATUM_A009660
config SYS_FSL_ERRATUM_A009929
bool
config SYS_FSL_HAS_RGMII
bool
depends on SYS_FSL_EC1 || SYS_FSL_EC2
config SYS_MC_RSV_MEM_ALIGN
hex "Management Complex reserved memory alignment"
depends on RESV_RAM
default 0x20000000
default 0x20000000 if ARCH_LS2080A
default 0x70000000 if ARCH_LS1088A
help
Reserved memory needs to be aligned for MC to use. Default value
is 512MB.

4
arch/arm/cpu/armv8/fsl-layerscape/Makefile
View file

@ -38,3 +38,7 @@ endif
ifneq ($(CONFIG_ARCH_LS1046A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
endif
ifneq ($(CONFIG_ARCH_LS1088A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
endif

20
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View file

@ -16,6 +16,7 @@
#include <asm/arch/soc.h>
#include <asm/arch/cpu.h>
#include <asm/arch/speed.h>
#include <fsl_immap.h>
#include <asm/arch/mp.h>
#include <efi_loader.h>
#include <fm_eth.h>
@ -516,6 +517,10 @@ int arch_early_init_r(void)
printf("Did not wake secondary cores\n");
}
#ifdef CONFIG_SYS_FSL_HAS_RGMII
fsl_rgmii_init();
#endif
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
#endif
@ -614,13 +619,22 @@ void efi_reset_system_init(void)
#endif
/*
* Calculate reserved memory with given memory bank
* Return aligned memory size on success
* Return (ram_size + needed size) for failure
*/
phys_size_t board_reserve_ram_top(phys_size_t ram_size)
{
phys_size_t ram_top = ram_size;
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
ram_top = mc_get_dram_block_size();
if (ram_top > ram_size)
return ram_size + ram_top;
ram_top = ram_size - ram_top;
/* The start address of MC reserved memory needs to be aligned. */
ram_top -= mc_get_dram_block_size();
ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
#endif
@ -664,8 +678,8 @@ phys_size_t get_effective_memsize(void)
/* Check if we have enough memory for MC */
if (rem < board_reserve_ram_top(rem)) {
/* Not enough memory in high region to reserve */
if (ea_size > board_reserve_ram_top(rem))
ea_size -= board_reserve_ram_top(rem);
if (ea_size > board_reserve_ram_top(ea_size))
ea_size -= board_reserve_ram_top(ea_size);
else
printf("Error: No enough space for reserved memory.\n");
}

43
arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
View file

@ -1,11 +1,12 @@
SoC overview
1. LS1043A
2. LS2080A
3. LS1012A
4. LS1046A
5. LS2088A
6. LS2081A
2. LS1088A
3. LS2080A
4. LS1012A
5. LS1046A
6. LS2088A
7. LS2081A
LS1043A
---------
@ -45,6 +46,38 @@ The LS1043A SoC includes the following function and features:
- Integrated flash controller supporting NAND and NOR flash
- QorIQ platform's trust architecture 2.1
LS1088A
--------
The QorIQ LS1088A processor is built on the Layerscape
architecture combining eight ARM A53 processor cores
with advanced, high-performance datapath acceleration
and networks, peripheral interfaces required for
networking, wireless infrastructure, and general-purpose
embedded applications.
LS1088A is compliant with the Layerscape Chassis Generation 3.
Features summary:
- 8 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
- Cores are in 2 cluster of 4-cores each
- 1MB L2 - Cache per cluster
- Cache coherent interconnect (CCI-400)
- 1 64-bit DDR4 SDRAM memory controller with ECC
- Data path acceleration architecture 2.0 (DPAA2)
- 4-Lane 10GHz SerDes comprising of WRIOP
- 4-Lane 10GHz SerDes comprising of PCI, SATA, uQE(TDM/HLDC/UART)
- Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs
- QSPI, SPI, IFC2.0 supporting NAND, NOR flash
- 3 PCIe3.0 , 1 SATA3.0, 2 USB3.0, 1 SDXC, 2 DUARTs etc
- 2 DUARTs
- 4 I2C, GPIO
- Thermal monitor unit(TMU)
- 4 Flextimers and 1 generic timer
- Support for hardware virtualization and partitioning enforcement
- QorIQ platform's trust architecture 3.0
- Service processor (SP) provides pre-boot initialization and secure-boot
capabilities
LS2080A
--------
The LS2080A integrated multicore processor combines eight ARM Cortex-A57

2
arch/arm/cpu/armv8/fsl-layerscape/fdt.c
View file

@ -418,7 +418,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_firmware(blob);
#endif
#ifndef CONFIG_LS1012A
#ifndef CONFIG_ARCH_LS1012A
fsl_fdt_disable_usb(blob);
#endif
#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN

19
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
View file

@ -28,6 +28,20 @@ __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
return;
}
/*
*The return value of this func is the serdes protocol used.
*Typically this function is called number of times depending
*upon the number of serdes blocks in the Silicon.
*Zero is used to denote that no serdes was enabled,
*this is the case when golden RCW was used where DPAA2 bring was
*intentionally removed to achieve boot to prompt
*/
__weak int serdes_get_number(int serdes, int cfg)
{
return cfg;
}
int is_serdes_configured(enum srds_prtcl device)
{
int ret = 0;
@ -73,6 +87,9 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
printf("invalid SerDes%d\n", sd);
break;
}
cfg = serdes_get_number(sd, cfg);
/* Is serdes enabled at all? */
if (cfg == 0)
return -ENODEV;
@ -99,6 +116,8 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
cfg >>= sd_prctl_shift;
cfg = serdes_get_number(sd, cfg);
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
if (!is_serdes_prtcl_valid(sd, cfg))

12
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
View file

@ -76,7 +76,7 @@ ENTRY(lowlevel_init)
switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
1:
#ifdef CONFIG_FSL_LSCH3
#if defined (CONFIG_SYS_FSL_HAS_CCN504)
/* Set Wuo bit for RN-I 20 */
#ifdef CONFIG_ARCH_LS2080A
@ -171,7 +171,7 @@ ENTRY(lowlevel_init)
ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
ldr x1, =0x00FF000C
bl ccn504_set_qos
#endif
#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
#ifdef SMMU_BASE
/* Set the SMMU page size in the sACR register */
@ -338,7 +338,9 @@ get_svr:
ldr x1, =FSL_LSCH3_SVR
ldr w0, [x1]
ret
#endif
#ifdef CONFIG_SYS_FSL_HAS_CCN504
hnf_pstate_poll:
/* x0 has the desired status, return 0 for success, 1 for timeout
* clobber x1, x2, x3, x4, x6, x7
@ -394,9 +396,6 @@ ENTRY(__asm_flush_l3_dcache)
mov x29, lr
mov x8, #0
switch_el x0, 1f, 100f, 100f /* skip if not in EL3 */
1:
dsb sy
mov x0, #0x1 /* HNFPSTAT_SFONLY */
bl hnf_set_pstate
@ -414,13 +413,12 @@ ENTRY(__asm_flush_l3_dcache)
bl hnf_pstate_poll
cbz x0, 1f
add x8, x8, #0x2
100:
1:
mov x0, x8
mov lr, x29
ret
ENDPROC(__asm_flush_l3_dcache)
#endif
#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
#ifdef CONFIG_MP
/* Keep literals not used by the secondary boot code outside it */

126
arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c Normal file
View file

@ -0,0 +1,126 @@
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/fsl_serdes.h>
struct serdes_config {
u8 ip_protocol;
u8 lanes[SRDS_MAX_LANES];
u8 rcw_lanes[SRDS_MAX_LANES];
};
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{0x12, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 3 } },
{0x15, {SGMII3, SGMII7, XFI1, XFI2 }, {3, 3, 1, 1 } },
{0x16, {SGMII3, SGMII7, SGMII1, XFI2 }, {3, 3, 3, 1 } },
{0x17, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 2 } },
{0x18, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 2, 2 } },
{0x19, {SGMII3, QSGMII_B, XFI1, XFI2}, {3, 4, 1, 1 } },
{0x1A, {SGMII3, QSGMII_B, SGMII1, XFI2 }, {3, 4, 3, 1 } },
{0x1B, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 2 } },
{0x1C, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 2, 2 } },
{0x1D, {QSGMII_A, QSGMII_B, XFI1, XFI2 }, {4, 4, 1, 1 } },
{0x1E, {QSGMII_A, QSGMII_B, SGMII1, XFI2 }, {4, 4, 3, 1 } },
{0x1F, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 3, 2 } },
{0x20, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 2, 2 } },
{0x35, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 3 } },
{0x36, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 3, 3 } },
{0x3A, {SGMII3, PCIE1, SGMII1, SGMII2 }, {3, 5, 3, 3 } },
{}
};
static struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
{0x0C, {PCIE1, PCIE1, PCIE1, PCIE1 }, {8, 8, 8, 8 } },
{0x0D, {PCIE1, PCIE2, PCIE3, SATA1 }, {5, 5, 5, 9 } },
{0x0E, {PCIE1, PCIE1, PCIE2, SATA1 }, {7, 7, 6, 9 } },
{0x13, {PCIE1, PCIE1, PCIE3, PCIE3 }, {7, 7, 7, 7 } },
{0x14, {PCIE1, PCIE2, PCIE3, PCIE3 }, {5, 5, 7, 7 } },
{0x3C, {NONE, PCIE2, NONE, PCIE3 }, {0, 5, 0, 6 } },
{}
};
static struct serdes_config *serdes_cfg_tbl[] = {
serdes1_cfg_tbl,
serdes2_cfg_tbl,
};
int serdes_get_number(int serdes, int cfg)
{
struct serdes_config *ptr;
int i, j, index, lnk;
int is_found, max_lane = SRDS_MAX_LANES;
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
ptr = serdes_cfg_tbl[serdes];
while (ptr->ip_protocol) {
is_found = 1;
for (i = 0, j = max_lane - 1; i < max_lane; i++, j--) {
lnk = cfg & (0xf << 4 * i);
lnk = lnk >> (4 * i);
index = (serdes == FSL_SRDS_1) ? j : i;
if (ptr->rcw_lanes[index] == lnk && is_found)
is_found = 1;
else
is_found = 0;
}
if (is_found)
return ptr->ip_protocol;
ptr++;
}
return 0;
}
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
{
struct serdes_config *ptr;
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
ptr = serdes_cfg_tbl[serdes];
while (ptr->ip_protocol) {
if (ptr->ip_protocol == cfg)
return ptr->lanes[lane];
ptr++;
}
return 0;
}
int is_serdes_prtcl_valid(int serdes, u32 prtcl)
{
int i;
struct serdes_config *ptr;
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
ptr = serdes_cfg_tbl[serdes];
while (ptr->ip_protocol) {
if (ptr->ip_protocol == prtcl)
break;
ptr++;
}
if (!ptr->ip_protocol)
return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) {
if (ptr->lanes[i] != NONE)
return 1;
}
return 0;
}

122
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View file

@ -5,6 +5,7 @@
*/
#include <common.h>
#include <fsl_immap.h>
#include <fsl_ifc.h>
#include <ahci.h>
#include <scsi.h>
@ -23,6 +24,7 @@
#ifdef CONFIG_CHAIN_OF_TRUST
#include <fsl_validate.h>
#endif
#include <fsl_immap.h>
DECLARE_GLOBAL_DATA_PTR;
@ -52,6 +54,109 @@ bool soc_has_aiop(void)
return false;
}
static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
{
scfg_clrsetbits32(scfg + offset / 4,
0xF << 6,
SCFG_USB_TXVREFTUNE << 6);
}
static void erratum_a009008(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
#elif defined(CONFIG_ARCH_LS2080A)
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
#endif
#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
}
static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
{
scfg_clrbits32(scfg + offset / 4,
SCFG_USB_SQRXTUNE_MASK << 23);
}
static void erratum_a009798(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
#elif defined(CONFIG_ARCH_LS2080A)
set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
#endif
#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
}
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
{
scfg_clrsetbits32(scfg + offset / 4,
0x7F << 9,
SCFG_USB_PCSTXSWINGFULL << 9);
}
#endif
static void erratum_a008997(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
#endif
#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
}
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
#elif defined(CONFIG_ARCH_LS2080A)
#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
#endif
static void erratum_a009007(void)
{
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
usb_phy = (void __iomem *)SCFG_USB_PHY2;
PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
usb_phy = (void __iomem *)SCFG_USB_PHY3;
PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
#elif defined(CONFIG_ARCH_LS2080A)
void __iomem *dcsr = (void __iomem *)DCSR_BASE;
PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
}
#if defined(CONFIG_FSL_LSCH3)
/*
* This erratum requires setting a value to eddrtqcr1 to
@ -198,6 +303,10 @@ void fsl_lsch3_early_init_f(void)
#endif
erratum_a008514();
erratum_a008336();
erratum_a009008();
erratum_a009798();
erratum_a008997();
erratum_a009007();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@ -285,7 +394,8 @@ static void erratum_a008850_early(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
/* part 1 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
/* Skip if running at lower exception level */
@ -304,7 +414,8 @@ void erratum_a008850_post(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
/* part 2 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
u32 tmp;
@ -439,7 +550,8 @@ int setup_chip_volt(void)
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
@ -473,6 +585,10 @@ void fsl_lsch2_early_init_f(void)
erratum_a009929();
erratum_a009660();
erratum_a010539();
erratum_a009008();
erratum_a009798();
erratum_a008997();
erratum_a009007();
}
#endif

4
arch/arm/dts/Makefile
View file

@ -188,7 +188,9 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb \
fsl-ls2081a-rdb.dtb \
fsl-ls2088a-rdb-qspi.dtb
fsl-ls2088a-rdb-qspi.dtb \
fsl-ls1088a-rdb.dtb \
fsl-ls1088a-qds.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \

70
arch/arm/dts/fsl-ls1088a-qds.dts Normal file
View file

@ -0,0 +1,70 @@
/*
* NXP ls1088a QDS board device tree source
*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "fsl-ls1088a.dtsi"
/ {
model = "NXP Layerscape 1088a QDS Board";
compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
aliases {
spi0 = &qspi;
spi1 = &dspi;
};
};
&dspi {
bus-num = <0>;
status = "okay";
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
reg = <0>;
spi-max-frequency = <1000000>; /* input clock */
};
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3500000>;
reg = <1>;
};
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3500000>;
reg = <2>;
};
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: s25fs512s@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <50000000>;
reg = <0>;
};
qflash1: s25fs512s@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <50000000>;
reg = <1>;
};
};

40
arch/arm/dts/fsl-ls1088a-rdb.dts Normal file
View file

@ -0,0 +1,40 @@
/*
* NXP ls1088a RDB board device tree source
*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "fsl-ls1088a.dtsi"
/ {
model = "NXP Layerscape 1088a RDB Board";
compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
aliases {
spi0 = &qspi;
};
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: s25fs512s@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <50000000>;
reg = <0>;
};
qflash1: s25fs512s@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <50000000>;
reg = <1>;
};
};

126
arch/arm/dts/fsl-ls1088a.dtsi Normal file
View file

@ -0,0 +1,126 @@
/*
* NXP ls1088a SOC common device tree source
*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
/ {
compatible = "fsl,ls1088a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>;
/* DRAM space - 1, size : 2 GB DRAM */
};
gic: interrupt-controller@6000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
<0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <1 9 0x4>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
<1 14 0x8>, /* Physical Non-Secure PPI, active-low */
<1 11 0x8>, /* Virtual PPI, active-low */
<1 10 0x8>; /* Hypervisor PPI, active-low */
};
serial0: serial@21c0500 {
device_type = "serial";
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0500 0x0 0x100>;
clock-frequency = <0>; /* Updated by bootloader */
interrupts = <0 32 0x1>; /* edge triggered */
};
serial1: serial@21c0600 {
device_type = "serial";
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0600 0x0 0x100>;
clock-frequency = <0>; /* Updated by bootloader */
interrupts = <0 32 0x1>; /* edge triggered */
};
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
};
dspi: dspi@2100000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <0 26 0x4>; /* Level high type */
num-cs = <6>;
};
qspi: quadspi@1550000 {
compatible = "fsl,vf610-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <4>;
};
pcie@3400000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
0x00 0x03480000 0x0 0x80000 /* lut registers */
0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
0x20 0x00000000 0x0 0x20000>; /* configuration space */
reg-names = "dbi", "lut", "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
pcie@3500000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
0x00 0x03580000 0x0 0x80000 /* lut registers */
0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
0x28 0x00000000 0x0 0x20000>; /* configuration space */
reg-names = "dbi", "lut", "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
pcie@3600000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
0x00 0x03680000 0x0 0x80000 /* lut registers */
0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
0x30 0x00000000 0x0 0x20000>; /* configuration space */
reg-names = "dbi", "lut", "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
};

62
arch/arm/include/asm/arch-fsl-layerscape/config.h
View file

@ -116,6 +116,67 @@
#define CONFIG_SYS_FSL_ERRATUM_A008751
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_ARCH_LS1088A)
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
#define CONFIG_FSL_TZASC_400
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4
/* TZ Protection Controller Definitions */
#define TZPC_BASE 0x02200000
#define TZPCR0SIZE_BASE (TZPC_BASE)
#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
#define GICR_BASE 0x06100000
/* SMMU Defintions */
#define SMMU_BASE 0x05000000 /* GR0 Base */
/* DDR */
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CONFIG_SYS_FSL_CCSR_GUR_LE
#define CONFIG_SYS_FSL_CCSR_SCFG_LE
#define CONFIG_SYS_FSL_ESDHC_LE
#define CONFIG_SYS_FSL_IFC_LE
#define CONFIG_SYS_FSL_PEX_LUT_LE
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
/* SFP */
#define CONFIG_SYS_FSL_SFP_VER_3_4
#define CONFIG_SYS_FSL_SFP_LE
#define CONFIG_SYS_FSL_SRK_LE
/* Security Monitor */
#define CONFIG_SYS_FSL_SEC_MON_LE
/* Secure Boot */
#define CONFIG_ESBC_HDR_LS
/* DCFG - GUR */
#define CONFIG_SYS_FSL_CCSR_GUR_LE
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
#elif defined(CONFIG_FSL_LSCH2)
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
@ -218,7 +279,6 @@
#define GICC_BASE 0x01420000
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else
#error SoC not defined
#endif

10
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
View file

@ -24,6 +24,10 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
};
#ifndef CONFIG_SYS_DCACHE_OFF
@ -199,7 +203,8 @@ static struct mm_region final_map[] = {
},
{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
CONFIG_SYS_FSL_QSPI_SIZE2,
@ -208,7 +213,8 @@ static struct mm_region final_map[] = {
},
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
CONFIG_SYS_FSL_IFC_SIZE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
CONFIG_SYS_FSL_DCSR_SIZE,

4
arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
View file

@ -9,7 +9,7 @@
#include <config.h>
#ifdef CONFIG_ARCH_LS2080A
#ifdef CONFIG_FSL_LSCH3
enum srds_prtcl {
/*
* Nobody will check whether the device 'NONE' has been configured,
@ -158,6 +158,8 @@ void fsl_serdes_init(void);
int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
int serdes_get_number(int serdes, int cfg);
void fsl_rgmii_init(void);
#ifdef CONFIG_FSL_LSCH2
const char *serdes_clock_to_string(u32 clock);

68
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View file

@ -15,7 +15,6 @@
#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
@ -338,6 +337,25 @@ struct ccsr_gur {
#define SCFG_USBPWRFAULT_USB2_SHIFT 2
#define SCFG_USBPWRFAULT_USB1_SHIFT 0
#define SCFG_BASE 0x01570000
#define SCFG_USB3PRM1CR_USB1 0x070
#define SCFG_USB3PRM2CR_USB1 0x074
#define SCFG_USB3PRM1CR_USB2 0x07C
#define SCFG_USB3PRM2CR_USB2 0x080
#define SCFG_USB3PRM1CR_USB3 0x088
#define SCFG_USB3PRM2CR_USB3 0x08c
#define SCFG_USB_TXVREFTUNE 0x9
#define SCFG_USB_SQRXTUNE_MASK 0x7
#define SCFG_USB_PCSTXSWINGFULL 0x47
#define SCFG_USB_PHY1 0x084F0000
#define SCFG_USB_PHY2 0x08500000
#define SCFG_USB_PHY3 0x08510000
#define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c
#define USB_PHY_RX_EQ_VAL_1 0x0000
#define USB_PHY_RX_EQ_VAL_2 0x0080
#define USB_PHY_RX_EQ_VAL_3 0x0380
#define USB_PHY_RX_EQ_VAL_4 0x0b80
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
@ -544,54 +562,6 @@ struct ccsr_serdes {
u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */
};
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
#define CCI400_CTRLORD_EN_BARRIER 0
#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
#define CCI400_SNOOP_REQ_EN 0x00000001
/* CCI-400 registers */
struct ccsr_cci400 {
u32 ctrl_ord; /* Control Override */
u32 spec_ctrl; /* Speculation Control */
u32 secure_access; /* Secure Access */
u32 status; /* Status */
u32 impr_err; /* Imprecise Error */
u8 res_14[0x100 - 0x14];
u32 pmcr; /* Performance Monitor Control */
u8 res_104[0xfd0 - 0x104];
u32 pid[8]; /* Peripheral ID */
u32 cid[4]; /* Component ID */
struct {
u32 snoop_ctrl; /* Snoop Control */
u32 sha_ord; /* Shareable Override */
u8 res_1008[0x1100 - 0x1008];
u32 rc_qos_ord; /* read channel QoS Value Override */
u32 wc_qos_ord; /* read channel QoS Value Override */
u8 res_1108[0x110c - 0x1108];
u32 qos_ctrl; /* QoS Control */
u32 max_ot; /* Max OT */
u8 res_1114[0x1130 - 0x1114];
u32 target_lat; /* Target Latency */
u32 latency_regu; /* Latency Regulation */
u32 qos_range; /* QoS Range */
u8 res_113c[0x2000 - 0x113c];
} slave[5]; /* Slave Interface */
u8 res_6000[0x9004 - 0x6000];
u32 cycle_counter; /* Cycle counter */
u32 count_ctrl; /* Count Control */
u32 overflow_status; /* Overflow Flag Status */
u8 res_9010[0xa000 - 0x9010];
struct {
u32 event_select; /* Event Select */
u32 event_count; /* Event Count */
u32 counter_ctrl; /* Counter Control */
u32 overflow_status; /* Overflow Flag Status */
u8 res_a010[0xb000 - 0xa010];
} pcounter[4]; /* Performance Counter */
u8 res_e004[0x10000 - 0xe004];
};
/* MMU 500 */
#define SMMU_SCR0 (SMMU_BASE + 0x0)
#define SMMU_SCR1 (SMMU_BASE + 0x4)

34
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View file

@ -107,10 +107,16 @@
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
#ifdef CONFIG_ARCH_LS1088A
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL
#else
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
#endif
/* Device Configuration */
#define DCFG_BASE 0x01e00000
@ -133,8 +139,19 @@
#define SCFG_BASE 0x01fc0000
#define SCFG_USB3PRM1CR 0x000
#define SCFG_USB3PRM1CR_INIT 0x27672b2a
#define SCFG_USB_TXVREFTUNE 0x9
#define SCFG_USB_SQRXTUNE_MASK 0x7
#define SCFG_QSPICLKCTLR 0x10
#define DCSR_BASE 0x700000000ULL
#define DCSR_USB_PHY1 0x4600000
#define DCSR_USB_PHY2 0x4610000
#define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C
#define USB_PHY_RX_EQ_VAL_1 0x0000
#define USB_PHY_RX_EQ_VAL_2 0x0080
#define USB_PHY_RX_EQ_VAL_3 0x0380
#define USB_PHY_RX_EQ_VAL_4 0x0b80
#define TP_ITYP_AV 0x00000001 /* Initiator available */
#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
#define TP_ITYP_TYPE_ARM 0x0
@ -246,6 +263,23 @@ struct ccsr_gur {
#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
#define FSL_CHASSIS3_SRDS1_REGSR 29
#define FSL_CHASSIS3_SRDS2_REGSR 29
#elif defined(CONFIG_ARCH_LS1088A)
#define FSL_CHASSIS3_EC1_REGSR 26
#define FSL_CHASSIS3_EC2_REGSR 26
#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007
#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0
#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038
#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3
#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000
#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16
#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF
#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 0
#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK
#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT
#define FSL_CHASSIS3_SRDS1_REGSR 29
#define FSL_CHASSIS3_SRDS2_REGSR 30
#endif
#define RCW_SB_EN_REG_INDEX 9
#define RCW_SB_EN_MASK 0x00000400

8
arch/arm/include/asm/arch-fsl-layerscape/soc.h
View file

@ -29,9 +29,13 @@
#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
#define scfg_in32(a) in_le32(a)
#define scfg_out32(a, v) out_le32(a, v)
#define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear)
#define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set)
#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
#define scfg_in32(a) in_be32(a)
#define scfg_out32(a, v) out_be32(a, v)
#define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear)
#define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set)
#endif
#ifdef CONFIG_SYS_FSL_PEX_LUT_LE
@ -57,6 +61,10 @@ struct cpu_type {
#define SVR_LS1023A 0x879208
#define SVR_LS1046A 0x870700
#define SVR_LS1026A 0x870708
#define SVR_LS1048A 0x870320
#define SVR_LS1084A 0x870302
#define SVR_LS1088A 0x870300
#define SVR_LS1044A 0x870322
#define SVR_LS2045A 0x870120
#define SVR_LS2080A 0x870110
#define SVR_LS2085A 0x870100

14
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
View file

@ -66,12 +66,26 @@
#define FSL_USB2_STREAM_ID 2
#define FSL_SDMMC_STREAM_ID 3
#define FSL_SATA1_STREAM_ID 4
#if defined(CONFIG_ARCH_LS2080A)
#define FSL_SATA2_STREAM_ID 5
#endif
#if defined(CONFIG_ARCH_LS2080A)
#define FSL_DMA_STREAM_ID 6
#elif defined(CONFIG_ARCH_LS1088A)
#define FSL_DMA_STREAM_ID 5
#endif
/* PCI - programmed in PEXn_LUT */
#define FSL_PEX_STREAM_ID_START 7
#if defined(CONFIG_ARCH_LS2080A)
#define FSL_PEX_STREAM_ID_END 22
#elif defined(CONFIG_ARCH_LS1088A)
#define FSL_PEX_STREAM_ID_END 18
#endif
/* DPAA2 - set in MC DPC and alloced by MC */
#define FSL_DPAA2_STREAM_ID_START 23

1
arch/arm/include/asm/arch-ls102xa/config.h
View file

@ -20,7 +20,6 @@
#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)

62
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
View file

@ -6,6 +6,7 @@
#ifndef __ASM_ARCH_LS102XA_IMMAP_H_
#define __ASM_ARCH_LS102XA_IMMAP_H_
#include <fsl_immap.h>
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
@ -173,6 +174,21 @@ struct ccsr_gur {
#define SCFG_PMCINTECR_ETSECERRG1 0x00040000
#define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000
#define SCFG_BASE 0x01570000
#define SCFG_USB3PRM1CR 0x070
#define SCFG_USB_TXVREFTUNE 0x9
#define SCFG_USB_SQRXTUNE_MASK 0x7
#define SCFG_USB3PRM2CR 0x074
#define SCFG_USB_PCSTXSWINGFULL_MASK 0x0000FE00
#define SCFG_USB_PCSTXSWINGFULL_VAL 0x00008E00
#define USB_PHY_BASE 0x08510000
#define USB_PHY_RX_OVRD_IN_HI 0x200c
#define USB_PHY_RX_EQ_VAL_1 0x0000
#define USB_PHY_RX_EQ_VAL_2 0x8000
#define USB_PHY_RX_EQ_VAL_3 0x8004
#define USB_PHY_RX_EQ_VAL_4 0x800C
/* Supplemental Configuration Unit */
struct ccsr_scfg {
u32 dpslpcr;
@ -374,53 +390,7 @@ struct ccsr_serdes {
u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
};
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
#define CCI400_CTRLORD_EN_BARRIER 0
#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
#define CCI400_SNOOP_REQ_EN 0x00000001
/* CCI-400 registers */
struct ccsr_cci400 {
u32 ctrl_ord; /* Control Override */
u32 spec_ctrl; /* Speculation Control */
u32 secure_access; /* Secure Access */
u32 status; /* Status */
u32 impr_err; /* Imprecise Error */
u8 res_14[0x100 - 0x14];
u32 pmcr; /* Performance Monitor Control */
u8 res_104[0xfd0 - 0x104];
u32 pid[8]; /* Peripheral ID */
u32 cid[4]; /* Component ID */
struct {
u32 snoop_ctrl; /* Snoop Control */
u32 sha_ord; /* Shareable Override */
u8 res_1008[0x1100 - 0x1008];
u32 rc_qos_ord; /* read channel QoS Value Override */
u32 wc_qos_ord; /* read channel QoS Value Override */
u8 res_1108[0x110c - 0x1108];
u32 qos_ctrl; /* QoS Control */
u32 max_ot; /* Max OT */
u8 res_1114[0x1130 - 0x1114];
u32 target_lat; /* Target Latency */
u32 latency_regu; /* Latency Regulation */
u32 qos_range; /* QoS Range */
u8 res_113c[0x2000 - 0x113c];
} slave[5]; /* Slave Interface */
u8 res_6000[0x9004 - 0x6000];
u32 cycle_counter; /* Cycle counter */
u32 count_ctrl; /* Count Control */
u32 overflow_status; /* Overflow Flag Status */
u8 res_9010[0xa000 - 0x9010];
struct {
u32 event_select; /* Event Select */
u32 event_count; /* Event Count */
u32 counter_ctrl; /* Counter Control */
u32 overflow_status; /* Overflow Flag Status */
u8 res_a010[0xb000 - 0xa010];
} pcounter[4]; /* Performance Counter */
u8 res_e004[0x10000 - 0xe004];
};
/* AHCI (sata) register map */
struct ccsr_ahci {

57
arch/arm/include/asm/fsl_secure_boot.h
View file

@ -1,5 +1,6 @@
/*
* Copyright 2015 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -71,55 +72,49 @@
* DDR memory map
*/
#ifdef CONFIG_FSL_LSCH3
#define CONFIG_BS_HDR_ADDR_DEVICE 0x580d00000
#define CONFIG_BS_ADDR_DEVICE 0x580e00000
#define CONFIG_BS_HDR_ADDR_RAM 0xa0d00000
#define CONFIG_BS_ADDR_RAM 0xa0e00000
#define CONFIG_BS_HDR_SIZE 0x00002000
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_BS_ADDR_DEVICE 0x20600000
#define CONFIG_BS_HDR_ADDR_DEVICE 0x20640000
#else /* NOR BOOT */
#define CONFIG_BS_ADDR_DEVICE 0x580600000
#define CONFIG_BS_HDR_ADDR_DEVICE 0x580640000
#endif /*ifdef CONFIG_QSPI_BOOT */
#define CONFIG_BS_SIZE 0x00001000
#define CONFIG_BS_HDR_SIZE 0x00004000
#define CONFIG_BS_ADDR_RAM 0xa0600000
#define CONFIG_BS_HDR_ADDR_RAM 0xa0640000
#else
#ifdef CONFIG_SD_BOOT
/* For SD boot address and size are assigned in terms of sector
* offset and no. of sectors respectively.
*/
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000920
#else
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000900
#endif
#define CONFIG_BS_ADDR_DEVICE 0x00000940
#define CONFIG_BS_HDR_SIZE 0x00000010
#define CONFIG_BS_ADDR_DEVICE 0x00003000
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00003200
#define CONFIG_BS_SIZE 0x00000008
#define CONFIG_BS_HDR_SIZE 0x00000010
#elif defined(CONFIG_NAND_BOOT)
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000
#define CONFIG_BS_ADDR_DEVICE 0x00802000
#define CONFIG_BS_HDR_SIZE 0x00002000
#define CONFIG_BS_ADDR_DEVICE 0x00600000
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00640000
#define CONFIG_BS_SIZE 0x00001000
#define CONFIG_BS_HDR_SIZE 0x00002000
#elif defined(CONFIG_QSPI_BOOT)
#ifdef CONFIG_ARCH_LS1046A
#define CONFIG_BS_HDR_ADDR_DEVICE 0x40780000
#define CONFIG_BS_ADDR_DEVICE 0x40800000
#elif defined(CONFIG_ARCH_LS1012A)
#define CONFIG_BS_HDR_ADDR_DEVICE 0x400c0000
#define CONFIG_BS_ADDR_DEVICE 0x40060000
#else
#error "Platform not supported"
#endif
#define CONFIG_BS_HDR_SIZE 0x00002000
#define CONFIG_BS_ADDR_DEVICE 0x40600000
#define CONFIG_BS_HDR_ADDR_DEVICE 0x40640000
#define CONFIG_BS_SIZE 0x00001000
#define CONFIG_BS_HDR_SIZE 0x00002000
#else /* Default NOR Boot */
#define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000
#define CONFIG_BS_ADDR_DEVICE 0x60060000
#define CONFIG_BS_HDR_SIZE 0x00002000
#define CONFIG_BS_ADDR_DEVICE 0x60600000
#define CONFIG_BS_HDR_ADDR_DEVICE 0x60640000
#define CONFIG_BS_SIZE 0x00001000
#define CONFIG_BS_HDR_SIZE 0x00002000
#endif
#define CONFIG_BS_HDR_ADDR_RAM 0x81000000
#define CONFIG_BS_ADDR_RAM 0x81020000
#define CONFIG_BS_ADDR_RAM 0x81000000
#define CONFIG_BS_HDR_ADDR_RAM 0x81020000
#endif
#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM
#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
#else
#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE
/* BOOTSCRIPT_ADDR is not required */

4
board/freescale/ls1012afrdm/ls1012afrdm.c
View file

@ -71,7 +71,9 @@ int board_early_init_f(void)
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
/*
* Set CCI-400 control override register to enable barrier
* transaction

4
board/freescale/ls1012aqds/ls1012aqds.c
View file

@ -106,8 +106,8 @@ int misc_init_r(void)
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
/* Set CCI-400 control override register to enable barrier
* transaction */

3
board/freescale/ls1012ardb/ls1012ardb.c
View file

@ -104,7 +104,8 @@ int board_early_init_f(void)
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
/*
* Set CCI-400 control override register to enable barrier
* transaction

9
board/freescale/ls1021aqds/ls1021aqds.c
View file

@ -204,7 +204,8 @@ int board_early_init_f(void)
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
#ifdef CONFIG_NAND_BOOT
@ -425,7 +426,8 @@ int misc_init_r(void)
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
@ -460,7 +462,8 @@ int board_init(void)
#if defined(CONFIG_DEEP_SLEEP)
void board_sleep_prepare(void)
{
struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
major = get_soc_major_rev();

31
board/freescale/ls1088a/Kconfig Normal file
View file

@ -0,0 +1,31 @@
if TARGET_LS1088AQDS
config SYS_BOARD
default "ls1088a"
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "fsl-layerscape"
config SYS_CONFIG_NAME
default "ls1088aqds"
endif
if TARGET_LS1088ARDB
config SYS_BOARD
default "ls1088a"
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "fsl-layerscape"
config SYS_CONFIG_NAME
default "ls1088ardb"
endif

15
board/freescale/ls1088a/MAINTAINERS Normal file
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LS1088ARDB BOARD
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
M: Ashish Kumar <Ashish.Kumar@nxp.com>
S: Maintained
F: board/freescale/ls1088a/
F: include/configs/ls1088ardb.h
F: configs/ls1088ardb_qspi_defconfig
LS1088AQDS BOARD
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
M: Ashish Kumar <Ashish.Kumar@nxp.com>
S: Maintained
F: board/freescale/ls1088a/
F: include/configs/ls1088aqds.h
F: configs/ls1088aqds_qspi_defconfig

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#
# Copyright 2017 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ls1088a.o
obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o
obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o
obj-y += ddr.o

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Overview
--------
The LS1088A Reference Design (RDB) is a high-performance computing,
evaluation, and development platform that supports ARM SoC LS1088A and its
derivatives.
LS1088A SoC Overview
--------------------------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
RDB Default Switch Settings (1: ON; 0: OFF)
-------------------------------------------
For QSPI Boot
SW1 0011 0001
SW2 x100 0000
SW3 1111 0010
SW4 1001 0011
SW5 1111 0000
For SD Boot
SW1 0010 0000
SW2 0100 0000
SW3 1111 0010
SW4 1001 0011
SW5 1111 0000
For eMMC Boot
SW1 0010 0000
SW2 1100 0000
SW3 1111 0010
SW4 1001 0011
SW5 1111 0000
Alternately you can use this command to switch from QSPI to SD
=> i2c mw 66 0x60 0x20; i2c mw 66 10 10;i2c mw 66 10 21
LS1088ARDB board Overview
-------------------------
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
- SATA 3.0
- XFI
- QSGMII
- DDR Controller
- One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default
with FSL refernce software is 2100MT/s
- 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB
- IFC/Local Bus
- One 2 GB NAND flash with ECC support, not as boot source
- CPLD of size 2K
- USB 3.0
- Two high speed USB 3.0 ports
- First USB 3.0 port configured as Host with Type-A connector
- Second USB 3.0 port configured as OTG with micro-AB connector
- SDHC/eMMC
- SDHC slot and onboard eMMC are muxed together
- 4 I2C controllers
- Two SATA onboard connectors
- 2 UART
- JTAG support
- QSPI emulator support
- TDM riser support
QDS Default Switch Settings (1: ON; 0: OFF)
-------------------------------------------
For 16b IFC-NOR
SW1 0001 0010
SW2 x110 1111
For QSPI Boot
SW1 0011 0001
SW2 0110 1111
For SD Boot
SW1 0010 0000
SW2 0110 1111
For eMMC Boot
SW1 0010 0000
SW2 1110 1111
For I2C (ext. addr.)
SW1 0010 0100
SW2 1110 1111
SW3 to SW12 are identical for all boot source
SW3 0010 0100
SW4 0010 0000
SW5 1110 0111
SW6 1110 1000
SW7 0001 1101
SW8 0000 1101
SW9 1100 1010
SW10 1110 1000
SW11 1111 0100
SW12 1111 1111
LS1088AQDS board Overview
-------------------------
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
- SATA 3.0
- 2 XFI
- QSGMII, SGMII with help for Riser card
- 2 RGMII
- 5 slot for Riser card or PCIe NIC
- DDR Controller
- One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default
with FSL refernce software is 2100MT/s
- 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB
- IFC/Local Bus
- One 2 GB NAND flash with ECC support, not as boot source
- CPLD of size 2K
- USB 3.0
- Two high speed USB 3.0 ports
- First USB 3.0 port configured as Host with Type-A connector
- Second USB 3.0 port configured as OTG with micro-AB connector
- SDHC/eMMC
- SDHC/eMMC slot via adaptor
- 4 I2C controllers
- Two SATA onboard connectors
- 2 UART
- JTAG support
- DSPI
- PROMJET support
- QSPI emulator support
- TDM riser support
QSPI flash memory map valid for both QDS and RDB
Image Flash Offset
RCW+PBI 0x00000000
Boot firmware (U-Boot) 0x00100000
Boot firmware Environment 0x00300000
PPA firmware 0x00400000
DPAA2 MC 0x00A00000
DPAA2 DPL 0x00D00000
DPAA2 DPC 0x00E00000
Kernel.itb 0x01000000

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/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/arch/soc.h>
#include <asm/arch/clock.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
if (ctrl_num > 1) {
printf("Not supported controller number %d\n", ctrl_num);
return;
}
if (!pdimm->n_ranks)
return;
/*
* we use identical timing for all slots. If needed, change the code
* to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
*/
pbsp = udimms[0];
/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm->n_ranks) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
goto found;
}
pbsp_highest = pbsp;
}
pbsp++;
}
if (pbsp_highest) {
printf("Error: board specific timing not found for %lu MT/s\n",
ddr_freq);
printf("Trying to use the highest speed (%u) parameters\n",
pbsp_highest->datarate_mhz_high);
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
} else {
panic("DIMM is not supported by this board");
}
found:
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
pbsp->wrlvl_ctl_3);
popts->half_strength_driver_enable = 0;
/*
* Write leveling override
*/
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
/* Enable ZQ calibration */
popts->zq_en = 1;
/* Enable DDR hashing */
popts->addr_hash = 1;
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
}
int fsl_initdram(void)
{
puts("Initializing DDR....using SPD\n");
gd->ram_size = fsl_ddr_sdram();
return 0;
}

49
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/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __LS1088A_DDR_H__
#define __LS1088A_DDR_H__
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
u32 rank_gb;
u32 clk_adjust;
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;
};
/*
* These tables contain all valid speeds we want to override with board
* specific parameters. datarate_mhz_high values need to be in ascending order
* for each n_ranks group.
*/
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
#if defined(CONFIG_TARGET_LS1088ARDB)
{2, 1666, 0, 8, 8, 0x090A0B0E, 0x0F10110D,},
{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
{2, 2300, 0, 8, 9, 0x0A0C0E11, 0x1214160F,},
{}
#elif defined(CONFIG_TARGET_LS1088AQDS)
{2, 1666, 0, 8, 8, 0x0A0A0C0E, 0x0F10110C,},
{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
{2, 2300, 0, 4, 9, 0x0A0C0D11, 0x1214150E,},
{}
#endif
};
static const struct board_specific_parameters *udimms[] = {
udimm0,
};
#endif

683
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/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#include <hwconfig.h>
#include <fsl_mdio.h>
#include <malloc.h>
#include <fm_eth.h>
#include <i2c.h>
#include <miiphy.h>
#include <fsl-mc/ldpaa_wriop.h>
#include "../common/qixis.h"
#include "ls1088a_qixis.h"
#define MC_BOOT_ENV_VAR "mcinitcmd"
#ifdef CONFIG_FSL_MC_ENET
#define SFP_TX 0
/* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks.
* Bank 1 -> Lanes A, B, C, D,
* Bank 2 -> Lanes A,B, C, D,
*/
/* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here
* means that the mapping must be determined dynamically, or that the lane
* maps to something other than a board slot.
*/
static u8 lane_to_slot_fsm1[] = {
0, 0, 0, 0, 0, 0, 0, 0
};
/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
* housed.
*/
static int xqsgii_riser_phy_addr[] = {
XQSGMII_CARD_PHY1_PORT0_ADDR,
XQSGMII_CARD_PHY2_PORT0_ADDR,
XQSGMII_CARD_PHY3_PORT0_ADDR,
XQSGMII_CARD_PHY4_PORT0_ADDR,
XQSGMII_CARD_PHY3_PORT2_ADDR,
XQSGMII_CARD_PHY1_PORT2_ADDR,
XQSGMII_CARD_PHY4_PORT2_ADDR,
XQSGMII_CARD_PHY2_PORT2_ADDR,
};
static int sgmii_riser_phy_addr[] = {
SGMII_CARD_PORT1_PHY_ADDR,
SGMII_CARD_PORT2_PHY_ADDR,
SGMII_CARD_PORT3_PHY_ADDR,
SGMII_CARD_PORT4_PHY_ADDR,
};
/* Slot2 does not have EMI connections */
#define EMI_NONE 0xFF
#define EMI1_RGMII1 0
#define EMI1_RGMII2 1
#define EMI1_SLOT1 2
static const char * const mdio_names[] = {
"LS1088A_QDS_MDIO0",
"LS1088A_QDS_MDIO1",
"LS1088A_QDS_MDIO2",
DEFAULT_WRIOP_MDIO2_NAME,
};
struct ls1088a_qds_mdio {
u8 muxval;
struct mii_dev *realbus;
};
static void sgmii_configure_repeater(int dpmac)
{
struct mii_dev *bus;
uint8_t a = 0xf;
int i, j, ret;
unsigned short value;
const char *dev = "LS1088A_QDS_MDIO2";
int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
int i2c_phy_addr = 0;
int phy_addr = 0;
uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
/* Set I2c to Slot 1 */
i2c_write(0x77, 0, 0, &a, 1);
switch (dpmac) {
case 1:
i2c_phy_addr = i2c_addr[1];
phy_addr = 4;
break;
case 2:
i2c_phy_addr = i2c_addr[0];
phy_addr = 0;
break;
case 3:
i2c_phy_addr = i2c_addr[3];
phy_addr = 0xc;
break;
case 7:
i2c_phy_addr = i2c_addr[2];
phy_addr = 8;
break;
}
/* Check the PHY status */
ret = miiphy_set_current_dev(dev);
if (ret > 0)
goto error;
bus = mdio_get_current_dev();
debug("Reading from bus %s\n", bus->name);
ret = miiphy_write(dev, phy_addr, 0x1f, 3);
if (ret > 0)
goto error;
mdelay(10);
ret = miiphy_read(dev, phy_addr, 0x11, &value);
if (ret > 0)
goto error;
mdelay(10);
if ((value & 0xfff) == 0x401) {
miiphy_write(dev, phy_addr, 0x1f, 0);
printf("DPMAC %d:PHY is ..... Configured\n", dpmac);
return;
}
for (i = 0; i < 4; i++) {
for (j = 0; j < 4; j++) {
a = 0x18;
i2c_write(i2c_phy_addr, 6, 1, &a, 1);
a = 0x38;
i2c_write(i2c_phy_addr, 4, 1, &a, 1);
a = 0x4;
i2c_write(i2c_phy_addr, 8, 1, &a, 1);
i2c_write(i2c_phy_addr, 0xf, 1,
&ch_a_eq[i], 1);
i2c_write(i2c_phy_addr, 0x11, 1,
&ch_a_ctl2[j], 1);
i2c_write(i2c_phy_addr, 0x16, 1,
&ch_b_eq[i], 1);
i2c_write(i2c_phy_addr, 0x18, 1,
&ch_b_ctl2[j], 1);
a = 0x14;
i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
a = 0xb5;
i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
a = 0x20;
i2c_write(i2c_phy_addr, 4, 1, &a, 1);
mdelay(100);
ret = miiphy_read(dev, phy_addr, 0x11, &value);
if (ret > 0)
goto error;
mdelay(100);
ret = miiphy_read(dev, phy_addr, 0x11, &value);
if (ret > 0)
goto error;
if ((value & 0xfff) == 0x401) {
printf("DPMAC %d :PHY is configured ",
dpmac);
printf("after setting repeater 0x%x\n",
value);
i = 5;
j = 5;
} else {
printf("DPMAC %d :PHY is failed to ",
dpmac);
printf("configure the repeater 0x%x\n", value);
}
}
}
miiphy_write(dev, phy_addr, 0x1f, 0);
error:
if (ret)
printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac);
return;
}
static void qsgmii_configure_repeater(int dpmac)
{
uint8_t a = 0xf;
int i, j;
int i2c_phy_addr = 0;
int phy_addr = 0;
int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
const char *dev = mdio_names[EMI1_SLOT1];
int ret = 0;
unsigned short value;
/* Set I2c to Slot 1 */
i2c_write(0x77, 0, 0, &a, 1);
switch (dpmac) {
case 7:
case 8:
case 9:
case 10:
i2c_phy_addr = i2c_addr[2];
phy_addr = 8;
break;
case 3:
case 4:
case 5:
case 6:
i2c_phy_addr = i2c_addr[3];
phy_addr = 0xc;
break;
}
/* Check the PHY status */
ret = miiphy_set_current_dev(dev);
ret = miiphy_write(dev, phy_addr, 0x1f, 3);
mdelay(10);
ret = miiphy_read(dev, phy_addr, 0x11, &value);
mdelay(10);
ret = miiphy_read(dev, phy_addr, 0x11, &value);
mdelay(10);
if ((value & 0xf) == 0xf) {
miiphy_write(dev, phy_addr, 0x1f, 0);
printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
return;
}
for (i = 0; i < 4; i++) {
for (j = 0; j < 4; j++) {
a = 0x18;
i2c_write(i2c_phy_addr, 6, 1, &a, 1);
a = 0x38;
i2c_write(i2c_phy_addr, 4, 1, &a, 1);
a = 0x4;
i2c_write(i2c_phy_addr, 8, 1, &a, 1);
i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
a = 0x14;
i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
a = 0xb5;
i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
a = 0x20;
i2c_write(i2c_phy_addr, 4, 1, &a, 1);
mdelay(100);
ret = miiphy_read(dev, phy_addr, 0x11, &value);
if (ret > 0)
goto error;
mdelay(1);
ret = miiphy_read(dev, phy_addr, 0x11, &value);
if (ret > 0)
goto error;
mdelay(10);
if ((value & 0xf) == 0xf) {
miiphy_write(dev, phy_addr, 0x1f, 0);
printf("DPMAC %d :PHY is ..... Configured\n",
dpmac);
return;
}
}
}
error:
printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
return;
}
static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval)
{
return mdio_names[muxval];
}
struct mii_dev *mii_dev_for_muxval(u8 muxval)
{
struct mii_dev *bus;
const char *name = ls1088a_qds_mdio_name_for_muxval(muxval);
if (!name) {
printf("No bus for muxval %x\n", muxval);
return NULL;
}
bus = miiphy_get_dev_by_name(name);
if (!bus) {
printf("No bus by name %s\n", name);
return NULL;
}
return bus;
}
static void ls1088a_qds_enable_SFP_TX(u8 muxval)
{
u8 brdcfg9;
brdcfg9 = QIXIS_READ(brdcfg[9]);
brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
QIXIS_WRITE(brdcfg[9], brdcfg9);
}
static void ls1088a_qds_mux_mdio(u8 muxval)
{
u8 brdcfg4;
if (muxval <= 5) {
brdcfg4 = QIXIS_READ(brdcfg[4]);
brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
QIXIS_WRITE(brdcfg[4], brdcfg4);
}
}
static int ls1088a_qds_mdio_read(struct mii_dev *bus, int addr,
int devad, int regnum)
{
struct ls1088a_qds_mdio *priv = bus->priv;
ls1088a_qds_mux_mdio(priv->muxval);
return priv->realbus->read(priv->realbus, addr, devad, regnum);
}
static int ls1088a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
int regnum, u16 value)
{
struct ls1088a_qds_mdio *priv = bus->priv;
ls1088a_qds_mux_mdio(priv->muxval);
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
}
static int ls1088a_qds_mdio_reset(struct mii_dev *bus)
{
struct ls1088a_qds_mdio *priv = bus->priv;
return priv->realbus->reset(priv->realbus);
}
static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval)
{
struct ls1088a_qds_mdio *pmdio;
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate ls1088a_qds MDIO bus\n");
return -1;
}
pmdio = malloc(sizeof(*pmdio));
if (!pmdio) {
printf("Failed to allocate ls1088a_qds private data\n");
free(bus);
return -1;
}
bus->read = ls1088a_qds_mdio_read;
bus->write = ls1088a_qds_mdio_write;
bus->reset = ls1088a_qds_mdio_reset;
sprintf(bus->name, ls1088a_qds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
if (!pmdio->realbus) {
printf("No bus with name %s\n", realbusname);
free(bus);
free(pmdio);
return -1;
}
pmdio->muxval = muxval;
bus->priv = pmdio;
return mdio_register(bus);
}
/*
* Initialize the dpmac_info array.
*
*/
static void initialize_dpmac_to_slot(void)
{
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
FSL_CHASSIS3_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
switch (serdes1_prtcl) {
case 0x12:
printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
serdes1_prtcl);
lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
break;
case 0x15:
case 0x1D:
printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
serdes1_prtcl);
lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
lane_to_slot_fsm1[2] = EMI_NONE;
lane_to_slot_fsm1[3] = EMI_NONE;
break;
case 0x1E:
printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
serdes1_prtcl);
lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
lane_to_slot_fsm1[3] = EMI_NONE;
break;
case 0x3A:
printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
serdes1_prtcl);
lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
lane_to_slot_fsm1[1] = EMI_NONE;
lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
break;
default:
printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
__func__, serdes1_prtcl);
break;
}
}
void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
{
struct mii_dev *bus;
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
FSL_CHASSIS3_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
int *riser_phy_addr;
char *env_hwconfig = env_get("hwconfig");
if (hwconfig_f("xqsgmii", env_hwconfig))
riser_phy_addr = &xqsgii_riser_phy_addr[0];
else
riser_phy_addr = &sgmii_riser_phy_addr[0];
switch (serdes1_prtcl) {
case 0x12:
case 0x15:
case 0x1E:
case 0x3A:
switch (dpmac_id) {
case 1:
wriop_set_phy_address(dpmac_id, riser_phy_addr[1]);
break;
case 2:
wriop_set_phy_address(dpmac_id, riser_phy_addr[0]);
break;
case 3:
wriop_set_phy_address(dpmac_id, riser_phy_addr[3]);
break;
case 7:
wriop_set_phy_address(dpmac_id, riser_phy_addr[2]);
break;
default:
printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id);
break;
}
break;
default:
printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
__func__, serdes1_prtcl);
return;
}
dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
bus = mii_dev_for_muxval(EMI1_SLOT1);
wriop_set_mdio(dpmac_id, bus);
}
void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
{
struct mii_dev *bus;
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
FSL_CHASSIS3_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
switch (serdes1_prtcl) {
case 0x1D:
case 0x1E:
switch (dpmac_id) {
case 3:
case 4:
case 5:
case 6:
wriop_set_phy_address(dpmac_id, dpmac_id + 9);
break;
case 7:
case 8:
case 9:
case 10:
wriop_set_phy_address(dpmac_id, dpmac_id + 1);
break;
}
dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
bus = mii_dev_for_muxval(EMI1_SLOT1);
wriop_set_mdio(dpmac_id, bus);
break;
default:
printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
serdes1_prtcl);
break;
}
}
void ls1088a_handle_phy_interface_xsgmii(int i)
{
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
FSL_CHASSIS3_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
switch (serdes1_prtcl) {
case 0x15:
case 0x1D:
case 0x1E:
wriop_set_phy_address(i, i + 26);
ls1088a_qds_enable_SFP_TX(SFP_TX);
break;
default:
printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
serdes1_prtcl);
break;
}
}
static void ls1088a_handle_phy_interface_rgmii(int dpmac_id)
{
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
struct mii_dev *bus;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
FSL_CHASSIS3_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
switch (dpmac_id) {
case 4:
wriop_set_phy_address(dpmac_id, RGMII_PHY1_ADDR);
dpmac_info[dpmac_id].board_mux = EMI1_RGMII1;
bus = mii_dev_for_muxval(EMI1_RGMII1);
wriop_set_mdio(dpmac_id, bus);
break;
case 5:
wriop_set_phy_address(dpmac_id, RGMII_PHY2_ADDR);
dpmac_info[dpmac_id].board_mux = EMI1_RGMII2;
bus = mii_dev_for_muxval(EMI1_RGMII2);
wriop_set_mdio(dpmac_id, bus);
break;
default:
printf("qds: WRIOP: Unsupported RGMII SerDes Protocol 0x%02x\n",
serdes1_prtcl);
break;
}
}
#endif
int board_eth_init(bd_t *bis)
{
int error = 0, i;
char *mc_boot_env_var;
#ifdef CONFIG_FSL_MC_ENET
struct memac_mdio_info *memac_mdio0_info;
char *env_hwconfig = env_get("hwconfig");
initialize_dpmac_to_slot();
memac_mdio0_info = (struct memac_mdio_info *)malloc(
sizeof(struct memac_mdio_info));
memac_mdio0_info->regs =
(struct memac_mdio_controller *)
CONFIG_SYS_FSL_WRIOP1_MDIO1;
memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the real MDIO1 bus */
fm_memac_mdio_init(bis, memac_mdio0_info);
/* Register the muxing front-ends to the MDIO buses */
ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);
ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2);
ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
switch (wriop_get_enet_if(i)) {
case PHY_INTERFACE_MODE_RGMII:
ls1088a_handle_phy_interface_rgmii(i);
break;
case PHY_INTERFACE_MODE_QSGMII:
ls1088a_handle_phy_interface_qsgmii(i);
break;
case PHY_INTERFACE_MODE_SGMII:
ls1088a_handle_phy_interface_sgmii(i);
break;
case PHY_INTERFACE_MODE_XGMII:
ls1088a_handle_phy_interface_xsgmii(i);
break;
default:
break;
if (i == 16)
i = NUM_WRIOP_PORTS;
}
}
mc_boot_env_var = env_get(MC_BOOT_ENV_VAR);
if (mc_boot_env_var)
run_command_list(mc_boot_env_var, -1, 0);
error = cpu_eth_init(bis);
if (hwconfig_f("xqsgmii", env_hwconfig)) {
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
switch (wriop_get_enet_if(i)) {
case PHY_INTERFACE_MODE_QSGMII:
qsgmii_configure_repeater(i);
break;
case PHY_INTERFACE_MODE_SGMII:
sgmii_configure_repeater(i);
break;
default:
break;
}
if (i == 16)
i = NUM_WRIOP_PORTS;
}
}
#endif
error = pci_eth_init(bis);
return error;
}

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/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <malloc.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <exports.h>
#include <asm/arch/fsl_serdes.h>
#include <fsl-mc/ldpaa_wriop.h>
DECLARE_GLOBAL_DATA_PTR;
#define MC_BOOT_ENV_VAR "mcinitcmd"
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
char *mc_boot_env_var;
int i, interface;
struct memac_mdio_info mdio_info;
struct mii_dev *dev;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct memac_mdio_controller *reg;
u32 srds_s1, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
FSL_CHASSIS3_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */
fm_memac_mdio_init(bis, &mdio_info);
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
/* Register the EMI 2 */
fm_memac_mdio_init(bis, &mdio_info);
switch (srds_s1) {
case 0x1D:
/*
* XFI does not need a PHY to work, but to avoid U-boot use
* default PHY address which is zero to a MAC when it found
* a MAC has no PHY address, we give a PHY address to XFI
* MAC error.
*/
wriop_set_phy_address(WRIOP1_DPMAC1, 0x0a);
wriop_set_phy_address(WRIOP1_DPMAC2, AQ_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC3, QSGMII1_PORT1_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC4, QSGMII1_PORT2_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC5, QSGMII1_PORT3_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC6, QSGMII1_PORT4_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC7, QSGMII2_PORT1_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC8, QSGMII2_PORT2_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC9, QSGMII2_PORT3_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC10, QSGMII2_PORT4_PHY_ADDR);
break;
default:
printf("SerDes1 protocol 0x%x is not supported on LS1088ARDB\n",
srds_s1);
break;
}
for (i = WRIOP1_DPMAC3; i <= WRIOP1_DPMAC10; i++) {
interface = wriop_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_QSGMII:
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
wriop_set_mdio(i, dev);
break;
default:
break;
}
}
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
wriop_set_mdio(WRIOP1_DPMAC2, dev);
mc_boot_env_var = env_get(MC_BOOT_ENV_VAR);
if (mc_boot_env_var)
run_command_list(mc_boot_env_var, -1, 0);
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}

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/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
#include <fsl_sec.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <libfdt.h>
#include <fsl-mc/fsl_mc.h>
#include <environment.h>
#include <asm/arch-fsl-layerscape/soc.h>
#include <asm/arch/ppa.h>
#include "../common/qixis.h"
#include "ls1088a_qixis.h"
DECLARE_GLOBAL_DATA_PTR;
unsigned long long get_qixis_addr(void)
{
unsigned long long addr;
if (gd->flags & GD_FLG_RELOC)
addr = QIXIS_BASE_PHYS;
else
addr = QIXIS_BASE_PHYS_EARLY;
/*
* IFC address under 256MB is mapped to 0x30000000, any address above
* is mapped to 0x5_10000000 up to 4GB.
*/
addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
return addr;
}
int checkboard(void)
{
char buf[64];
u8 sw;
static const char *const freq[] = {"100", "125", "156.25",
"100 separate SSCG"};
int clock;
#ifdef CONFIG_TARGET_LS1088AQDS
printf("Board: LS1088A-QDS, ");
#else
printf("Board: LS1088A-RDB, ");
#endif
sw = QIXIS_READ(arch);
printf("Board Arch: V%d, ", sw >> 4);
#ifdef CONFIG_TARGET_LS1088AQDS
printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
#else
printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
#endif
memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
#ifdef CONFIG_SD_BOOT
puts("SD card\n");
#endif
switch (sw) {
#ifdef CONFIG_TARGET_LS1088AQDS
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
printf("vBank: %d\n", sw);
break;
case 8:
puts("PromJet\n");
break;
case 15:
puts("IFCCard\n");
break;
case 14:
#else
case 0:
#endif
puts("QSPI:");
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
if (sw == 0 || sw == 4)
puts("0\n");
else if (sw == 1)
puts("1\n");
else
puts("EMU\n");
break;
default:
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
break;
}
#ifdef CONFIG_TARGET_LS1088AQDS
printf("FPGA: v%d (%s), build %d",
(int)QIXIS_READ(scver), qixis_read_tag(buf),
(int)qixis_read_minor());
/* the timestamp string contains "\n" at the end */
printf(" on %s", qixis_read_time(buf));
#else
printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
#endif
/*
* Display the actual SERDES reference clocks as configured by the
* dip switches on the board. Note that the SWx registers could
* technically be set to force the reference clocks to match the
* values that the SERDES expects (or vice versa). For now, however,
* we just display both values and hope the user notices when they
* don't match.
*/
puts("SERDES1 Reference : ");
sw = QIXIS_READ(brdcfg[2]);
clock = (sw >> 6) & 3;
printf("Clock1 = %sMHz ", freq[clock]);
clock = (sw >> 4) & 3;
printf("Clock2 = %sMHz", freq[clock]);
puts("\nSERDES2 Reference : ");
clock = (sw >> 2) & 3;
printf("Clock1 = %sMHz ", freq[clock]);
clock = (sw >> 0) & 3;
printf("Clock2 = %sMHz\n", freq[clock]);
return 0;
}
bool if_board_diff_clk(void)
{
#ifdef CONFIG_TARGET_LS1088AQDS
u8 diff_conf = QIXIS_READ(brdcfg[11]);
return diff_conf & 0x40;
#else
u8 diff_conf = QIXIS_READ(dutcfg[11]);
return diff_conf & 0x80;
#endif
}
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
switch (sysclk_conf & 0x0f) {
case QIXIS_SYSCLK_83:
return 83333333;
case QIXIS_SYSCLK_100:
return 100000000;
case QIXIS_SYSCLK_125:
return 125000000;
case QIXIS_SYSCLK_133:
return 133333333;
case QIXIS_SYSCLK_150:
return 150000000;
case QIXIS_SYSCLK_160:
return 160000000;
case QIXIS_SYSCLK_166:
return 166666666;
}
return 66666666;
}
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
if (if_board_diff_clk())
return get_board_sys_clk();
switch ((ddrclk_conf & 0x30) >> 4) {
case QIXIS_DDRCLK_100:
return 100000000;
case QIXIS_DDRCLK_125:
return 125000000;
case QIXIS_DDRCLK_133:
return 133333333;
}
return 66666666;
}
int select_i2c_ch_pca9547(u8 ch)
{
int ret;
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
}
return 0;
}
void board_retimer_init(void)
{
u8 reg;
/* Retimer is connected to I2C1_CH5 */
select_i2c_ch_pca9547(I2C_MUX_CH5);
/* Access to Control/Shared register */
reg = 0x0;
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
/* Read device revision and ID */
i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
debug("Retimer version id = 0x%x\n", reg);
/* Enable Broadcast. All writes target all channel register sets */
reg = 0x0c;
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
/* Reset Channel Registers */
i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
reg |= 0x4;
i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
/* Set data rate as 10.3125 Gbps */
reg = 0x90;
i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
reg = 0xb3;
i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
reg = 0x90;
i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
reg = 0xb3;
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
reg = 0xcd;
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
/* Select VCO Divider to full rate (000) */
i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
reg &= 0x0f;
reg |= 0x70;
i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
#ifdef CONFIG_TARGET_LS1088AQDS
/* Retimer is connected to I2C1_CH5 */
select_i2c_ch_pca9547(I2C_MUX_CH5);
/* Access to Control/Shared register */
reg = 0x0;
i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
/* Read device revision and ID */
i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
debug("Retimer version id = 0x%x\n", reg);
/* Enable Broadcast. All writes target all channel register sets */
reg = 0x0c;
i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
/* Reset Channel Registers */
i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
reg |= 0x4;
i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
/* Set data rate as 10.3125 Gbps */
reg = 0x90;
i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
reg = 0xb3;
i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
reg = 0x90;
i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
reg = 0xb3;
i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
reg = 0xcd;
i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
/* Select VCO Divider to full rate (000) */
i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
reg &= 0x0f;
reg |= 0x70;
i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
#endif
/*return the default channel*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
}
int board_init(void)
{
init_final_memctl_regs();
#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
board_retimer_init();
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif
#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
/* invert AQR105 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
return 0;
}
int board_early_init_f(void)
{
fsl_lsch3_early_init_f();
return 0;
}
void detail_board_ddr_info(void)
{
puts("\nDDR ");
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
}
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
return 0;
}
#endif
#ifdef CONFIG_FSL_MC_ENET
void fdt_fixup_board_enet(void *fdt)
{
int offset;
offset = fdt_path_offset(fdt, "/fsl-mc");
if (offset < 0)
offset = fdt_path_offset(fdt, "/fsl,dprc@0");
if (offset < 0) {
printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
__func__, offset);
return;
}
if (get_mc_boot_status() == 0)
fdt_status_okay(fdt, offset);
else
fdt_status_fail(fdt, offset);
}
#endif
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
int err, i;
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
ft_cpu_setup(blob, bd);
/* fixup DT for the two GPP DDR banks */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
base[i] = gd->bd->bi_dram[i].start;
size[i] = gd->bd->bi_dram[i].size;
}
#ifdef CONFIG_RESV_RAM
/* reduce size if reserved memory is within this bank */
if (gd->arch.resv_ram >= base[0] &&
gd->arch.resv_ram < base[0] + size[0])
size[0] = gd->arch.resv_ram - base[0];
else if (gd->arch.resv_ram >= base[1] &&
gd->arch.resv_ram < base[1] + size[1])
size[1] = gd->arch.resv_ram - base[1];
#endif
fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
err = fsl_mc_ldpaa_exit(bd);
if (err)
return err;
#endif
return 0;
}
#endif

39
board/freescale/ls1088a/ls1088a_qixis.h Normal file
View file

@ -0,0 +1,39 @@
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __LS1088AQDS_QIXIS_H__
#define __LS1088AQDS_QIXIS_H__
/* Definitions of QIXIS Registers for LS1088AQDS */
/* SYSCLK */
#define QIXIS_SYSCLK_66 0x0
#define QIXIS_SYSCLK_83 0x1
#define QIXIS_SYSCLK_100 0x2
#define QIXIS_SYSCLK_125 0x3
#define QIXIS_SYSCLK_133 0x4
#define QIXIS_SYSCLK_150 0x5
#define QIXIS_SYSCLK_160 0x6
#define QIXIS_SYSCLK_166 0x7
/* DDRCLK */
#define QIXIS_DDRCLK_66 0x0
#define QIXIS_DDRCLK_100 0x1
#define QIXIS_DDRCLK_125 0x2
#define QIXIS_DDRCLK_133 0x3
/* BRDCFG2 - SD clock*/
#define QIXIS_SDCLK1_100 0x0
#define QIXIS_SDCLK1_125 0x1
#define QIXIS_SDCLK1_165 0x2
#define QIXIS_SDCLK1_100_SP 0x3
#define BRDCFG4_EMISEL_MASK 0xE0
#define BRDCFG4_EMISEL_SHIFT 5
#define BRDCFG9_SFPTX_MASK 0x10
#define BRDCFG9_SFPTX_SHIFT 4
#endif

7
board/freescale/ls2080aqds/ls2080aqds.c
View file

@ -226,15 +226,14 @@ int board_init(void)
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
rtc_enable_32khz_output();
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
return 0;
}

5
board/freescale/ls2080ardb/MAINTAINERS
View file

@ -21,3 +21,8 @@ LS2080A_SECURE_BOOT BOARD
M: Saksham Jain <saksham.jain@nxp.freescale.com>
S: Maintained
F: configs/ls2080ardb_SECURE_BOOT_defconfig
LS2088A_QSPI_SECURE_BOOT BOARD
M: Udit Agarwal <udit.agarwal@nxp.com>
S: Maintained
F: configs/ls2088ardb_qspi_SECURE_BOOT_defconfig

4
board/freescale/ls2080ardb/ls2080ardb.c
View file

@ -218,6 +218,10 @@ int board_init(void)
#ifdef CONFIG_FSL_QIXIS
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif

8
cmd/spl.c
View file

@ -109,12 +109,12 @@ static int spl_export(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
c = find_cmd_tbl(argv[1], &cmd_spl_export_sub[0],
ARRAY_SIZE(cmd_spl_export_sub));
if ((c) && ((int)c->cmd <= SPL_EXPORT_LAST)) {
if ((c) && ((long)c->cmd <= SPL_EXPORT_LAST)) {
argc -= 2;
argv += 2;
if (call_bootm(argc, argv, subcmd_list[(int)c->cmd]))
if (call_bootm(argc, argv, subcmd_list[(long)c->cmd]))
return -1;
switch ((int)c->cmd) {
switch ((long)c->cmd) {
#ifdef CONFIG_OF_LIBFDT
case SPL_EXPORT_FDT:
printf("Argument image is now in RAM: 0x%p\n",
@ -153,7 +153,7 @@ static int do_spl(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
c = find_cmd_tbl(argv[1], &cmd_spl_sub[0], ARRAY_SIZE(cmd_spl_sub));
if (c) {
cmd = (int)c->cmd;
cmd = (long)c->cmd;
switch (cmd) {
case SPL_EXPORT:
argc--;

96
common/spl/spl_fit.c
View file

@ -11,6 +11,10 @@
#include <libfdt.h>
#include <spl.h>
#ifndef CONFIG_SYS_BOOTM_LEN
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
#endif
/**
* spl_fit_get_image_node(): By using the matching configuration subnode,
* retrieve the name of an image, specified by a property name and an index
@ -128,41 +132,79 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
void *fit, ulong base_offset, int node,
struct spl_image_info *image_info)
{
ulong offset;
int offset;
size_t length;
int len;
ulong load_addr, load_ptr;
void *src;
ulong overhead;
int nr_sectors;
int align_len = ARCH_DMA_MINALIGN - 1;
uint8_t image_comp = -1, type = -1;
const void *data;
offset = fdt_getprop_u32(fit, node, "data-offset");
if (offset == FDT_ERROR)
return -ENOENT;
offset += base_offset;
length = fdt_getprop_u32(fit, node, "data-size");
if (length == FDT_ERROR)
return -ENOENT;
load_addr = fdt_getprop_u32(fit, node, "load");
if (load_addr == FDT_ERROR && image_info)
if (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP)) {
if (fit_image_get_comp(fit, node, &image_comp))
puts("Cannot get image compression format.\n");
else
debug("%s ", genimg_get_comp_name(image_comp));
if (fit_image_get_type(fit, node, &type))
puts("Cannot get image type.\n");
else
debug("%s ", genimg_get_type_name(type));
}
if (fit_image_get_load(fit, node, &load_addr))
load_addr = image_info->load_addr;
if (!fit_image_get_data_offset(fit, node, &offset)) {
/* External data */
offset += base_offset;
if (fit_image_get_data_size(fit, node, &len))
return -ENOENT;
load_ptr = (load_addr + align_len) & ~align_len;
length = len;
overhead = get_aligned_image_overhead(info, offset);
nr_sectors = get_aligned_image_size(info, length, offset);
if (info->read(info, sector + get_aligned_image_offset(info, offset),
if (info->read(info,
sector + get_aligned_image_offset(info, offset),
nr_sectors, (void *)load_ptr) != nr_sectors)
return -EIO;
debug("image: dst=%lx, offset=%lx, size=%lx\n", load_ptr, offset,
(unsigned long)length);
debug("External data: dst=%lx, offset=%x, size=%lx\n",
load_ptr, offset, (unsigned long)length);
src = (void *)load_ptr + overhead;
} else {
/* Embedded data */
if (fit_image_get_data(fit, node, &data, &length)) {
puts("Cannot get image data/size\n");
return -ENOENT;
}
debug("Embedded data: dst=%lx, size=%lx\n", load_addr,
(unsigned long)length);
src = (void *)data;
}
#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
board_fit_image_post_process(&src, &length);
#endif
if (IS_ENABLED(CONFIG_SPL_OS_BOOT) &&
IS_ENABLED(CONFIG_SPL_GZIP) &&
image_comp == IH_COMP_GZIP &&
type == IH_TYPE_KERNEL) {
if (gunzip((void *)load_addr, CONFIG_SYS_BOOTM_LEN,
src, &length)) {
puts("Uncompressing error\n");
return -EIO;
}
} else {
memcpy((void *)load_addr, src, length);
}
if (image_info) {
image_info->load_addr = load_addr;
@ -180,13 +222,16 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
ulong size;
unsigned long count;
struct spl_image_info image_info;
int node, images, ret;
bool boot_os = false;
int node = -1;
int images, ret;
int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
int index = 0;
/*
* Figure out where the external images start. This is the base for the
* data-offset properties in each image.
* For FIT with external data, figure out where the external images
* start. This is the base for the data-offset properties in each
* image.
*/
size = fdt_totalsize(fit);
size = (size + 3) & ~3;
@ -205,6 +250,9 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
*
* In fact the FIT has its own load address, but we assume it cannot
* be before CONFIG_SYS_TEXT_BASE.
*
* For FIT with data embedded, data is loaded as part of FIT image.
* For FIT with external data, data is not loaded in this step.
*/
fit = (void *)((CONFIG_SYS_TEXT_BASE - size - info->bl_len -
align_len) & ~align_len);
@ -222,7 +270,16 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
return -1;
}
#ifdef CONFIG_SPL_OS_BOOT
/* Find OS image first */
node = spl_fit_get_image_node(fit, images, FIT_KERNEL_PROP, 0);
if (node < 0)
debug("No kernel image.\n");
else
boot_os = true;
#endif
/* find the U-Boot image */
if (node < 0)
node = spl_fit_get_image_node(fit, images, "firmware", 0);
if (node < 0) {
debug("could not find firmware image, trying loadables...\n");
@ -245,8 +302,14 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
if (ret)
return ret;
#ifdef CONFIG_SPL_OS_BOOT
if (!fit_image_get_os(fit, node, &spl_image->os))
debug("Image OS is %s\n", genimg_get_os_name(spl_image->os));
#else
spl_image->os = IH_OS_U_BOOT;
#endif
if (!boot_os) {
/* Figure out which device tree the board wants to use */
node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, 0);
if (node < 0) {
@ -263,6 +326,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
&image_info);
if (ret < 0)
return ret;
}
/* Now check if there are more images for us to load */
for (; ; index++) {

33
configs/ls1088aqds_qspi_defconfig Normal file
View file

@ -0,0 +1,33 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1088AQDS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_FSL_LS_PPA=y

33
configs/ls1088ardb_qspi_defconfig Normal file
View file

@ -0,0 +1,33 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1088ARDB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_FSL_LS_PPA=y

48
configs/ls2088ardb_qspi_SECURE_BOOT_defconfig Normal file
View file

@ -0,0 +1,48 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2080ARDB=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_QSPI_BOOT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=10
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GREPENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SECURE_BOOT=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y

7
doc/uImage.FIT/multi_spl.its
View file

@ -4,6 +4,13 @@
* (Bogus) example FIT image description file demonstrating the usage
* of multiple images loaded by the SPL.
* Several binaries will be loaded at their respective load addresses.
*
* For booting U-Boot, "firmware" is searched first. If not found, "loadables"
* is used to identify images to be loaded into memory. If falcon boot is
* enabled, "kernel" is searched first. If not found, it falls back to the
* same flow as booting U-Boot. Changing image type will result skipping
* specific image.
*
* Finally the one image specifying an entry point will be entered by the SPL.
*/

4
doc/uImage.FIT/source_file_format.txt
View file

@ -288,6 +288,10 @@ The 'data-offset' property can be substituted with 'data-position', which
defines an absolute position or address as the offset. This is helpful when
booting U-Boot proper before performing relocation.
Normal kernel FIT image has data embedded within FIT structure. U-Boot image
for SPL boot has external data. Existence of 'data-offset' can be used to
identify which format is used.
9) Examples
-----------

2
drivers/ddr/fsl/util.c
View file

@ -390,7 +390,7 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
void remove_unused_controllers(fsl_ddr_info_t *info)
{
#ifdef CONFIG_FSL_LSCH3
#ifdef CONFIG_SYS_FSL_HAS_CCN504
int i;
u64 nodeid;
void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);

11
drivers/net/fsl-mc/mc.c
View file

@ -800,12 +800,19 @@ int get_dpl_apply_status(void)
return mc_dpl_applied;
}
/**
/*
* Return the MC address of private DRAM block.
* As per MC design document, MC initial base address
* should be least significant 512MB address of MC private
* memory, i.e. address should point to end address masked
* with 512MB offset in private DRAM block.
*/
u64 mc_get_dram_addr(void)
{
return gd->arch.resv_ram;
size_t mc_ram_size = mc_get_dram_block_size();
return (gd->arch.resv_ram + mc_ram_size - 1) &
MC_RAM_BASE_ADDR_ALIGNMENT_MASK;
}
/**

1
drivers/net/ldpaa_eth/Makefile
View file

@ -7,3 +7,4 @@
obj-y += ldpaa_wriop.o
obj-y += ldpaa_eth.o
obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o
obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o

9
drivers/net/ldpaa_eth/ldpaa_wriop.c
View file

@ -37,6 +37,15 @@ void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl)
}
}
void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if)
{
dpmac_info[dpmac_id].enabled = 1;
dpmac_info[dpmac_id].id = dpmac_id;
dpmac_info[dpmac_id].phy_addr = -1;
dpmac_info[dpmac_id].enet_if = enet_if;
}
/*TODO what it do */
static int wriop_dpmac_to_index(int dpmac_id)
{

114
drivers/net/ldpaa_eth/ls1088a.c Normal file
View file

@ -0,0 +1,114 @@
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <phy.h>
#include <fsl-mc/ldpaa_wriop.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
u32 dpmac_to_devdisr[] = {
[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
[WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
[WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
[WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
[WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
[WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
[WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
[WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
[WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
[WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
};
static int is_device_disabled(int dpmac_id)
{
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
u32 devdisr2 = in_le32(&gur->devdisr2);
return dpmac_to_devdisr[dpmac_id] & devdisr2;
}
void wriop_dpmac_disable(int dpmac_id)
{
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
}
void wriop_dpmac_enable(int dpmac_id)
{
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
}
phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
{
enum srds_prtcl;
if (is_device_disabled(dpmac_id + 1))
return PHY_INTERFACE_MODE_NONE;
switch (lane_prtcl) {
case SGMII1:
case SGMII2:
case SGMII3:
case SGMII7:
return PHY_INTERFACE_MODE_SGMII;
}
if (lane_prtcl >= XFI1 && lane_prtcl <= XFI2)
return PHY_INTERFACE_MODE_XGMII;
if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_B)
return PHY_INTERFACE_MODE_QSGMII;
return PHY_INTERFACE_MODE_NONE;
}
void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
{
switch (lane_prtcl) {
case QSGMII_A:
wriop_init_dpmac(sd, 3, (int)lane_prtcl);
wriop_init_dpmac(sd, 4, (int)lane_prtcl);
wriop_init_dpmac(sd, 5, (int)lane_prtcl);
wriop_init_dpmac(sd, 6, (int)lane_prtcl);
break;
case QSGMII_B:
wriop_init_dpmac(sd, 7, (int)lane_prtcl);
wriop_init_dpmac(sd, 8, (int)lane_prtcl);
wriop_init_dpmac(sd, 9, (int)lane_prtcl);
wriop_init_dpmac(sd, 10, (int)lane_prtcl);
break;
}
}
#ifdef CONFIG_SYS_FSL_HAS_RGMII
void fsl_rgmii_init(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 ec;
#ifdef CONFIG_SYS_FSL_EC1
ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1])
& FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK;
ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;
if (!ec)
wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII);
#endif
#ifdef CONFIG_SYS_FSL_EC2
ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1])
& FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK;
ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;
if (!ec)
wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII);
#endif
}
#endif

2
drivers/qe/qe.c
View file

@ -225,7 +225,7 @@ void u_qe_init(void)
flush_cache((ulong)addr, cnt * 512);
}
#endif
u_qe_upload_firmware(addr);
if (!u_qe_upload_firmware(addr))
out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
free(addr);

205
include/configs/ls1088a_common.h Normal file
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@ -0,0 +1,205 @@
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __LS1088_COMMON_H
#define __LS1088_COMMON_H
#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_MP
#include <asm/arch/stream_id_lsch3.h>
#include <asm/arch/config.h>
#include <asm/arch/soc.h>
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
/* Link Definitions */
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_TEXT_BASE 0x20100000
#else
#define CONFIG_SYS_TEXT_BASE 0x30100000
#endif
#define CONFIG_SUPPORT_RAW_INITRD
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
/*
* SMP Definitinos
*/
#define CPU_RELEASE_ADDR secondary_boot_func
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#endif
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* IFC */
#define CONFIG_FSL_IFC
/*
* During booting, IFC is mapped at the region of 0x30000000.
* But this region is limited to 256MB. To accommodate NOR, promjet
* and FPGA. This region is divided as below:
* 0x30000000 - 0x37ffffff : 128MB : NOR flash
* 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
* 0x3C000000 - 0x40000000 : 64MB : FPGA etc
*
* To accommodate bigger NOR flash and other devices, we will map IFC
* chip selects to as below:
* 0x5_1000_0000..0x5_1fff_ffff Memory Hole
* 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
* 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
* 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
* 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
*
* For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
* CONFIG_SYS_FLASH_BASE has the final address (core view)
* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
* CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
*/
#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
#ifndef __ASSEMBLY__
unsigned long long get_qixis_addr(void);
#endif
#define QIXIS_BASE get_qixis_addr()
#define QIXIS_BASE_PHYS 0x20000000
#define QIXIS_BASE_PHYS_EARLY 0xC000000
#define CONFIG_SYS_NAND_BASE 0x530000000ULL
#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
/* MC firmware */
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
/*
* Carve out a DDR region which will not be used by u-boot/Linux
*
* It will be used by MC and Debug Server. The MC region must be
* 512MB aligned, so the min size to hide is 512MB.
*/
#if defined(CONFIG_FSL_MC_ENET)
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
#endif
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
/* Command line configuration */
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_CACHE
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
/* #define CONFIG_DISPLAY_CPUINFO */
/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x80100000\0" \
"kernel_addr=0x100000\0" \
"ramdisk_addr=0x800000\0" \
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
"kernel_start=0x581000000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \
"console=ttyAMA0,38400n8\0" \
"mcinitcmd=fsl_mc start mc 0x580a00000" \
" 0x580e00000 \0"
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
"earlycon=uart8250,mmio,0x21c0500 " \
"ramdisk_size=0x3000000 default_hugepagesz=2m" \
" hugepagesz=2m hugepages=256"
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
"sf read 0x80200000 0xd00000 0x100000;"\
" fsl_mc apply dpl 0x80200000 &&" \
" sf read $kernel_load $kernel_start" \
" $kernel_size && bootm $kernel_load"
#else /* NOR BOOT*/
#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
" cp.b $kernel_start $kernel_load" \
" $kernel_size && bootm $kernel_load"
#endif
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS 64 /* max command args */
#define CONFIG_PANIC_HANG /* do not reset board on panic */
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#endif /* __LS1088_COMMON_H */

414
include/configs/ls1088aqds.h Normal file
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@ -0,0 +1,414 @@
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __LS1088A_QDS_H
#define __LS1088A_QDS_H
#include "ls1088a_common.h"
#define CONFIG_DISPLAY_BOARDINFO_LATE
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x40000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x20000
#endif
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_QIXIS_I2C_ACCESS
#define SYS_NO_FLASH
#undef CONFIG_CMD_IMLS
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#else
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#endif
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_DDR_SPD
#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
/*
* IFC Definitions
*/
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
#define CONFIG_SYS_NOR0_CSPR \
(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR0_CSPR_EARLY \
(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR1_CSPR \
(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EARLY \
(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
FTIM0_NOR_TEADC(0x5) | \
FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
FTIM1_NOR_TRAD_NOR(0x1a) |\
FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
FTIM2_NOR_TCH(0x4) | \
FTIM2_NOR_TWPH(0x0E) | \
FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3 0x04000000
#define CONFIG_SYS_IFC_CCR 0x01000000
#ifndef SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif
#endif
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_FSL_QIXIS
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 6
#define QIXIS_QMAP_MASK 0xe0
#define QIXIS_QMAP_SHIFT 5
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SHIFT 0
#define QIXIS_LBMAP_DFLTBANK 0x0e
#define QIXIS_LBMAP_ALTBANK 0x2e
#define QIXIS_LBMAP_SD 0x00
#define QIXIS_LBMAP_SD_QSPI 0x0e
#define QIXIS_LBMAP_QSPI 0x0e
#define QIXIS_RCW_SRC_SD 0x40
#define QIXIS_RCW_SRC_QSPI 0x62
#define QIXIS_RST_CTL_RESET 0x41
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_RST_FORCE_MEM 0x01
#define QIXIS_STAT_PRES1 0xb
#define QIXIS_SDID_MASK 0x07
#define QIXIS_ESDHC_NO_ADAPTER 0x7
#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
#else
#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
#endif
/* QIXIS Timing parameters*/
#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
FTIM2_GPCM_TCH(0xf) | \
FTIM2_GPCM_TWP(0x3E))
#define SYS_FPGA_CS_FTIM3 0x0
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_CSPR3_FINAL CONFIG_SYS_FPGA_CSPR_FINAL
#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_CS_FTIM0
#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_CS_FTIM1
#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_CS_FTIM2
#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_CS_FTIM3
#endif
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
/*
* I2C bus multiplexer
*/
#define I2C_MUX_PCA_ADDR_PRI 0x77
#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
#define I2C_RETIMER_ADDR 0x18
#define I2C_RETIMER_ADDR2 0x19
#define I2C_MUX_CH_DEFAULT 0x8
#define I2C_MUX_CH5 0xD
/*
* RTC configuration
*/
#define RTC
#define CONFIG_RTC_PCF8563 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
#define CONFIG_CMD_DATE
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/* QSPI device */
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE (1 << 26)
#define FSL_QSPI_FLASH_NUM 2
#endif
#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_SST
#define CONFIG_SPI_FLASH_EON
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SF_DEFAULT_BUS 1
#define CONFIG_SF_DEFAULT_CS 0
#endif
#endif
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_FSL_MEMAC
/* MMC */
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
/* Initial environment variables */
#if defined(CONFIG_QSPI_BOOT)
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x90100000\0" \
"kernel_addr=0x100000\0" \
"ramdisk_addr=0x800000\0" \
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
"kernel_start=0x1000000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \
"mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
"sf read 0x80100000 0xE00000 0x100000;" \
"fsl_mc start mc 0x80000000 0x80100000\0" \
"mcmemsize=0x70000000 \0"
#else /* NOR BOOT */
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x90100000\0" \
"kernel_addr=0x100000\0" \
"ramdisk_addr=0x800000\0" \
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
"kernel_start=0x1000000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \
"mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
"mcmemsize=0x70000000 \0"
#endif
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_FSL_MEMAC
#define CONFIG_PHYLIB
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_TERANETICS
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
#define CONFIG_MII /* MII PHY management */
#define CONFIG_ETHPRIME "DPMAC1@xgmii"
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
#undef CONFIG_CMDLINE_EDITING
#include <config_distro_defaults.h>
#define BOOT_TARGET_DEVICES(func) \
func(USB, usb, 0) \
func(MMC, mmc, 0) \
func(SCSI, scsi, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#include <asm/fsl_secure_boot.h>
#endif /* __LS1088A_QDS_H */

317
include/configs/ls1088ardb.h Normal file
View file

@ -0,0 +1,317 @@
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __LS1088A_RDB_H
#define __LS1088A_RDB_H
#include "ls1088a_common.h"
#define CONFIG_DISPLAY_BOARDINFO_LATE
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x40000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x20000
#endif
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_QIXIS_I2C_ACCESS
#define SYS_NO_FLASH
#undef CONFIG_CMD_IMLS
#endif
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
#define CONFIG_DDR_SPD
#ifdef CONFIG_EMU
#define CONFIG_SYS_FSL_DDR_EMU
#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
#else
#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
#define CONFIG_SYS_NOR0_CSPR \
(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR0_CSPR_EARLY \
(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
FTIM0_NOR_TEADC(0x1) | \
FTIM0_NOR_TEAHC(0x1))
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
FTIM1_NOR_TRAD_NOR(0x1))
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
FTIM2_NOR_TCH(0x0) | \
FTIM2_NOR_TWP(0x1))
#define CONFIG_SYS_NOR_FTIM3 0x04000000
#define CONFIG_SYS_IFC_CCR 0x01000000
#ifndef SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#endif
#endif
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_FSL_QIXIS
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 2
#define QIXIS_QMAP_MASK 0xe0
#define QIXIS_QMAP_SHIFT 5
#define QIXIS_LBMAP_MASK 0x1f
#define QIXIS_LBMAP_SHIFT 5
#define QIXIS_LBMAP_DFLTBANK 0x00
#define QIXIS_LBMAP_ALTBANK 0x20
#define QIXIS_LBMAP_SD 0x00
#define QIXIS_LBMAP_SD_QSPI 0x00
#define QIXIS_LBMAP_QSPI 0x00
#define QIXIS_RCW_SRC_SD 0x40
#define QIXIS_RCW_SRC_QSPI 0x62
#define QIXIS_RST_CTL_RESET 0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_RST_FORCE_MEM 0x01
#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
/* QIXIS Timing parameters*/
#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
FTIM2_GPCM_TCH(0xf) | \
FTIM2_GPCM_TWP(0x3E))
#define SYS_FPGA_CS_FTIM3 0x0
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
#endif
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
/*
* I2C bus multiplexer
*/
#define I2C_MUX_PCA_ADDR_PRI 0x77
#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
#define I2C_RETIMER_ADDR 0x18
#define I2C_MUX_CH_DEFAULT 0x8
#define I2C_MUX_CH5 0xD
/*
* RTC configuration
*/
#define RTC
#define CONFIG_RTC_PCF8563 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
#define CONFIG_CMD_DATE
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/* QSPI device */
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE (1 << 26)
#define FSL_QSPI_FLASH_NUM 2
#endif
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_FSL_MEMAC
/* Initial environment variables */
#if defined(CONFIG_QSPI_BOOT)
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x90100000\0" \
"kernel_addr=0x100000\0" \
"ramdisk_addr=0x800000\0" \
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
"kernel_start=0x1000000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \
"mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
"sf read 0x80100000 0xE00000 0x100000;" \
"fsl_mc start mc 0x80000000 0x80100000\0" \
"mcmemsize=0x70000000 \0"
#endif
/* MAC/PHY configuration */
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_AQUANTIA
#define AQ_PHY_ADDR1 0x00
#define AQR105_IRQ_MASK 0x00000004
#define QSGMII1_PORT1_PHY_ADDR 0x0c
#define QSGMII1_PORT2_PHY_ADDR 0x0d
#define QSGMII1_PORT3_PHY_ADDR 0x0e
#define QSGMII1_PORT4_PHY_ADDR 0x0f
#define QSGMII2_PORT1_PHY_ADDR 0x1c
#define QSGMII2_PORT2_PHY_ADDR 0x1d
#define QSGMII2_PORT3_PHY_ADDR 0x1e
#define QSGMII2_PORT4_PHY_ADDR 0x1f
#define CONFIG_MII
#define CONFIG_ETHPRIME "DPMAC1@xgmii"
#define CONFIG_PHY_GIGE
#endif
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#undef CONFIG_CMDLINE_EDITING
#include <config_distro_defaults.h>
#define BOOT_TARGET_DEVICES(func) \
func(USB, usb, 0) \
func(MMC, mmc, 0) \
func(SCSI, scsi, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#include <asm/fsl_secure_boot.h>
#endif /* __LS1088A_RDB_H */

2
include/fsl-mc/ldpaa_wriop.h
View file

@ -69,4 +69,6 @@ void wriop_dpmac_disable(int);
void wriop_dpmac_enable(int);
phy_interface_t wriop_dpmac_enet_if(int, int);
void wriop_init_dpmac_qsgmii(int, int);
void wriop_init_rgmii(void);
void wriop_init_dpmac_enet_if(int , phy_interface_t);
#endif /* __LDPAA_WRIOP_H */

51
include/fsl_immap.h
View file

@ -133,4 +133,55 @@ struct ccsr_ddr {
u8 res_e5c[164];
u32 debug[64]; /* debug_1 to debug_64 */
};
#ifdef CONFIG_SYS_FSL_HAS_CCI400
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
#define CCI400_CTRLORD_EN_BARRIER 0
#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
#define CCI400_SNOOP_REQ_EN 0x00000001
/* CCI-400 registers */
struct ccsr_cci400 {
u32 ctrl_ord; /* Control Override */
u32 spec_ctrl; /* Speculation Control */
u32 secure_access; /* Secure Access */
u32 status; /* Status */
u32 impr_err; /* Imprecise Error */
u8 res_14[0x100 - 0x14];
u32 pmcr; /* Performance Monitor Control */
u8 res_104[0xfd0 - 0x104];
u32 pid[8]; /* Peripheral ID */
u32 cid[4]; /* Component ID */
struct {
u32 snoop_ctrl; /* Snoop Control */
u32 sha_ord; /* Shareable Override */
u8 res_1008[0x1100 - 0x1008];
u32 rc_qos_ord; /* read channel QoS Value Override */
u32 wc_qos_ord; /* read channel QoS Value Override */
u8 res_1108[0x110c - 0x1108];
u32 qos_ctrl; /* QoS Control */
u32 max_ot; /* Max OT */
u8 res_1114[0x1130 - 0x1114];
u32 target_lat; /* Target Latency */
u32 latency_regu; /* Latency Regulation */
u32 qos_range; /* QoS Range */
u8 res_113c[0x2000 - 0x113c];
} slave[5]; /* Slave Interface */
u8 res_6000[0x9004 - 0x6000];
u32 cycle_counter; /* Cycle counter */
u32 count_ctrl; /* Count Control */
u32 overflow_status; /* Overflow Flag Status */
u8 res_9010[0xa000 - 0x9010];
struct {
u32 event_select; /* Event Select */
u32 event_count; /* Event Count */
u32 counter_ctrl; /* Counter Control */
u32 overflow_status; /* Overflow Flag Status */
u8 res_a010[0xb000 - 0xa010];
} pcounter[4]; /* Performance Counter */
u8 res_e004[0x10000 - 0xe004];
};
#endif
#endif /* __FSL_IMMAP_H */

12
lib/Kconfig
View file

@ -176,6 +176,18 @@ config LZO
bool "Enable LZO decompression support"
help
This enables support for LZO compression algorithm.r
config SPL_GZIP
bool "Enable gzip decompression support for SPL build"
select SPL_ZLIB
help
This enables support for GZIP compression altorithm for SPL boot.
config SPL_ZLIB
bool
help
This enables compression lib for SPL boot.
endmenu
config ERRNO_STR

5
lib/Makefile
View file

@ -11,7 +11,6 @@ obj-$(CONFIG_EFI) += efi/
obj-$(CONFIG_EFI_LOADER) += efi_loader/
obj-$(CONFIG_LZMA) += lzma/
obj-$(CONFIG_LZO) += lzo/
obj-$(CONFIG_ZLIB) += zlib/
obj-$(CONFIG_BZIP2) += bzip2/
obj-$(CONFIG_TIZEN) += tizen/
obj-$(CONFIG_FIT) += libfdt/
@ -26,7 +25,6 @@ obj-y += crc16.o
obj-$(CONFIG_ERRNO_STR) += errno_str.o
obj-$(CONFIG_FIT) += fdtdec_common.o
obj-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o
obj-$(CONFIG_GZIP) += gunzip.o
obj-$(CONFIG_GZIP_COMPRESSED) += gzip.o
obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o
obj-y += initcall.o
@ -49,6 +47,9 @@ obj-$(CONFIG_RSA) += rsa/
obj-$(CONFIG_SHA1) += sha1.o
obj-$(CONFIG_SHA256) += sha256.o
obj-$(CONFIG_$(SPL_)ZLIB) += zlib/
obj-$(CONFIG_$(SPL_)GZIP) += gunzip.o
obj-$(CONFIG_$(SPL_TPL_)SAVEENV) += qsort.o
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/
ifneq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy)

1
scripts/config_whitelist.txt
View file

@ -2433,7 +2433,6 @@ CONFIG_SYS_CACHE_STASHING
CONFIG_SYS_CADMUS_BASE_REG
CONFIG_SYS_CBSIZE
CONFIG_SYS_CCCR
CONFIG_SYS_CCI400_ADDR
CONFIG_SYS_CCSRBAR
CONFIG_SYS_CCSRBAR_PHYS
CONFIG_SYS_CCSRBAR_PHYS_HIGH

2
tools/pblimage.c
View file

@ -293,7 +293,7 @@ int pblimage_check_params(struct image_tool_params *params)
pbi_crc_cmd2 = 0;
pbl_cmd_initaddr = params->addr & PBL_ADDR_24BIT_MASK;
pbl_cmd_initaddr |= PBL_ACS_CONT_CMD;
pbl_cmd_initaddr |= uboot_size;
pbl_cmd_initaddr += uboot_size;
pbl_end_cmd[0] = 0x09610000;
pbl_end_cmd[1] = 0x00000000;
pbl_end_cmd[2] = 0x096100c0;