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crypto: aspeed: Add AST2600 ACRY support
ACRY is designed to accelerate ECC/RSA digital signature generation and verification. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
This commit is contained in:
Chia-Wei Wang
Tom Rini
parent
af6451187c
commit
89c36cca0b
4 changed files with 210 additions and 1 deletions
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@ -8,3 +8,13 @@ config ASPEED_HACE
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Enabling this allows the use of SHA operations in hardware without
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requiring the SHA software implementations. It also improves performance
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and saves code size.
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config ASPEED_ACRY
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bool "ASPEED RSA and ECC Engine"
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depends on ASPEED_AST2600
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help
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Select this option to enable a driver for using the RSA/ECC engine in
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the ASPEED BMC SoCs.
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Enabling this allows the use of RSA/ECC operations in hardware without requiring the
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software implementations. It also improves performance and saves code size.
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@ -1 +1,2 @@
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obj-$(CONFIG_ASPEED_HACE) += aspeed_hace.o
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obj-$(CONFIG_ASPEED_ACRY) += aspeed_acry.o
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190
drivers/crypto/aspeed/aspeed_acry.c
Normal file
190
drivers/crypto/aspeed/aspeed_acry.c
Normal file
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@ -0,0 +1,190 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2021 ASPEED Technology Inc.
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*/
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#include <config.h>
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <asm/types.h>
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#include <asm/io.h>
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#include <dm/device.h>
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#include <dm/fdtaddr.h>
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#include <linux/delay.h>
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#include <u-boot/rsa-mod-exp.h>
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/* ACRY register offsets */
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#define ACRY_CTRL1 0x00
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#define ACRY_CTRL1_RSA_DMA BIT(1)
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#define ACRY_CTRL1_RSA_START BIT(0)
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#define ACRY_CTRL2 0x44
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#define ACRY_CTRL3 0x48
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#define ACRY_CTRL3_SRAM_AHB_ACCESS BIT(8)
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#define ACRY_CTRL3_ECC_RSA_MODE_MASK GENMASK(5, 4)
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#define ACRY_CTRL3_ECC_RSA_MODE_SHIFT 4
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#define ACRY_DMA_DRAM_SADDR 0x4c
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#define ACRY_DMA_DMEM_TADDR 0x50
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#define ACRY_DMA_DMEM_TADDR_LEN_MASK GENMASK(15, 0)
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#define ACRY_DMA_DMEM_TADDR_LEN_SHIFT 0
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#define ACRY_RSA_PARAM 0x58
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#define ACRY_RSA_PARAM_EXP_MASK GENMASK(31, 16)
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#define ACRY_RSA_PARAM_EXP_SHIFT 16
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#define ACRY_RSA_PARAM_MOD_MASK GENMASK(15, 0)
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#define ACRY_RSA_PARAM_MOD_SHIFT 0
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#define ACRY_RSA_INT_EN 0x3f8
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#define ACRY_RSA_INT_EN_RSA_READY BIT(2)
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#define ACRY_RSA_INT_EN_RSA_CMPLT BIT(1)
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#define ACRY_RSA_INT_STS 0x3fc
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#define ACRY_RSA_INT_STS_RSA_READY BIT(2)
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#define ACRY_RSA_INT_STS_RSA_CMPLT BIT(1)
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/* misc. constant */
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#define ACRY_ECC_MODE 2
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#define ACRY_RSA_MODE 3
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#define ACRY_CTX_BUFSZ 0x600
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struct aspeed_acry {
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phys_addr_t base;
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phys_addr_t sram_base; /* internal sram */
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struct clk clk;
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};
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static int aspeed_acry_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len,
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struct key_prop *prop, uint8_t *out)
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{
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int i, j;
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u8 *ctx;
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u8 *ptr;
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u32 reg;
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struct aspeed_acry *acry = dev_get_priv(dev);
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ctx = memalign(16, ACRY_CTX_BUFSZ);
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if (!ctx)
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return -ENOMEM;
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memset(ctx, 0, ACRY_CTX_BUFSZ);
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ptr = (u8 *)prop->public_exponent;
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for (i = prop->exp_len - 1, j = 0; i >= 0; --i) {
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ctx[j] = ptr[i];
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j++;
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j = (j % 16) ? j : j + 32;
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}
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ptr = (u8 *)prop->modulus;
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for (i = (prop->num_bits >> 3) - 1, j = 0; i >= 0; --i) {
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ctx[j + 16] = ptr[i];
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j++;
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j = (j % 16) ? j : j + 32;
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}
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ptr = (u8 *)sig;
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for (i = sig_len - 1, j = 0; i >= 0; --i) {
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ctx[j + 32] = ptr[i];
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j++;
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j = (j % 16) ? j : j + 32;
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}
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writel((u32)ctx, acry->base + ACRY_DMA_DRAM_SADDR);
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reg = (((prop->exp_len << 3) << ACRY_RSA_PARAM_EXP_SHIFT) & ACRY_RSA_PARAM_EXP_MASK) |
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((prop->num_bits << ACRY_RSA_PARAM_MOD_SHIFT) & ACRY_RSA_PARAM_MOD_MASK);
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writel(reg, acry->base + ACRY_RSA_PARAM);
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reg = (ACRY_CTX_BUFSZ << ACRY_DMA_DMEM_TADDR_LEN_SHIFT) & ACRY_DMA_DMEM_TADDR_LEN_MASK;
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writel(reg, acry->base + ACRY_DMA_DMEM_TADDR);
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reg = (ACRY_RSA_MODE << ACRY_CTRL3_ECC_RSA_MODE_SHIFT) & ACRY_CTRL3_ECC_RSA_MODE_MASK;
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writel(reg, acry->base + ACRY_CTRL3);
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writel(ACRY_CTRL1_RSA_DMA | ACRY_CTRL1_RSA_START, acry->base + ACRY_CTRL1);
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/* polling RSA status */
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while (1) {
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reg = readl(acry->base + ACRY_RSA_INT_STS);
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if ((reg & ACRY_RSA_INT_STS_RSA_READY) && (reg & ACRY_RSA_INT_STS_RSA_CMPLT)) {
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writel(reg, ACRY_RSA_INT_STS);
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break;
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}
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udelay(20);
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}
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/* grant SRAM access permission to CPU */
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writel(0x0, acry->base + ACRY_CTRL1);
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writel(ACRY_CTRL3_SRAM_AHB_ACCESS, acry->base + ACRY_CTRL3);
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udelay(20);
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for (i = (prop->num_bits / 8) - 1, j = 0; i >= 0; --i) {
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out[i] = readb(acry->sram_base + (j + 32));
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j++;
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j = (j % 16) ? j : j + 32;
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}
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/* return SRAM access permission to ACRY */
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writel(0, acry->base + ACRY_CTRL3);
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free(ctx);
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return 0;
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}
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static int aspeed_acry_probe(struct udevice *dev)
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{
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struct aspeed_acry *acry = dev_get_priv(dev);
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int ret;
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ret = clk_get_by_index(dev, 0, &acry->clk);
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if (ret < 0) {
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debug("Can't get clock for %s: %d\n", dev->name, ret);
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return ret;
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}
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ret = clk_enable(&acry->clk);
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if (ret) {
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debug("Failed to enable acry clock (%d)\n", ret);
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return ret;
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}
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acry->base = devfdt_get_addr_index(dev, 0);
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if (acry->base == FDT_ADDR_T_NONE) {
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debug("Failed to get acry base\n");
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return acry->base;
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}
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acry->sram_base = devfdt_get_addr_index(dev, 1);
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if (acry->sram_base == FDT_ADDR_T_NONE) {
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debug("Failed to get acry SRAM base\n");
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return acry->sram_base;
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}
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return ret;
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}
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static int aspeed_acry_remove(struct udevice *dev)
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{
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struct aspeed_acry *acry = dev_get_priv(dev);
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clk_disable(&acry->clk);
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return 0;
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}
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static const struct mod_exp_ops aspeed_acry_ops = {
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.mod_exp = aspeed_acry_mod_exp,
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};
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static const struct udevice_id aspeed_acry_ids[] = {
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{ .compatible = "aspeed,ast2600-acry" },
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{ }
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};
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U_BOOT_DRIVER(aspeed_acry) = {
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.name = "aspeed_acry",
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.id = UCLASS_MOD_EXP,
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.of_match = aspeed_acry_ids,
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.probe = aspeed_acry_probe,
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.remove = aspeed_acry_remove,
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.priv_auto = sizeof(struct aspeed_acry),
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.ops = &aspeed_acry_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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@ -1,7 +1,8 @@
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config RSA
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bool "Use RSA Library"
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select RSA_FREESCALE_EXP if FSL_CAAM && !ARCH_MX7 && !ARCH_MX7ULP && !ARCH_MX6 && !ARCH_MX5
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select RSA_SOFTWARE_EXP if !RSA_FREESCALE_EXP
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select RSA_ASPEED_EXP if ASPEED_ACRY
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select RSA_SOFTWARE_EXP if !RSA_FREESCALE_EXP && !RSA_ASPEED_EXP
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help
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RSA support. This enables the RSA algorithm used for FIT image
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verification in U-Boot.
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@ -62,4 +63,11 @@ config RSA_FREESCALE_EXP
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Enables driver for RSA modular exponentiation using Freescale cryptographic
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accelerator - CAAM.
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config RSA_ASPEED_EXP
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bool "Enable RSA Modular Exponentiation with ASPEED crypto accelerator"
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depends on DM && ASPEED_ACRY
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help
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Enables driver for RSA modular exponentiation using ASPEED cryptographic
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accelerator - ACRY
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endif
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