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https://github.com/AsahiLinux/u-boot
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Convert CONFIG_LAST_STAGE_INIT to Kconfig
This converts the following to Kconfig: CONFIG_LAST_STAGE_INIT Signed-off-by: Tom Rini <trini@konsulko.com>
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parent
d3fb2e3991
commit
82cd1e3da0
7 changed files with 5 additions and 5 deletions
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@ -14,6 +14,7 @@ CONFIG_BOOTDELAY=3
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="earlycon=serial,0xf4329148 console=ttyS0,115200 root=/dev/ram0"
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CONFIG_BOARD_EARLY_INIT_R=y
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CONFIG_LAST_STAGE_INIT=y
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CONFIG_SYS_PROMPT="G3#"
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CONFIG_CMD_WDT=y
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CONFIG_CMD_CACHE=y
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@ -12,6 +12,7 @@ CONFIG_SYS_LOAD_ADDR=0x10000000
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CONFIG_SHOW_BOOT_PROGRESS=y
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CONFIG_BOOTDELAY=3
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CONFIG_BOARD_EARLY_INIT_R=y
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CONFIG_LAST_STAGE_INIT=y
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CONFIG_SYS_PROMPT="G3#"
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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@ -14,6 +14,7 @@ CONFIG_BOOTDELAY=3
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="earlycon=serial,0xf4329148 console=ttyS0,115200 root=/dev/ram0"
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CONFIG_BOARD_EARLY_INIT_R=y
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CONFIG_LAST_STAGE_INIT=y
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CONFIG_SYS_PROMPT="G3#"
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CONFIG_CMD_MTD=y
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CONFIG_CMD_WDT=y
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@ -24,6 +24,7 @@ CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=6 rootwait rw root=/dev/mmcblk0p2 coherent_pool=16M"
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_BOARD_EARLY_INIT_R=y
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CONFIG_LAST_STAGE_INIT=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_PROMPT="Marvell> "
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# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
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@ -24,6 +24,7 @@ CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=24 rootwait rw root=/dev/mmcblk0p2 coherent_pool=16M"
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_BOARD_EARLY_INIT_R=y
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CONFIG_LAST_STAGE_INIT=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_PROMPT="Marvell> "
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# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
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@ -18,8 +18,6 @@
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/** Stack starting address */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0)
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#define CONFIG_LAST_STAGE_INIT
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/* Autoboot options */
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#define CONFIG_RESET_TO_RETRY
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#define CONFIG_BOOT_RETRY_TIME -1
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@ -43,9 +43,6 @@
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/* BOOTP options */
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#define CONFIG_BOOTP_BOOTFILESIZE
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/* Miscellaneous configurable options */
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#define CONFIG_LAST_STAGE_INIT
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/* SDRAM Bank #1 */
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#define DDR_BASE 0x00000000
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#define PHYS_SDRAM_1 DDR_BASE
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