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Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

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This commit is contained in:
Wolfgang Denk 2010-10-26 20:57:41 +02:00
commit 7ad1a5f69d
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2
MAINTAINERS
View file

@ -144,6 +144,8 @@ Dirk Eibach <eibach@gdsys.de>
dlvision PPC405EP
gdppc440etx PPC440EP/GR
intip PPC460EX
io PPC405EP
iocon PPC405EP
neo PPC405EP
Dave Ellis <DGE@sixnetio.com>

93
board/gdsys/405ep/405ep.c Normal file
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/*
* (C) Copyright 2010
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
#include "../common/fpga.h"
#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
#define REFLECTION_TESTPATTERN 0xdede
#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
int board_early_init_f(void)
{
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks
* -> ca. 15 us
*/
mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
/*
* setup io-latches for reset
*/
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
/*
* set "startup-finished"-gpios
*/
gpio_write_bit(21, 0);
gpio_write_bit(22, 1);
/*
* wait for fpga-done
* fail ungraceful if fpga is not configuring properly
*/
while (!(in_le16((void *)LATCH2_BASE) & 0x0010))
;
/*
* setup io-latches for boot (stop reset)
*/
udelay(10);
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
/*
* wait for fpga out of reset
* fail ungraceful if fpga is not working properly
*/
while (1) {
fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN);
if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) ==
REFLECTION_TESTPATTERN_INV)
break;
}
return 0;
}

54
board/gdsys/405ep/Makefile Normal file
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@ -0,0 +1,54 @@
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-$(CONFIG_IO) += io.o
COBJS-$(CONFIG_IOCON) += iocon.o
COBJS := $(BOARD).o $(COBJS-y)
SOBJS =
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

181
board/gdsys/405ep/io.c Normal file
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@ -0,0 +1,181 @@
/*
* (C) Copyright 2010
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
#include <miiphy.h>
#include "../common/fpga.h"
#define PHYREG_CONTROL 0
#define PHYREG_PAGE_ADDRESS 22
#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
enum {
REG_VERSIONS = 0x0002,
REG_FPGA_FEATURES = 0x0004,
REG_FPGA_VERSION = 0x0006,
REG_QUAD_SERDES_RESET = 0x0012,
};
enum {
UNITTYPE_CCD_SWITCH = 1,
};
enum {
HWVER_100 = 0,
HWVER_110 = 1,
HWVER_121 = 2,
HWVER_122 = 3,
};
int configure_gbit_phy(unsigned char addr)
{
unsigned short value;
/* select page 2 */
if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
PHYREG_PAGE_ADDRESS, 0x0002))
goto err_out;
/* disable SGMII autonegotiation */
if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
goto err_out;
/* select page 0 */
if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
PHYREG_PAGE_ADDRESS, 0x0000))
goto err_out;
/* switch from powerdown to normal operation */
if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
goto err_out;
if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
goto err_out;
/* reset phy so settings take effect */
if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
PHYREG_CONTROL, 0x9140))
goto err_out;
return 0;
err_out:
printf("Error writing to the PHY addr=%02x\n", addr);
return -1;
}
/*
* Check Board Identity:
*/
int checkboard(void)
{
char *s = getenv("serial#");
u16 versions = fpga_get_reg(REG_VERSIONS);
u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
unsigned unit_type;
unsigned hardware_version;
unsigned feature_channels;
unsigned feature_expansion;
unit_type = (versions & 0xf000) >> 12;
hardware_version = versions & 0x000f;
feature_channels = fpga_features & 0x007f;
feature_expansion = fpga_features & (1<<15);
printf("Board: ");
printf("CATCenter Io");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
puts("\n ");
switch (unit_type) {
case UNITTYPE_CCD_SWITCH:
printf("CCD-Switch");
break;
default:
printf("UnitType %d(not supported)", unit_type);
break;
}
switch (hardware_version) {
case HWVER_100:
printf(" HW-Ver 1.00\n");
break;
case HWVER_110:
printf(" HW-Ver 1.10\n");
break;
case HWVER_121:
printf(" HW-Ver 1.21\n");
break;
case HWVER_122:
printf(" HW-Ver 1.22\n");
break;
default:
printf(" HW-Ver %d(not supported)\n",
hardware_version);
break;
}
printf(" FPGA V %d.%02d, features:",
fpga_version / 100, fpga_version % 100);
printf(" %d channel(s)", feature_channels);
printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
return 0;
}
/*
* setup Gbit PHYs
*/
int last_stage_init(void)
{
unsigned int k;
miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
bb_miiphy_read, bb_miiphy_write);
for (k = 0; k < 32; ++k)
configure_gbit_phy(k);
/* take fpga serdes blocks out of reset */
fpga_set_reg(REG_QUAD_SERDES_RESET, 0);
return 0;
}

236
board/gdsys/405ep/iocon.c Normal file
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@ -0,0 +1,236 @@
/*
* (C) Copyright 2010
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
#include "../common/fpga.h"
#include "../common/osd.h"
enum {
REG_VERSIONS = 0x0002,
REG_FPGA_VERSION = 0x0004,
REG_FPGA_FEATURES = 0x0006,
};
enum {
UNITTYPE_MAIN_SERVER = 0,
UNITTYPE_MAIN_USER = 1,
UNITTYPE_VIDEO_SERVER = 2,
UNITTYPE_VIDEO_USER = 3,
};
enum {
HWVER_100 = 0,
HWVER_104 = 1,
HWVER_110 = 2,
};
enum {
COMPRESSION_NONE = 0,
COMPRESSION_TYPE1_DELTA,
};
enum {
AUDIO_NONE = 0,
AUDIO_TX = 1,
AUDIO_RX = 2,
AUDIO_RXTX = 3,
};
enum {
SYSCLK_147456 = 0,
};
enum {
RAM_DDR2_32 = 0,
};
/*
* Check Board Identity:
*/
int checkboard(void)
{
char *s = getenv("serial#");
u16 versions = fpga_get_reg(REG_VERSIONS);
u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
unsigned unit_type;
unsigned hardware_version;
unsigned feature_compression;
unsigned feature_osd;
unsigned feature_audio;
unsigned feature_sysclock;
unsigned feature_ramconfig;
unsigned feature_carriers;
unsigned feature_video_channels;
unit_type = (versions & 0xf000) >> 12;
hardware_version = versions & 0x000f;
feature_compression = (fpga_features & 0xe000) >> 13;
feature_osd = fpga_features & (1<<11);
feature_audio = (fpga_features & 0x0600) >> 9;
feature_sysclock = (fpga_features & 0x0180) >> 7;
feature_ramconfig = (fpga_features & 0x0060) >> 5;
feature_carriers = (fpga_features & 0x000c) >> 2;
feature_video_channels = fpga_features & 0x0003;
printf("Board: ");
printf("IoCon");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
puts("\n ");
switch (unit_type) {
case UNITTYPE_MAIN_USER:
printf("Mainchannel");
break;
case UNITTYPE_VIDEO_USER:
printf("Videochannel");
break;
default:
printf("UnitType %d(not supported)", unit_type);
break;
}
switch (hardware_version) {
case HWVER_100:
printf(" HW-Ver 1.00\n");
break;
case HWVER_104:
printf(" HW-Ver 1.04\n");
break;
case HWVER_110:
printf(" HW-Ver 1.10\n");
break;
default:
printf(" HW-Ver %d(not supported)\n",
hardware_version);
break;
}
printf(" FPGA V %d.%02d, features:",
fpga_version / 100, fpga_version % 100);
switch (feature_compression) {
case COMPRESSION_NONE:
printf(" no compression");
break;
case COMPRESSION_TYPE1_DELTA:
printf(" type1-deltacompression");
break;
default:
printf(" compression %d(not supported)", feature_compression);
break;
}
printf(", %sosd", feature_osd ? "" : "no ");
switch (feature_audio) {
case AUDIO_NONE:
printf(", no audio");
break;
case AUDIO_TX:
printf(", audio tx");
break;
case AUDIO_RX:
printf(", audio rx");
break;
case AUDIO_RXTX:
printf(", audio rx+tx");
break;
default:
printf(", audio %d(not supported)", feature_audio);
break;
}
puts(",\n ");
switch (feature_sysclock) {
case SYSCLK_147456:
printf("clock 147.456 MHz");
break;
default:
printf("clock %d(not supported)", feature_sysclock);
break;
}
switch (feature_ramconfig) {
case RAM_DDR2_32:
printf(", RAM 32 bit DDR2");
break;
default:
printf(", RAM %d(not supported)", feature_ramconfig);
break;
}
printf(", %d carrier(s)", feature_carriers);
printf(", %d video channel(s)\n", feature_video_channels);
return 0;
}
int last_stage_init(void)
{
return osd_probe();
}
/*
* provide access to fpga gpios (for I2C bitbang)
*/
void fpga_gpio_set(int pin)
{
out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x18), pin);
}
void fpga_gpio_clear(int pin)
{
out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x16), pin);
}
int fpga_gpio_get(int pin)
{
return in_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x14)) & pin;
}

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board/gdsys/common/Makefile Normal file
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#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)board/$(VENDOR)/common)
endif
LIB = $(obj)lib$(VENDOR).a
COBJS-$(CONFIG_IO) += miiphybb.o
COBJS-$(CONFIG_IOCON) += osd.o
COBJS := $(COBJS-y)
SOBJS =
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

37
board/gdsys/common/fpga.h Normal file
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/*
* (C) Copyright 2010
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _FPGA_H_
#define _FPGA_H_
static inline u16 fpga_get_reg(unsigned reg)
{
return in_le16((void *)(CONFIG_SYS_FPGA_BASE + reg));
}
static inline void fpga_set_reg(unsigned reg, u16 val)
{
return out_le16((void *)(CONFIG_SYS_FPGA_BASE + reg), val);
}
#endif

102
board/gdsys/common/miiphybb.c Normal file
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/*
* (C) Copyright 2010
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <miiphy.h>
#include <asm/io.h>
static int io_bb_mii_init(struct bb_miiphy_bus *bus)
{
return 0;
}
static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
{
out_be32((void *)GPIO0_TCR,
in_be32((void *)GPIO0_TCR) | CONFIG_SYS_MDIO_PIN);
return 0;
}
static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
out_be32((void *)GPIO0_TCR,
in_be32((void *)GPIO0_TCR) & ~CONFIG_SYS_MDIO_PIN);
return 0;
}
static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
if (v)
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDIO_PIN);
else
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDIO_PIN);
return 0;
}
static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
*v = ((in_be32((void *)GPIO0_IR) & CONFIG_SYS_MDIO_PIN) != 0);
return 0;
}
static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
if (v)
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDC_PIN);
else
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDC_PIN);
return 0;
}
static int io_bb_delay(struct bb_miiphy_bus *bus)
{
udelay(1);
return 0;
}
struct bb_miiphy_bus bb_miiphy_buses[] = {
{
.name = CONFIG_SYS_GBIT_MII_BUSNAME,
.init = io_bb_mii_init,
.mdio_active = io_bb_mdio_active,
.mdio_tristate = io_bb_mdio_tristate,
.set_mdio = io_bb_set_mdio,
.get_mdio = io_bb_get_mdio,
.set_mdc = io_bb_set_mdc,
.delay = io_bb_delay,
}
};
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
sizeof(bb_miiphy_buses[0]);

247
board/gdsys/common/osd.c Normal file
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/*
* (C) Copyright 2010
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include "fpga.h"
#define CH7301_I2C_ADDR 0x75
#define PIXCLK_640_480_60 25180000
#define BASE_WIDTH 32
#define BASE_HEIGHT 16
#define BUFSIZE (BASE_WIDTH * BASE_HEIGHT)
enum {
REG_CONTROL = 0x0010,
REG_MPC3W_CONTROL = 0x001a,
REG_VIDEOCONTROL = 0x0042,
REG_OSDVERSION = 0x0100,
REG_OSDFEATURES = 0x0102,
REG_OSDCONTROL = 0x0104,
REG_XY_SIZE = 0x0106,
REG_VIDEOMEM = 0x0800,
};
enum {
CH7301_CM = 0x1c, /* Clock Mode Register */
CH7301_IC = 0x1d, /* Input Clock Register */
CH7301_GPIO = 0x1e, /* GPIO Control Register */
CH7301_IDF = 0x1f, /* Input Data Format Register */
CH7301_CD = 0x20, /* Connection Detect Register */
CH7301_DC = 0x21, /* DAC Control Register */
CH7301_HPD = 0x23, /* Hot Plug Detection Register */
CH7301_TCTL = 0x31, /* DVI Control Input Register */
CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */
CH7301_TPD = 0x34, /* DVI PLL Divide Register */
CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */
CH7301_TPF = 0x36, /* DVI PLL Filter Register */
CH7301_TCT = 0x37, /* DVI Clock Test Register */
CH7301_TSTP = 0x48, /* Test Pattern Register */
CH7301_PM = 0x49, /* Power Management register */
CH7301_VID = 0x4a, /* Version ID Register */
CH7301_DID = 0x4b, /* Device ID Register */
CH7301_DSP = 0x56, /* DVI Sync polarity Register */
};
static void mpc92469ac_calc_parameters(unsigned int fout,
unsigned int *post_div, unsigned int *feedback_div)
{
unsigned int n = *post_div;
unsigned int m = *feedback_div;
unsigned int a;
unsigned int b = 14745600 / 16;
if (fout < 50169600)
n = 8;
else if (fout < 100339199)
n = 4;
else if (fout < 200678399)
n = 2;
else
n = 1;
a = fout * n + (b / 2); /* add b/2 for proper rounding */
m = a / b;
*post_div = n;
*feedback_div = m;
}
static void mpc92469ac_set(unsigned int fout)
{
unsigned int n;
unsigned int m;
unsigned int bitval = 0;
mpc92469ac_calc_parameters(fout, &n, &m);
switch (n) {
case 1:
bitval = 0x00;
break;
case 2:
bitval = 0x01;
break;
case 4:
bitval = 0x02;
break;
case 8:
bitval = 0x03;
break;
}
fpga_set_reg(REG_MPC3W_CONTROL, (bitval << 9) | m);
}
static int osd_write_videomem(unsigned offset, u16 *data, size_t charcount)
{
unsigned int k;
for (k = 0; k < charcount; ++k) {
if (offset + k >= BUFSIZE)
return -1;
fpga_set_reg(REG_VIDEOMEM + 2 * (offset + k), data[k]);
}
return charcount;
}
static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned x;
unsigned y;
unsigned charcount;
unsigned len;
u8 color;
unsigned int k;
u16 buf[BUFSIZE];
char *text;
if (argc < 5) {
cmd_usage(cmdtp);
return 1;
}
x = simple_strtoul(argv[1], NULL, 16);
y = simple_strtoul(argv[2], NULL, 16);
color = simple_strtoul(argv[3], NULL, 16);
text = argv[4];
charcount = strlen(text);
len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
for (k = 0; k < len; ++k)
buf[k] = (text[k] << 8) | color;
return osd_write_videomem(y * BASE_WIDTH + x, buf, len);
}
int osd_probe(void)
{
u8 value;
u16 version = fpga_get_reg(REG_OSDVERSION);
u16 features = fpga_get_reg(REG_OSDFEATURES);
unsigned width;
unsigned height;
width = ((features & 0x3f00) >> 8) + 1;
height = (features & 0x001f) + 1;
printf("OSD: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
version/100, version%100, width, height);
value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
if (value != 0x17) {
printf(" Probing CH7301 failed, DID %02x\n", value);
return -1;
}
i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
mpc92469ac_set(PIXCLK_640_480_60);
fpga_set_reg(REG_VIDEOCONTROL, 0x0002);
fpga_set_reg(REG_OSDCONTROL, 0x0049);
fpga_set_reg(REG_XY_SIZE, ((32 - 1) << 8) | (16 - 1));
return 0;
}
int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned x;
unsigned y;
unsigned k;
u16 buffer[BASE_WIDTH];
char *rp;
u16 *wp = buffer;
unsigned count = (argc > 4) ? simple_strtoul(argv[4], NULL, 16) : 1;
if ((argc < 4) || (strlen(argv[3]) % 4)) {
cmd_usage(cmdtp);
return 1;
}
x = simple_strtoul(argv[1], NULL, 16);
y = simple_strtoul(argv[2], NULL, 16);
rp = argv[3];
while (*rp) {
char substr[5];
memcpy(substr, rp, 4);
substr[4] = 0;
*wp = simple_strtoul(substr, NULL, 16);
rp += 4;
wp++;
if (wp - buffer > BASE_WIDTH)
break;
}
for (k = 0; k < count; ++k) {
unsigned offset = y * BASE_WIDTH + x + k * (wp - buffer);
osd_write_videomem(offset, buffer, wp - buffer);
}
return 0;
}
U_BOOT_CMD(
osdw, 5, 0, osd_write,
"write 16-bit hex encoded buffer to osd memory",
"pos_x pos_y buffer count\n"
);
U_BOOT_CMD(
osdp, 5, 0, osd_print,
"write ASCII buffer to osd memory",
"pos_x pos_y color text\n"
);

29
board/gdsys/common/osd.h Normal file
View file

@ -0,0 +1,29 @@
/*
* (C) Copyright 2010
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _OSD_H_
#define _OSD_H_
int osd_probe(void);
#endif

2
boards.cfg
View file

@ -641,6 +641,8 @@ CPCI405AB powerpc ppc4xx cpci405 esd
CPCI405DT powerpc ppc4xx cpci405 esd
dlvision powerpc ppc4xx - gdsys
gdppc440etx powerpc ppc4xx - gdsys
io powerpc ppc4xx 405ep gdsys
iocon powerpc ppc4xx 405ep gdsys
CPCIISER4 powerpc ppc4xx cpciiser4 esd
DASA_SIM powerpc ppc4xx dasa_sim esd
PMC405DE powerpc ppc4xx pmc405de esd

251
include/configs/io.h Normal file
View file

@ -0,0 +1,251 @@
/*
* (C) Copyright 2010
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_405EP 1 /* this is a PPC405 CPU */
#define CONFIG_4xx 1 /* member of PPC4xx family */
#define CONFIG_IO 1 /* on a Io board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
/*
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME io
#define CONFIG_IDENT_STRING " io 0.04"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
#define CONFIG_LAST_STAGE_INIT /* call last_stage_init */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
/*
* Configure PLL
*/
#define PLLMR0_DEFAULT PLLMR0_266_133_66
#define PLLMR1_DEFAULT PLLMR1_266_133_66
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_AMCC_DEF_ENV \
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
"kernel_addr=fc000000\0" \
"fdt_addr=fc1e0000\0" \
"ramdisk_addr=fc200000\0" \
""
#define CONFIG_PHY_ADDR 4 /* PHY address */
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
/*
* Commands additional to the ones defined in amcc-common.h
*/
#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_EEPROM
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
*/
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
/* SDRAM timings used in datasheet */
#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
/*
* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
* The Linux BASE_BAUD define should match this configuration.
* baseBaud = cpuClock/(uartDivisor*16)
* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
* set Linux BASE_BAUD to 403200.
*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CONFIG_SYS_BASE_BAUD 691200
/*
* I2C stuff
*/
#define CONFIG_SYS_I2C_SPEED 100000
/* Temp sensor/hwmon/dtt */
#define CONFIG_DTT_LM63 1 /* National LM63 */
#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
#define CONFIG_DTT_PWM_LOOKUPTABLE \
{ { 40, 10 }, { 50, 20 }, { 60, 40 } }
#define CONFIG_DTT_TACH_LIMIT 0xa10
/*
* FLASH organization
*/
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CONFIG_SYS_FLASH_BASE 0xFC000000
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif
/* Gbit PHYs */
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 13) /* our MDIO is GPIO0 */
#define CONFIG_SYS_MDC_PIN (0x80000000 >> 7) /* our MDC is GPIO7 */
#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy"
/*
* PPC405 GPIO Configuration
*/
#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
{ \
/* GPIO Core 0 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
} \
}
/*
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory (OCM) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM 1
/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
* External Bus Controller (EBC) Setup
*/
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0xa382a880
/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
/* Memory Bank 1 (NVRAM) initializatio */
#define CONFIG_SYS_EBC_PB1AP 0x92015480
/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
#define CONFIG_SYS_EBC_PB1CR 0x7f318000
/* Memory Bank 2 (FPGA) initialization */
#define CONFIG_SYS_FPGA_BASE 0x7f100000
#define CONFIG_SYS_EBC_PB2AP 0x02025080
/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
#define CONFIG_SYS_EBC_PB2CR 0x7f11a000
#define CONFIG_SYS_FPGA_RFL_LOW 0x0000
#define CONFIG_SYS_FPGA_RFL_HIGH 0x3ffe
/* Memory Bank 3 (Latches) initialization */
#define CONFIG_SYS_LATCH_BASE 0x7f200000
#define CONFIG_SYS_EBC_PB3AP 0xa2015480
/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
#define CONFIG_SYS_LATCH0_RESET 0xffff
#define CONFIG_SYS_LATCH0_BOOT 0xffff
#define CONFIG_SYS_LATCH1_RESET 0xffbf
#define CONFIG_SYS_LATCH1_BOOT 0xffff
#endif /* __CONFIG_H */

252
include/configs/iocon.h Normal file
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@ -0,0 +1,252 @@
/*
* (C) Copyright 2010
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_405EP 1 /* this is a PPC405 CPU */
#define CONFIG_4xx 1 /* member of PPC4xx family */
#define CONFIG_IOCON 1 /* on a IoCon board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
/*
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME iocon
#define CONFIG_IDENT_STRING " iocon 0.03"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
/*
* Configure PLL
*/
#define PLLMR0_DEFAULT PLLMR0_266_133_66
#define PLLMR1_DEFAULT PLLMR1_266_133_66
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_AMCC_DEF_ENV \
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
"kernel_addr=fc000000\0" \
"fdt_addr=fc1e0000\0" \
"ramdisk_addr=fc200000\0" \
""
#define CONFIG_PHY_ADDR 4 /* PHY address */
#define CONFIG_HAS_ETH0
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
/*
* Commands additional to the ones defined in amcc-common.h
*/
#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_EEPROM
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
*/
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
/* SDRAM timings used in datasheet */
#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
/*
* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
* The Linux BASE_BAUD define should match this configuration.
* baseBaud = cpuClock/(uartDivisor*16)
* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
* set Linux BASE_BAUD to 403200.
*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CONFIG_SYS_BASE_BAUD 691200
/*
* I2C stuff
*/
#define CONFIG_SYS_I2C_SPEED 400000
/* enable I2C and select the hardware/software driver */
#undef CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
/*
* Software (bit-bang) I2C driver configuration
*/
#ifndef __ASSEMBLY__
void fpga_gpio_set(int pin);
void fpga_gpio_clear(int pin);
int fpga_gpio_get(int pin);
#endif
#define I2C_ACTIVE { }
#define I2C_TRISTATE { }
#define I2C_READ fpga_gpio_get(0x0040) ? 1 : 0
#define I2C_SDA(bit) if (bit) fpga_gpio_set(0x0040); \
else fpga_gpio_clear(0x0040)
#define I2C_SCL(bit) if (bit) fpga_gpio_set(0x0020); \
else fpga_gpio_clear(0x0020)
#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
/*
* FLASH organization
*/
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CONFIG_SYS_FLASH_BASE 0xFC000000
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif
/*
* PPC405 GPIO Configuration
*/
#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
{ \
/* GPIO Core 0 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
} \
}
/*
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory (OCM) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM 1
/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
* External Bus Controller (EBC) Setup
*/
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0xa382a880
#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
/* Memory Bank 1 (NVRAM) initializatio */
#define CONFIG_SYS_EBC_PB1AP 0x92015480
#define CONFIG_SYS_EBC_PB1CR 0xFB858000
/* Memory Bank 2 (FPGA) initialization */
#define CONFIG_SYS_FPGA_BASE 0x7f100000
#define CONFIG_SYS_EBC_PB2AP 0x02825080
#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x1a000)
#define CONFIG_SYS_FPGA_RFL_LOW 0x0000
#define CONFIG_SYS_FPGA_RFL_HIGH 0x00fe
/* Memory Bank 3 (Latches) initialization */
#define CONFIG_SYS_LATCH_BASE 0x7f200000
#define CONFIG_SYS_EBC_PB3AP 0x02025080
#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
#define CONFIG_SYS_LATCH0_RESET 0xffef
#define CONFIG_SYS_LATCH0_BOOT 0xffff
#define CONFIG_SYS_LATCH1_RESET 0xffff
#define CONFIG_SYS_LATCH1_BOOT 0xffff
#endif /* __CONFIG_H */