Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-10 15:14:43 +00:00
Code Issues Projects Releases Packages Wiki Activity

Xilinx changes for v2020.07-rc2

Browse source 
mmc:
 - Fix dt property handling via generic function
 
 clk:
 - Fix versal watchdog clock setting
 
 nand:
 - Fix zynq nand command comparison
 
 xilinx:
 - Enable ubifs
 - Sync board_late_init configurations with initrd_high setup
 - Make custom distro boot more verbose
 
 zynq:
 - Kconfig alignments
 - Fix nand cse configuration
 
 zynqmp:
 - Fix zcu104 low level qspi configuration
 - Small DT updates
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCXqp9yAAKCRDKSWXLKUoM
 IXiuAKCLjBKGQ+o+BkJMvjbydF1JgFdXpwCffFPRe6dTkPsLZhpzW/YQMrjidtg=
 =CQTb
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2020.07-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2020.07-rc2

mmc:
- Fix dt property handling via generic function

clk:
- Fix versal watchdog clock setting

nand:
- Fix zynq nand command comparison

xilinx:
- Enable ubifs
- Sync board_late_init configurations with initrd_high setup
- Make custom distro boot more verbose

zynq:
- Kconfig alignments
- Fix nand cse configuration

zynqmp:
- Fix zcu104 low level qspi configuration
- Small DT updates

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2020-04-30 11:31:33 -04:00
commit 6d7dacf726
27 changed files with 165 additions and 98 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
arch/arm/Kconfig
View file

@ -475,7 +475,7 @@ config TPL_USE_ARCH_MEMSET
config SET_STACK_SIZE
bool "Enable an option to set max stack size that can be used"
default y if ARCH_VERSAL || ARCH_ZYNQMP
default y if ARCH_VERSAL || ARCH_ZYNQMP || ARCH_ZYNQ
help
This will enable an option to set max stack size that can be
used by U-Boot.
@ -484,6 +484,7 @@ config STACK_SIZE
hex "Define max stack size that can be used by U-Boot"
depends on SET_STACK_SIZE
default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
default 0x1000000 if ARCH_ZYNQ
help
Define Max stack size that can be used by U-Boot so that the
initrd_high will be calculated as base stack pointer minus this

15
arch/arm/dts/zynq-cse-nand.dts
View file

@ -38,6 +38,21 @@
#size-cells = <1>;
ranges;
smcc: memory-controller@e000e000 {
#address-cells = <1>;
#size-cells = <1>;
clock-names = "memclk", "apb_pclk";
clocks = <&clkc 11>, <&clkc 44>;
compatible = "arm,pl353-smc-r2p1", "arm,primecell";
ranges;
reg = <0xe000e000 0x1000>;
nand0: flash@e1000000 {
compatible = "arm,pl353-nand-r2p1";
reg = <0xe1000000 0x1000000>;
};
};
slcr: slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <1>;

20
arch/arm/dts/zynqmp-e-a2197-00-revA.dts
View file

@ -162,8 +162,8 @@
"", "", "", "", "", /* 65 - 69 */
"", "", "", "", "", /* 70 - 74 */
"", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
"", "", /* 78 - 79 */
"", "", "", "", "", /* 80 - 84 */
"SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
"SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */
"", "", "", "", "", /* 85 - 89 */
"", "", "", "", "", /* 90 - 94 */
"", "", "", "", "", /* 95 - 99 */
@ -198,9 +198,6 @@
#size-cells = <0>;
reg = <0>;
/* u152 IR35215 0x16/0x46 vcc_soc */
/* u160 IRPS5401 0x17/0x47 */
/* u167 IRPS5401 0x1c/0x4c */
/* u175 IRPS5401 0x1d/0x4d */
/* u179 ir38164 0x19/0x49 vcco_500 */
/* u181 ir38164 0x1a/0x4a vcco_501 */
/* u183 ir38164 0x1b/0x4b vcco_502 */
@ -209,6 +206,19 @@
/* u189 ir38164 0x20/0x50 mgtyavtt */
/* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */
/* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */
irps5401_47: irps5401@47 { /* IRPS5401 - u160 */
compatible = "infineon,irps5401";
reg = <0x47>; /* pmbus / i2c 0x17 */
};
irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */
compatible = "infineon,irps5401";
reg = <0x4c>; /* pmbus / i2c 0x1c */
};
irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */
compatible = "infineon,irps5401";
reg = <0x4d>; /* pmbus / i2c 0x1d */
};
};
i2c@1 { /* PMBUS1_INA226 */
#address-cells = <1>;

10
arch/arm/dts/zynqmp-zcu104-revA.dts
View file

@ -147,15 +147,13 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
#clock-cells = <0>;
irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
compatible = "infineon,irps5401";
reg = <0x43>;
reg = <0x43>; /* pmbus / i2c 0x13 */
};
irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
#clock-cells = <0>;
irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
compatible = "infineon,irps5401";
reg = <0x4d>;
reg = <0x44>; /* pmbus / i2c 0x14 */
};
};

10
arch/arm/dts/zynqmp-zcu104-revC.dts
View file

@ -172,15 +172,13 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
#clock-cells = <0>;
irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
compatible = "infineon,irps5401";
reg = <0x43>;
reg = <0x43>; /* pmbus / i2c 0x13 */
};
irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
#clock-cells = <0>;
irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
compatible = "infineon,irps5401";
reg = <0x4d>;
reg = <0x44>; /* pmbus / i2c 0x14 */
};
};

9
arch/arm/dts/zynqmp-zcu111-revA.dts
View file

@ -327,18 +327,15 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
#clock-cells = <0>;
irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */
compatible = "infineon,irps5401";
reg = <0x43>;
};
irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
#clock-cells = <0>;
irps5401_44: irps5401@44 { /* IRPS5401 - u55 */
compatible = "infineon,irps5401";
reg = <0x44>;
};
irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
#clock-cells = <0>;
irps5401_45: irps5401@45 { /* IRPS5401 - u57 */
compatible = "infineon,irps5401";
reg = <0x45>;
};

6
arch/arm/dts/zynqmp-zcu208-revA.dts
View file

@ -351,13 +351,11 @@
/* u112 - ir38164 0x13/0x43 */
/* u123 - ir38164 0x1c/0x4c */
irps5401_44: irps54012@44 { /* IRPS5401 - u53 */
#clock-cells = <0>;
irps5401_44: irps5401@44 { /* IRPS5401 - u53 */
compatible = "infineon,irps5401";
reg = <0x44>; /* i2c addr 0x14 */
};
irps5401_45: irps54012@45 { /* IRPS5401 - u55 */
#clock-cells = <0>;
irps5401_45: irps5401@45 { /* IRPS5401 - u55 */
compatible = "infineon,irps5401";
reg = <0x45>; /* i2c addr 0x15 */
};

6
arch/arm/dts/zynqmp-zcu216-revA.dts
View file

@ -355,13 +355,11 @@
/* u112 - ir38164 0x13/0x43 */
/* u123 - ir38164 0x1c/0x4c */
irps5401_44: irps54012@44 { /* IRPS5401 - u53 */
#clock-cells = <0>;
irps5401_44: irps5401@44 { /* IRPS5401 - u53 */
compatible = "infineon,irps5401";
reg = <0x44>; /* i2c addr 0x14 */
};
irps5401_45: irps54012@45 { /* IRPS5401 - u55 */
#clock-cells = <0>;
irps5401_45: irps5401@45 { /* IRPS5401 - u55 */
compatible = "infineon,irps5401";
reg = <0x45>; /* i2c addr 0x15 */
};

1
board/bitmain/antminer_s9/Makefile
View file

@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
obj-y := board.o
obj-y += ../../xilinx/common/board.o
# Remove quotes
hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))

1
board/topic/zynq/Makefile
View file

@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := board.o
obj-y += ../../xilinx/common/board.o
# Remove quotes
hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))

15
board/xilinx/common/board.c
View file

@ -8,6 +8,8 @@
#include <asm/sections.h>
#include <dm/uclass.h>
#include <i2c.h>
#include <linux/sizes.h>
#include "board.h"
int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
{
@ -71,3 +73,16 @@ void *board_fdt_blob_setup(void)
return NULL;
}
#endif
int board_late_init_xilinx(void)
{
ulong initrd_hi;
env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
initrd_hi = round_down(initrd_hi, SZ_16M);
env_set_addr("initrd_high", (void *)initrd_hi);
return 0;
}

12
board/xilinx/common/board.h Normal file
View file

@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) Copyright 2020 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
*/
#ifndef _BOARD_XILINX_COMMON_BOARD_H
#define _BOARD_XILINX_COMMON_BOARD_H
int board_late_init_xilinx(void);
#endif /* BOARD_XILINX_COMMON_BOARD_H */

34
board/xilinx/versal/board.c
View file

@ -16,7 +16,7 @@
#include <dm/device.h>
#include <dm/uclass.h>
#include <versalpl.h>
#include <linux/sizes.h>
#include "../common/board.h"
DECLARE_GLOBAL_DATA_PTR;
@ -82,9 +82,23 @@ int board_early_init_r(void)
return 0;
}
static u8 versal_get_bootmode(void)
{
u8 bootmode;
u32 reg = 0;
reg = readl(&crp_base->boot_mode_usr);
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
bootmode = reg & BOOT_MODES_MASK;
return bootmode;
}
int board_late_init(void)
{
u32 reg = 0;
u8 bootmode;
struct udevice *dev;
int bootseq = -1;
@ -93,19 +107,13 @@ int board_late_init(void)
const char *mode;
char *new_targets;
char *env_targets;
ulong initrd_hi;
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
debug("Saved variables - Skipping\n");
return 0;
}
reg = readl(&crp_base->boot_mode_usr);
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
bootmode = reg & BOOT_MODES_MASK;
bootmode = versal_get_bootmode();
puts("Bootmode: ");
switch (bootmode) {
@ -200,13 +208,7 @@ int board_late_init(void)
env_set("boot_targets", new_targets);
initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
initrd_hi = round_down(initrd_hi, SZ_16M);
env_set_addr("initrd_high", (void *)initrd_hi);
env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
return 0;
return board_late_init_xilinx();
}
int dram_init_banksize(void)

5
board/xilinx/zynq/board.c
View file

@ -17,6 +17,7 @@
#include <zynqpl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include "../common/board.h"
DECLARE_GLOBAL_DATA_PTR;
@ -76,9 +77,7 @@ int board_late_init(void)
env_set("boot_targets", new_targets);
env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
return 0;
return board_late_init_xilinx();
}
#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)

3
board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
View file

@ -363,6 +363,7 @@ static unsigned long psu_mio_init_data(void)
psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
@ -408,7 +409,7 @@ static unsigned long psu_mio_init_data(void)
psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
psu_mask_write(0xFF180204, 0x7B3F003FU, 0x52240000U);
psu_mask_write(0xFF180204, 0x7B3F007FU, 0x52240000U);
psu_mask_write(0xFF180208, 0xFFFFE000U, 0x00B02000U);
psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);

39
board/xilinx/zynqmp/zynqmp.c
View file

@ -26,7 +26,7 @@
#include <zynqmppl.h>
#include <zynqmp_firmware.h>
#include <g_dnl.h>
#include <linux/sizes.h>
#include "../common/board.h"
#include "pm_cfg_obj.h"
@ -552,9 +552,26 @@ static int set_fdtfile(void)
return 0;
}
static u8 zynqmp_get_bootmode(void)
{
u8 bootmode;
u32 reg = 0;
int ret;
ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
if (ret)
return -EINVAL;
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
bootmode = reg & BOOT_MODES_MASK;
return bootmode;
}
int board_late_init(void)
{
u32 reg = 0;
u8 bootmode;
struct udevice *dev;
int bootseq = -1;
@ -564,7 +581,6 @@ int board_late_init(void)
char *new_targets;
char *env_targets;
int ret;
ulong initrd_hi;
#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
usb_ether_init();
@ -579,14 +595,7 @@ int board_late_init(void)
if (ret)
return ret;
ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
if (ret)
return -EINVAL;
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
bootmode = reg & BOOT_MODES_MASK;
bootmode = zynqmp_get_bootmode();
puts("Bootmode: ");
switch (bootmode) {
@ -691,15 +700,9 @@ int board_late_init(void)
env_set("boot_targets", new_targets);
initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
initrd_hi = round_down(initrd_hi, SZ_16M);
env_set_addr("initrd_high", (void *)initrd_hi);
env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
reset_reason();
return 0;
return board_late_init_xilinx();
}
#endif

5
configs/xilinx_zynq_virt_defconfig
View file

@ -32,12 +32,17 @@ CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_MTDPARTS_SPREAD=y
CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
CONFIG_CMD_UBI=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 zynq-zc770-xm011-x16 zynq-zc770-xm012 zynq-zc770-xm013 zynq-cc108 zynq-microzed zynq-minized zynq-picozed zynq-zed zynq-zturn zynq-zybo zynq-zybo-z7 zynq-dlc20-rev1.0"
CONFIG_ENV_IS_IN_SPI_FLASH=y

5
configs/xilinx_zynqmp_virt_defconfig
View file

@ -35,6 +35,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_POWEROFF=y
CONFIG_CMD_SDRAM=y
@ -45,6 +46,10 @@ CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_MTDPARTS_SPREAD=y
CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
CONFIG_CMD_UBI=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC"
CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA"

2
configs/zynq_cse_nand_defconfig
View file

@ -5,7 +5,7 @@ CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x100000
CONFIG_ENV_SIZE=0x190
CONFIG_SYS_MALLOC_LEN=0x1000
CONFIG_SYS_MALLOC_LEN=0x8000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y

5
drivers/clk/clk_versal.c
View file

@ -503,6 +503,9 @@ static u64 versal_clock_calc(u32 clk_id)
NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
return versal_clock_ref(clk_id);
if (!parent_id)
return 0;
clk_rate = versal_clock_calc(parent_id);
if (versal_clock_div(clk_id)) {
@ -526,7 +529,7 @@ static int versal_clock_get_rate(u32 clk_id, u64 *clk_rate)
NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_OUT &&
((clk_id >> NODE_CLASS_SHIFT) &
NODE_CLASS_MASK) == NODE_CLASS_CLOCK) {
if (!versal_clock_gate(clk_id))
if (!versal_clock_gate(clk_id) && !versal_clock_mux(clk_id))
return -EINVAL;
*clk_rate = versal_clock_calc(clk_id);
return 0;

3
drivers/mmc/sdhci.c
View file

@ -839,8 +839,7 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
cfg->host_caps &= ~MMC_MODE_HS_52MHz;
}
if (!(cfg->voltages & MMC_VDD_165_195) ||
(host->quirks & SDHCI_QUIRK_NO_1_8_V))
if (!(cfg->voltages & MMC_VDD_165_195))
caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
SDHCI_SUPPORT_DDR50);

15
drivers/mmc/zynq_sdhci.c
View file

@ -22,14 +22,12 @@ DECLARE_GLOBAL_DATA_PTR;
struct arasan_sdhci_plat {
struct mmc_config cfg;
struct mmc mmc;
unsigned int f_max;
};
struct arasan_sdhci_priv {
struct sdhci_host *host;
u8 deviceid;
u8 bank;
u8 no_1p8;
};
#if defined(CONFIG_ARCH_ZYNQMP)
@ -238,8 +236,11 @@ static int arasan_sdhci_probe(struct udevice *dev)
host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
#endif
if (priv->no_1p8)
host->quirks |= SDHCI_QUIRK_NO_1_8_V;
plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
ret = mmc_of_parse(dev, &plat->cfg);
if (ret)
return ret;
host->max_clk = clock;
@ -247,7 +248,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
host->mmc->dev = dev;
host->mmc->priv = host;
ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
CONFIG_ZYNQ_SDHCI_MIN_FREQ);
if (ret)
return ret;
@ -258,7 +259,6 @@ static int arasan_sdhci_probe(struct udevice *dev)
static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
{
struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
struct arasan_sdhci_priv *priv = dev_get_priv(dev);
priv->host = calloc(1, sizeof(struct sdhci_host));
@ -277,10 +277,7 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1);
priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
plat->f_max = dev_read_u32_default(dev, "max-frequency",
CONFIG_ZYNQ_SDHCI_MAX_FREQ);
return 0;
}

2
drivers/mtd/nand/raw/zynq_nand.c
View file

@ -845,7 +845,7 @@ static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
end_cmd_valid = 1;
if (curr_cmd->end_cmd == NAND_CMD_NONE)
if (curr_cmd->end_cmd == (u8)NAND_CMD_NONE)
end_cmd = 0x0;
else
end_cmd = curr_cmd->end_cmd;

12
include/configs/xilinx_versal.h
View file

@ -109,7 +109,8 @@
#define BOOTENV_DEV_XSPI(devtypeu, devtypel, instance) \
"bootcmd_xspi0=sf probe 0 0 0 && " \
"sf read $scriptaddr $script_offset_f $script_size_f && " \
"source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
"echo XSPI: Trying to boot script at ${scriptaddr} && " \
"source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0"
#define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \
"xspi "
@ -117,7 +118,8 @@
#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na)
#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \
"bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0"
"bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \
"source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0"
#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
"jtag "
@ -126,8 +128,10 @@
#define BOOTENV_DEV_DFU_USB(devtypeu, devtypel, instance) \
"bootcmd_dfu_usb=setenv dfu_alt_info boot.scr ram $scriptaddr " \
"$script_size_f; dfu 0 ram 0 && source $scriptaddr; " \
"echo SCRIPT FAILED: continuing...;\0"
"$script_size_f; dfu 0 ram 0 && " \
"echo DFU: Trying to boot script at ${scriptaddr} && " \
"source ${scriptaddr}; " \
"echo DFU: SCRIPT FAILED: continuing...;\0"
#define BOOTENV_DEV_NAME_DFU_USB(devtypeu, devtypel, instance) \
"dfu_usb "

9
include/configs/xilinx_zynqmp.h
View file

@ -160,7 +160,8 @@
#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
"bootcmd_" #devtypel #instance "=sf probe " #instance " 0 0 && " \
"sf read $scriptaddr $script_offset_f $script_size_f && " \
"source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
"echo QSPI: Trying to boot script at ${scriptaddr} && " \
"source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0"
#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
#devtypel #instance " "
@ -168,7 +169,8 @@
#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
"bootcmd_" #devtypel #instance "= nand info && " \
"nand read $scriptaddr $script_offset_f $script_size_f && " \
"source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
"echo NAND: Trying to boot script at ${scriptaddr} && " \
"source ${scriptaddr}; echo NAND: SCRIPT FAILED: continuing...;\0"
#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
#devtypel #instance " "
@ -176,7 +178,8 @@
#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na)
#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \
"bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0"
"bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \
"source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0"
#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
"jtag "

13
include/configs/zynq-common.h
View file

@ -152,7 +152,8 @@
#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
"bootcmd_qspi=sf probe 0 0 0 && " \
"sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \
"source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
"echo QSPI: Trying to boot script at ${scriptaddr} && " \
"source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0"
#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
"qspi "
@ -160,7 +161,8 @@
#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
"bootcmd_nand=nand info && " \
"nand read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \
"source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
"echo NAND: Trying to boot script at ${scriptaddr} && " \
"source ${scriptaddr}; echo NAND: SCRIPT FAILED: continuing...;\0"
#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
"nand "
@ -168,7 +170,8 @@
#define BOOTENV_DEV_NOR(devtypeu, devtypel, instance) \
"script_offset_nor=0xE2FC0000\0" \
"bootcmd_nor=cp.b ${script_offset_nor} ${scriptaddr} ${script_size_f} && " \
"source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
"echo NOR: Trying to boot script at ${scriptaddr} && " \
"source ${scriptaddr}; echo NOR: SCRIPT FAILED: continuing...;\0"
#define BOOTENV_DEV_NAME_NOR(devtypeu, devtypel, instance) \
"nor "
@ -176,7 +179,8 @@
#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na)
#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \
"bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0"
"bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \
"source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0"
#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
"jtag "
@ -198,7 +202,6 @@
#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x20000000\0" \
"initrd_high=0x20000000\0" \
"scriptaddr=0x20000\0" \
"script_size_f=0x40000\0" \
"fdt_addr_r=0x1f00000\0" \

1
include/sdhci.h
View file

@ -243,7 +243,6 @@
#define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5)
#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
#define SDHCI_QUIRK_NO_1_8_V (1 << 9)
/* to make gcc happy */
struct sdhci_host;