From 942b5fc03218d1c94468fc658e7dec65dabcc830 Mon Sep 17 00:00:00 2001 From: Benedikt Grassl Date: Tue, 14 Apr 2020 07:32:12 +0200 Subject: [PATCH 01/14] mmc: zynq: parse dt when probing Currently, the entry "bus-width = <8>" in the ZynqMP's sdhci nodes is not evaluated. This results in the bus width staying at its default value (4 bit in HS200 mode). Fix this by calling mmc_of_parse. This function also checks for the "no-1-8-v" and "max-frequency" entries. Remove the handling of those nodes from this driver. Signed-off-by: Benedikt Grassl Reviewed-by: Jaehoon Chung Signed-off-by: Michal Simek --- drivers/mmc/sdhci.c | 3 +-- drivers/mmc/zynq_sdhci.c | 15 ++++++--------- include/sdhci.h | 1 - 3 files changed, 7 insertions(+), 12 deletions(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 520c9f9feb..372dc0a820 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -839,8 +839,7 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, cfg->host_caps &= ~MMC_MODE_HS_52MHz; } - if (!(cfg->voltages & MMC_VDD_165_195) || - (host->quirks & SDHCI_QUIRK_NO_1_8_V)) + if (!(cfg->voltages & MMC_VDD_165_195)) caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index da3ff53da1..18925d01fa 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -22,14 +22,12 @@ DECLARE_GLOBAL_DATA_PTR; struct arasan_sdhci_plat { struct mmc_config cfg; struct mmc mmc; - unsigned int f_max; }; struct arasan_sdhci_priv { struct sdhci_host *host; u8 deviceid; u8 bank; - u8 no_1p8; }; #if defined(CONFIG_ARCH_ZYNQMP) @@ -238,8 +236,11 @@ static int arasan_sdhci_probe(struct udevice *dev) host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE; #endif - if (priv->no_1p8) - host->quirks |= SDHCI_QUIRK_NO_1_8_V; + plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ; + + ret = mmc_of_parse(dev, &plat->cfg); + if (ret) + return ret; host->max_clk = clock; @@ -247,7 +248,7 @@ static int arasan_sdhci_probe(struct udevice *dev) host->mmc->dev = dev; host->mmc->priv = host; - ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max, + ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max, CONFIG_ZYNQ_SDHCI_MIN_FREQ); if (ret) return ret; @@ -258,7 +259,6 @@ static int arasan_sdhci_probe(struct udevice *dev) static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) { - struct arasan_sdhci_plat *plat = dev_get_platdata(dev); struct arasan_sdhci_priv *priv = dev_get_priv(dev); priv->host = calloc(1, sizeof(struct sdhci_host)); @@ -277,10 +277,7 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1); priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1); - priv->no_1p8 = dev_read_bool(dev, "no-1-8-v"); - plat->f_max = dev_read_u32_default(dev, "max-frequency", - CONFIG_ZYNQ_SDHCI_MAX_FREQ); return 0; } diff --git a/include/sdhci.h b/include/sdhci.h index aa4378fd57..0ef8c2ed62 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -243,7 +243,6 @@ #define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5) #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6) #define SDHCI_QUIRK_USE_WIDE8 (1 << 8) -#define SDHCI_QUIRK_NO_1_8_V (1 << 9) /* to make gcc happy */ struct sdhci_host; From 26ee8fc369f1f5a697d37d6a732498b252a6b561 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 8 Apr 2020 10:37:51 +0200 Subject: [PATCH 02/14] xilinx: Enable MTD and UBIFS for zynq and zynqmp Both of them have nand controller that's why it is good to enable it because these configurations are also covered by testing. Signed-off-by: Michal Simek --- configs/xilinx_zynq_virt_defconfig | 5 +++++ configs/xilinx_zynqmp_virt_defconfig | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 54cbd3e12b..6af4565451 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -32,12 +32,17 @@ CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_MTDPARTS_SPREAD=y +CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y +CONFIG_CMD_UBI=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 zynq-zc770-xm011-x16 zynq-zc770-xm012 zynq-zc770-xm013 zynq-cc108 zynq-microzed zynq-minized zynq-picozed zynq-zed zynq-zturn zynq-zybo zynq-zybo-z7 zynq-dlc20-rev1.0" CONFIG_ENV_IS_IN_SPI_FLASH=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 7b09edd78e..73e8d84b88 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_POWEROFF=y CONFIG_CMD_SDRAM=y @@ -45,6 +46,10 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_MTDPARTS_SPREAD=y +CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y +CONFIG_CMD_UBI=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC" CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA" From b72f4505277369bb9d8013370d5f316aff49f596 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 16 Apr 2020 14:17:23 +0200 Subject: [PATCH 03/14] ARM: zynq: Setup stack size via Kconfig Stack size has been introduced by commit a69814c815b9 ("arm64: zynqmp: Set initrd_high to as high as possible") and commit 085201c246ee ("arm64: versal: Set initrd_high to as high as possible") to support setting up initrd_high as high as possible. The same change should happen for Zynq because the code is moved to xilinx common location. Signed-off-by: Michal Simek --- arch/arm/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1bcf345028..8e67e1c587 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -475,7 +475,7 @@ config TPL_USE_ARCH_MEMSET config SET_STACK_SIZE bool "Enable an option to set max stack size that can be used" - default y if ARCH_VERSAL || ARCH_ZYNQMP + default y if ARCH_VERSAL || ARCH_ZYNQMP || ARCH_ZYNQ help This will enable an option to set max stack size that can be used by U-Boot. @@ -484,6 +484,7 @@ config STACK_SIZE hex "Define max stack size that can be used by U-Boot" depends on SET_STACK_SIZE default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP + default 0x1000000 if ARCH_ZYNQ help Define Max stack size that can be used by U-Boot so that the initrd_high will be calculated as base stack pointer minus this From 80fdef12b22ab70f9d83343016abcd3b50a87d7c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 31 Mar 2020 12:39:37 +0200 Subject: [PATCH 04/14] xilinx: Introduce board_late_init_xilinx() This function should keep common shared late configurations for Xilinx SoCs. Signed-off-by: Michal Simek --- board/bitmain/antminer_s9/Makefile | 1 + board/topic/zynq/Makefile | 1 + board/xilinx/common/board.c | 8 ++++++++ board/xilinx/common/board.h | 12 ++++++++++++ board/xilinx/versal/board.c | 5 ++--- board/xilinx/zynq/board.c | 5 ++--- board/xilinx/zynqmp/zynqmp.c | 5 ++--- 7 files changed, 28 insertions(+), 9 deletions(-) create mode 100644 board/xilinx/common/board.h diff --git a/board/bitmain/antminer_s9/Makefile b/board/bitmain/antminer_s9/Makefile index 93a1e77f72..1af01d6d80 100644 --- a/board/bitmain/antminer_s9/Makefile +++ b/board/bitmain/antminer_s9/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-y := board.o +obj-y += ../../xilinx/common/board.o # Remove quotes hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)) diff --git a/board/topic/zynq/Makefile b/board/topic/zynq/Makefile index becadd2ca7..cc100b0f42 100644 --- a/board/topic/zynq/Makefile +++ b/board/topic/zynq/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y := board.o +obj-y += ../../xilinx/common/board.o # Remove quotes hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)) diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index e83c692f21..7c191e53fb 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -8,6 +8,7 @@ #include #include #include +#include "board.h" int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) { @@ -71,3 +72,10 @@ void *board_fdt_blob_setup(void) return NULL; } #endif + +int board_late_init_xilinx(void) +{ + env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET); + + return 0; +} diff --git a/board/xilinx/common/board.h b/board/xilinx/common/board.h new file mode 100644 index 0000000000..180dfbca10 --- /dev/null +++ b/board/xilinx/common/board.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2020 Xilinx, Inc. + * Michal Simek + */ + +#ifndef _BOARD_XILINX_COMMON_BOARD_H +#define _BOARD_XILINX_COMMON_BOARD_H + +int board_late_init_xilinx(void); + +#endif /* BOARD_XILINX_COMMON_BOARD_H */ diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 75aedb0929..908ea87163 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -17,6 +17,7 @@ #include #include #include +#include "../common/board.h" DECLARE_GLOBAL_DATA_PTR; @@ -204,9 +205,7 @@ int board_late_init(void) initrd_hi = round_down(initrd_hi, SZ_16M); env_set_addr("initrd_high", (void *)initrd_hi); - env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET); - - return 0; + return board_late_init_xilinx(); } int dram_init_banksize(void) diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 420a5ca663..2164eac8d5 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -17,6 +17,7 @@ #include #include #include +#include "../common/board.h" DECLARE_GLOBAL_DATA_PTR; @@ -76,9 +77,7 @@ int board_late_init(void) env_set("boot_targets", new_targets); - env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET); - - return 0; + return board_late_init_xilinx(); } #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 3c92b1a582..b2172356ad 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -27,6 +27,7 @@ #include #include #include +#include "../common/board.h" #include "pm_cfg_obj.h" @@ -695,11 +696,9 @@ int board_late_init(void) initrd_hi = round_down(initrd_hi, SZ_16M); env_set_addr("initrd_high", (void *)initrd_hi); - env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET); - reset_reason(); - return 0; + return board_late_init_xilinx(); } #endif From dec206a09b660ee1ac58e3cd9a7b2003aeca4381 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 8 Apr 2020 13:24:05 +0200 Subject: [PATCH 05/14] xilinx: zynqmp: Fix MIO 18 configuration on zcu104 revC Without this change QSPI is not detected on zcu104 revC. Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c index 4805e5a3b9..383e3d0c7e 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c @@ -363,6 +363,7 @@ static unsigned long psu_mio_init_data(void) psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U); psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U); psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U); @@ -408,7 +409,7 @@ static unsigned long psu_mio_init_data(void) psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180204, 0x7B3F003FU, 0x52240000U); + psu_mask_write(0xFF180204, 0x7B3F007FU, 0x52240000U); psu_mask_write(0xFF180208, 0xFFFFE000U, 0x00B02000U); psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); From 7eab624baf96a6d967416ffeb51e3fef289c47ae Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Wed, 8 Apr 2020 21:34:54 -0600 Subject: [PATCH 06/14] clk: versal: Fix watchdog clock issue Enable mux based clocks to populate LPD_LSBUS clock to xilinx_wwdt driver. Skip reading clock rate for the mux based clocks with parent clock id is zero. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma --- drivers/clk/clk_versal.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index d3673a5c8b..075a08380d 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -503,6 +503,9 @@ static u64 versal_clock_calc(u32 clk_id) NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF) return versal_clock_ref(clk_id); + if (!parent_id) + return 0; + clk_rate = versal_clock_calc(parent_id); if (versal_clock_div(clk_id)) { @@ -526,7 +529,7 @@ static int versal_clock_get_rate(u32 clk_id, u64 *clk_rate) NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_OUT && ((clk_id >> NODE_CLASS_SHIFT) & NODE_CLASS_MASK) == NODE_CLASS_CLOCK) { - if (!versal_clock_gate(clk_id)) + if (!versal_clock_gate(clk_id) && !versal_clock_mux(clk_id)) return -EINVAL; *clk_rate = versal_clock_calc(clk_id); return 0; From 783814288b28cc6d63117c15b5755f6396f0c799 Mon Sep 17 00:00:00 2001 From: Saeed Nowshadi Date: Fri, 27 Mar 2020 08:12:20 -0700 Subject: [PATCH 07/14] arm64: zynqmp: Add label to GPIO lines for boot mode and POR Add label to GPIO lines controlling boot mode and POR EMIO pins so System Controller can assert those lines on Versal. Signed-off-by: Saeed Nowshadi Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 39b5d7fff9..65cf591494 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -162,9 +162,9 @@ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ - "", "", /* 78 - 79 */ - "", "", "", "", "", /* 80 - 84 */ - "", "", "", "", "", /* 85 -89 */ + "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ + "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */ + "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ From a29511eeca5f00e31653af28b9f758cf39e001fc Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 8 Apr 2020 10:51:36 +0200 Subject: [PATCH 08/14] xilinx: Move initrd_high setup to common location Moving to common location initrd_high is also setup for Zynq which hasn't done in run time code. Signed-off-by: Michal Simek --- board/xilinx/common/board.c | 7 +++++++ board/xilinx/versal/board.c | 6 ------ board/xilinx/zynqmp/zynqmp.c | 6 ------ include/configs/zynq-common.h | 1 - 4 files changed, 7 insertions(+), 13 deletions(-) diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 7c191e53fb..294a59df77 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -8,6 +8,7 @@ #include #include #include +#include #include "board.h" int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) @@ -75,7 +76,13 @@ void *board_fdt_blob_setup(void) int board_late_init_xilinx(void) { + ulong initrd_hi; + env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET); + initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE; + initrd_hi = round_down(initrd_hi, SZ_16M); + env_set_addr("initrd_high", (void *)initrd_hi); + return 0; } diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 908ea87163..2900dfb44e 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "../common/board.h" DECLARE_GLOBAL_DATA_PTR; @@ -94,7 +93,6 @@ int board_late_init(void) const char *mode; char *new_targets; char *env_targets; - ulong initrd_hi; if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { debug("Saved variables - Skipping\n"); @@ -201,10 +199,6 @@ int board_late_init(void) env_set("boot_targets", new_targets); - initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE; - initrd_hi = round_down(initrd_hi, SZ_16M); - env_set_addr("initrd_high", (void *)initrd_hi); - return board_late_init_xilinx(); } diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index b2172356ad..66a43974e6 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -26,7 +26,6 @@ #include #include #include -#include #include "../common/board.h" #include "pm_cfg_obj.h" @@ -565,7 +564,6 @@ int board_late_init(void) char *new_targets; char *env_targets; int ret; - ulong initrd_hi; #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD) usb_ether_init(); @@ -692,10 +690,6 @@ int board_late_init(void) env_set("boot_targets", new_targets); - initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE; - initrd_hi = round_down(initrd_hi, SZ_16M); - env_set_addr("initrd_high", (void *)initrd_hi); - reset_reason(); return board_late_init_xilinx(); diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 1eaf65b0a2..4ccc31e376 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -198,7 +198,6 @@ #ifndef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x20000000\0" \ - "initrd_high=0x20000000\0" \ "scriptaddr=0x20000\0" \ "script_size_f=0x40000\0" \ "fdt_addr_r=0x1f00000\0" \ From 51f6c52e6b12d7bc7a82db566057efe731f5aae9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 8 Apr 2020 11:04:41 +0200 Subject: [PATCH 09/14] xilinx: Move bootmode detection to separate function Create special function for reading bootmode on Versal and ZynqMP. Zynq is using specific function (without mask) already. Future patches will be calling this function from different location too. Signed-off-by: Michal Simek --- board/xilinx/versal/board.c | 23 ++++++++++++++++------- board/xilinx/zynqmp/zynqmp.c | 28 +++++++++++++++++++--------- 2 files changed, 35 insertions(+), 16 deletions(-) diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 2900dfb44e..483e3ce2f7 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -82,9 +82,23 @@ int board_early_init_r(void) return 0; } +static u8 versal_get_bootmode(void) +{ + u8 bootmode; + u32 reg = 0; + + reg = readl(&crp_base->boot_mode_usr); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + bootmode = reg & BOOT_MODES_MASK; + + return bootmode; +} + int board_late_init(void) { - u32 reg = 0; u8 bootmode; struct udevice *dev; int bootseq = -1; @@ -99,12 +113,7 @@ int board_late_init(void) return 0; } - reg = readl(&crp_base->boot_mode_usr); - - if (reg >> BOOT_MODE_ALT_SHIFT) - reg >>= BOOT_MODE_ALT_SHIFT; - - bootmode = reg & BOOT_MODES_MASK; + bootmode = versal_get_bootmode(); puts("Bootmode: "); switch (bootmode) { diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 66a43974e6..a2a0d56331 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -552,9 +552,26 @@ static int set_fdtfile(void) return 0; } +static u8 zynqmp_get_bootmode(void) +{ + u8 bootmode; + u32 reg = 0; + int ret; + + ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®); + if (ret) + return -EINVAL; + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + bootmode = reg & BOOT_MODES_MASK; + + return bootmode; +} + int board_late_init(void) { - u32 reg = 0; u8 bootmode; struct udevice *dev; int bootseq = -1; @@ -578,14 +595,7 @@ int board_late_init(void) if (ret) return ret; - ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®); - if (ret) - return -EINVAL; - - if (reg >> BOOT_MODE_ALT_SHIFT) - reg >>= BOOT_MODE_ALT_SHIFT; - - bootmode = reg & BOOT_MODES_MASK; + bootmode = zynqmp_get_bootmode(); puts("Bootmode: "); switch (bootmode) { From 14c0fbbc94e30ef8a586e9b8685393337246b19d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 30 Mar 2020 11:35:38 +0200 Subject: [PATCH 10/14] arm64: zynqmp: Fix irps5401 device nodes - Do not use irps54012 as device node which is not correct. - Fix addresses of irps5401/u180 on zcu104 revisions. - Remove clock-cells property. It is PMIC without any clock output. - Define irps5401 nodes in zynqmp-e-a2197 Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 16 +++++++++++++--- arch/arm/dts/zynqmp-zcu104-revA.dts | 10 ++++------ arch/arm/dts/zynqmp-zcu104-revC.dts | 10 ++++------ arch/arm/dts/zynqmp-zcu111-revA.dts | 9 +++------ arch/arm/dts/zynqmp-zcu208-revA.dts | 6 ++---- arch/arm/dts/zynqmp-zcu216-revA.dts | 6 ++---- 6 files changed, 28 insertions(+), 29 deletions(-) diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 65cf591494..bf982e2218 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -198,9 +198,6 @@ #size-cells = <0>; reg = <0>; /* u152 IR35215 0x16/0x46 vcc_soc */ - /* u160 IRPS5401 0x17/0x47 */ - /* u167 IRPS5401 0x1c/0x4c */ - /* u175 IRPS5401 0x1d/0x4d */ /* u179 ir38164 0x19/0x49 vcco_500 */ /* u181 ir38164 0x1a/0x4a vcco_501 */ /* u183 ir38164 0x1b/0x4b vcco_502 */ @@ -209,6 +206,19 @@ /* u189 ir38164 0x20/0x50 mgtyavtt */ /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */ /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */ + + irps5401_47: irps5401@47 { /* IRPS5401 - u160 */ + compatible = "infineon,irps5401"; + reg = <0x47>; /* pmbus / i2c 0x17 */ + }; + irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */ + compatible = "infineon,irps5401"; + reg = <0x4c>; /* pmbus / i2c 0x1c */ + }; + irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */ + compatible = "infineon,irps5401"; + reg = <0x4d>; /* pmbus / i2c 0x1d */ + }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 3ceb39dce0..a4bd6b800a 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -147,15 +147,13 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ - #clock-cells = <0>; + irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; - reg = <0x43>; + reg = <0x43>; /* pmbus / i2c 0x13 */ }; - irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ - #clock-cells = <0>; + irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; - reg = <0x4d>; + reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 7dad4523de..d4b3769a27 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -172,15 +172,13 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ - #clock-cells = <0>; + irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; - reg = <0x43>; + reg = <0x43>; /* pmbus / i2c 0x13 */ }; - irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ - #clock-cells = <0>; + irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; - reg = <0x4d>; + reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index d16bf8ac7a..63e285fe9a 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -327,18 +327,15 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ - #clock-cells = <0>; + irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */ compatible = "infineon,irps5401"; reg = <0x43>; }; - irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ - #clock-cells = <0>; + irps5401_44: irps5401@44 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x44>; }; - irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ - #clock-cells = <0>; + irps5401_45: irps5401@45 { /* IRPS5401 - u57 */ compatible = "infineon,irps5401"; reg = <0x45>; }; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 75ecd7a5c2..118a2de96b 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -351,13 +351,11 @@ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ - irps5401_44: irps54012@44 { /* IRPS5401 - u53 */ - #clock-cells = <0>; + irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; - irps5401_45: irps54012@45 { /* IRPS5401 - u55 */ - #clock-cells = <0>; + irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index f3b5edfeb4..e454bfcba7 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -355,13 +355,11 @@ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ - irps5401_44: irps54012@44 { /* IRPS5401 - u53 */ - #clock-cells = <0>; + irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; - irps5401_45: irps54012@45 { /* IRPS5401 - u55 */ - #clock-cells = <0>; + irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; From e86dce1c0c240b8f548d757c80bd65f38d37512e Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Wed, 15 Apr 2020 04:45:02 -0600 Subject: [PATCH 11/14] ARM: zynq: Add nand controller node in zynq-ces-nand dt Add memory-controller@e000e000 node in zynq-ces-nand.dts as zynq_nand driver utilizes flash@e1000000 node. Without this dt node mini nand u-boot does not probe. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- arch/arm/dts/zynq-cse-nand.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts index 1e16d7fab9..32cb3bffcb 100644 --- a/arch/arm/dts/zynq-cse-nand.dts +++ b/arch/arm/dts/zynq-cse-nand.dts @@ -38,6 +38,21 @@ #size-cells = <1>; ranges; + smcc: memory-controller@e000e000 { + #address-cells = <1>; + #size-cells = <1>; + clock-names = "memclk", "apb_pclk"; + clocks = <&clkc 11>, <&clkc 44>; + compatible = "arm,pl353-smc-r2p1", "arm,primecell"; + ranges; + reg = <0xe000e000 0x1000>; + + nand0: flash@e1000000 { + compatible = "arm,pl353-nand-r2p1"; + reg = <0xe1000000 0x1000000>; + }; + }; + slcr: slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <1>; From 7a3e239e90ec6f7a34c73508cf05d181d700c607 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Sun, 19 Apr 2020 22:19:54 -0600 Subject: [PATCH 12/14] ARM: zynq: Change SYS_MALLOC_LEN in zynq_cse_nand_defconfig nand_scan_tail() function allocates memory dynamically for struct nand_buffers which needs ~21kbytes of memory. But the memory alloted with CONFIG_SYS_MALLOC_LEN is 4k which is insufficient. Increase CONFIG_SYS_MALLOC_LEN to 32Kbytes from which struct nand_buffers uses ~21kbytes & remaining memory is used for other. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- configs/zynq_cse_nand_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig index 2b58c461c3..80a427d905 100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_ICACHE_OFF=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x100000 -CONFIG_SYS_MALLOC_LEN=0x1000 +CONFIG_SYS_MALLOC_LEN=0x8000 CONFIG_ENV_SIZE=0x190 CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y From 19d130450544f505589b25afc30508136ab52b71 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 20 Apr 2020 09:17:53 +0200 Subject: [PATCH 13/14] xilinx: Make Xilinx custom distro boot commands more verbose Extend description of Xilinx custom boot commands to make clear what runs and what failed. Signed-off-by: Michal Simek --- include/configs/xilinx_versal.h | 12 ++++++++---- include/configs/xilinx_zynqmp.h | 9 ++++++--- include/configs/zynq-common.h | 12 ++++++++---- 3 files changed, 22 insertions(+), 11 deletions(-) diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index dec5001b5f..0c259a181f 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -109,7 +109,8 @@ #define BOOTENV_DEV_XSPI(devtypeu, devtypel, instance) \ "bootcmd_xspi0=sf probe 0 0 0 && " \ "sf read $scriptaddr $script_offset_f $script_size_f && " \ - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" + "echo XSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \ "xspi " @@ -117,7 +118,8 @@ #define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) #define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ - "bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0" + "bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ "jtag " @@ -126,8 +128,10 @@ #define BOOTENV_DEV_DFU_USB(devtypeu, devtypel, instance) \ "bootcmd_dfu_usb=setenv dfu_alt_info boot.scr ram $scriptaddr " \ - "$script_size_f; dfu 0 ram 0 && source $scriptaddr; " \ - "echo SCRIPT FAILED: continuing...;\0" + "$script_size_f; dfu 0 ram 0 && " \ + "echo DFU: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; " \ + "echo DFU: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_DFU_USB(devtypeu, devtypel, instance) \ "dfu_usb " diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 010738363d..eddc2b4020 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -160,7 +160,8 @@ #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ "bootcmd_" #devtypel #instance "=sf probe " #instance " 0 0 && " \ "sf read $scriptaddr $script_offset_f $script_size_f && " \ - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ #devtypel #instance " " @@ -168,7 +169,8 @@ #define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ "bootcmd_" #devtypel #instance "= nand info && " \ "nand read $scriptaddr $script_offset_f $script_size_f && " \ - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" + "echo NAND: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo NAND: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ #devtypel #instance " " @@ -176,7 +178,8 @@ #define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) #define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ - "bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0" + "bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ "jtag " diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 4ccc31e376..a93172b02c 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -152,7 +152,8 @@ #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ "bootcmd_qspi=sf probe 0 0 0 && " \ "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ "qspi " @@ -160,7 +161,8 @@ #define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ "bootcmd_nand=nand info && " \ "nand read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" + "echo NAND: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo NAND: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ "nand " @@ -168,7 +170,8 @@ #define BOOTENV_DEV_NOR(devtypeu, devtypel, instance) \ "script_offset_nor=0xE2FC0000\0" \ "bootcmd_nor=cp.b ${script_offset_nor} ${scriptaddr} ${script_size_f} && " \ - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" + "echo NOR: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo NOR: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_NOR(devtypeu, devtypel, instance) \ "nor " @@ -176,7 +179,8 @@ #define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) #define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ - "bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0" + "bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ "jtag " From 27d706937a5c72f0414a540ca20fd36b4b72bda7 Mon Sep 17 00:00:00 2001 From: Patrick van Gelder Date: Fri, 24 Apr 2020 01:28:56 -0600 Subject: [PATCH 14/14] ARM: zynq: Fix invalid check on NAND_CMD_NONE. The end_cmd field in the variables cmd_phase_addr and data_phase_addr contains the value 0xFF when the end_cmd equals NAND_CMD_NONE. This should be 0x00. This is caused by comparing NAND_CMD_NONE (int) with end_cmd (u8). end_cmd will be promoted by the int value -1 and therefore is not equal to 0xFF. Solved by casting NAND_CMD_NONE to u8 which will avoid int promotion. Signed-off-by: Patrick van Gelder Reviewed-by: T Karthik Reddy Signed-off-by: Michal Simek --- drivers/mtd/nand/raw/zynq_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c index 0aea83dac0..3941297418 100644 --- a/drivers/mtd/nand/raw/zynq_nand.c +++ b/drivers/mtd/nand/raw/zynq_nand.c @@ -845,7 +845,7 @@ static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command, if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE) end_cmd_valid = 1; - if (curr_cmd->end_cmd == NAND_CMD_NONE) + if (curr_cmd->end_cmd == (u8)NAND_CMD_NONE) end_cmd = 0x0; else end_cmd = curr_cmd->end_cmd;