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ARM: tegra: pinctrl: make pmux_func values consistent on Tegra20
For consistency with other SoCs, modify Tegra20's enum pmux_func to: * Remove PMUX_FUNC values that aren't real * Use the same PMUX_FUNC_RSVD[1-4] values, and ensure (RSVD1 & 3)==0; this will be assumed by pinmux_set_func() in a future patch. Unfortunately, PMUX_FUNC_RSVD is still used in the pin macros. Use a private define inside the driver to prevent this from causing compilaton errors. This will be cleaned up when the pin tables are re-written in a later patch in this series. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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dd45948dd7
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2 changed files with 10 additions and 11 deletions
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@ -307,7 +307,9 @@ struct tegra_pingroup_desc {
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/* A pin group number which is not used */
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#define PIN_RESERVED \
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PIN(NONE, NONE, NONE, NONE, NONE, NONE, NONE)
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PIN(NONE, NONE, RSVD, RSVD, RSVD, RSVD, RSVD)
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#define PMUX_FUNC_RSVD ((enum pmux_func)-1)
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const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
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PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE),
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@ -228,21 +228,18 @@ enum pmux_func {
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PMUX_FUNC_VI_SENSOR_CLK,
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PMUX_FUNC_XIO,
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/* These don't have a name, but can be used in the table */
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PMUX_FUNC_RSVD1,
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PMUX_FUNC_RSVD2,
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PMUX_FUNC_RSVD3,
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PMUX_FUNC_RSVD4,
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PMUX_FUNC_RSVD, /* Not valid and should not be used */
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PMUX_FUNC_COUNT,
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PMUX_FUNC_NONE = -1,
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PMUX_FUNC_RSVD1 = 0x8000,
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PMUX_FUNC_RSVD2 = 0x8001,
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PMUX_FUNC_RSVD3 = 0x8002,
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PMUX_FUNC_RSVD4 = 0x8003,
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};
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/* return 1 if a pmux_func is in range */
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#define pmux_func_isvalid(func) ((func) >= 0 && (func) < PMUX_FUNC_COUNT && \
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(func) != PMUX_FUNC_RSVD)
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#define pmux_func_isvalid(func) \
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((((func) >= 0) && ((func) < PMUX_FUNC_COUNT)) ||\
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(((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
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/* The pullup/pulldown state of a pin group */
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enum pmux_pull {
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