mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-03 01:50:25 +00:00
arm: dts: k3-j7200: Sync Linux v5.11-rc6 dts into U-Boot
Sync all J7200 related v5.11-rc6 Linux kernel dts into U-Boot. MCU R5F nodes are not yet added in Linux kernel yet but were added in U-Boot. In order to avoid regressions, r5f nodes are kept intact. These will be added in kernel in future. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla
parent
70e167495a
commit
6239cc8c4e
6 changed files with 584 additions and 216 deletions
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@ -11,13 +11,13 @@
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aliases {
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ethernet0 = &cpsw_port1;
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i2c0 = &wkup_i2c0;
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i2c1 = &mcu_i2c0;
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i2c2 = &mcu_i2c1;
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i2c3 = &main_i2c0;
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};
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};
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&chipid {
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u-boot,dm-spl;
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};
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&cbass_main {
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u-boot,dm-spl;
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};
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@ -36,6 +36,10 @@
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clock-frequency = <25000000>;
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u-boot,dm-spl;
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};
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chipid@43000014 {
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u-boot,dm-spl;
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};
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};
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&secure_proxy_main {
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@ -136,10 +140,6 @@
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u-boot,dm-spl;
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};
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&wkup_gpio0 {
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u-boot,dm-spl;
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};
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&mcu_fss0_hpb0_pins_default {
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u-boot,dm-spl;
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};
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@ -5,9 +5,10 @@
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/dts-v1/;
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#include <dt-bindings/net/ti-dp83867.h>
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#include "k3-j7200-som-p0.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/net/ti-dp83867.h>
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#include <dt-bindings/mux/ti-serdes.h>
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/ {
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chosen {
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@ -60,7 +61,7 @@
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>;
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};
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mcu_cpsw_pins_default: mcu_cpsw_pins_default {
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mcu_cpsw_pins_default: mcu-cpsw-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
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J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
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@ -77,7 +78,7 @@
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>;
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};
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mcu_mdio_pins_default: mcu_mdio1_pins_default {
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mcu_mdio_pins_default: mcu-mdio1-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
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J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
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@ -93,7 +94,14 @@
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>;
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};
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main_mmc1_pins_default: main_mmc1_pins_default {
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main_i2c1_pins_default: main-i2c1-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
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J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
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>;
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};
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main_mmc1_pins_default: main-mmc1-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
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J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
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@ -112,7 +120,7 @@
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>;
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};
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main_usbss0_pins_default: main_usbss0_pins_default {
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main_usbss0_pins_default: main-usbss0-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
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>;
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@ -121,16 +129,17 @@
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&wkup_uart0 {
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/* Wakeup UART is used by System firmware */
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status = "disabled";
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status = "reserved";
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};
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&main_uart0 {
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/* Shared with ATF on this platform */
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power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
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};
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&main_uart2 {
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/* MAIN UART 2 is used by R5F firmware */
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status = "disabled";
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status = "reserved";
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};
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&main_uart3 {
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@ -168,27 +177,22 @@
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status = "disabled";
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};
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&wkup_i2c0 {
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&mcu_cpsw {
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pinctrl-names = "default";
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pinctrl-0 = <&wkup_i2c0_pins_default>;
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clock-frequency = <400000>;
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pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
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};
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&main_sdhci0 {
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/* eMMC */
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non-removable;
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ti,driver-strength-ohm = <50>;
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disable-wp;
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&davinci_mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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};
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&main_sdhci1 {
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/* SD card */
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pinctrl-0 = <&main_mmc1_pins_default>;
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pinctrl-names = "default";
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vmmc-supply = <&vdd_mmc1>;
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vqmmc-supply = <&vdd_sd_dv>;
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ti,driver-strength-ohm = <50>;
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disable-wp;
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&cpsw_port1 {
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phy-mode = "rgmii-rxid";
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phy-handle = <&phy0>;
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};
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&main_i2c0 {
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@ -211,6 +215,55 @@
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};
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};
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/*
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* The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
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* swapped on the CPB.
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*
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* main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
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* The i2c1 of the CPB (as it is labeled) is not connected to j7200.
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*/
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&main_i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c1_pins_default>;
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clock-frequency = <400000>;
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exp3: gpio@20 {
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compatible = "ti,tca6408";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
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"UB926_LOCK", "UB926_PWR_SW_CNTRL",
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"UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
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};
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};
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&main_sdhci0 {
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/* eMMC */
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non-removable;
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ti,driver-strength-ohm = <50>;
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disable-wp;
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};
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&main_sdhci1 {
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/* SD card */
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pinctrl-0 = <&main_mmc1_pins_default>;
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pinctrl-names = "default";
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vmmc-supply = <&vdd_mmc1>;
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vqmmc-supply = <&vdd_sd_dv>;
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ti,driver-strength-ohm = <50>;
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disable-wp;
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};
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&serdes_ln_ctrl {
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idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
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<J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
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};
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&usb_serdes_mux {
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idle-states = <1>; /* USB0 to SERDES lane 3 */
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};
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&usbss0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_usbss0_pins_default>;
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@ -223,25 +276,8 @@
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maximum-speed = "high-speed";
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};
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&wkup_gpio0 {
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pinctrl-names = "default";
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pinctrl-0 = <&wkup_gpio_pins_default>;
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};
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&mcu_cpsw {
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
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};
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&davinci_mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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&tscadc0 {
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adc {
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ti,adc-channels = <0 1 2 3 4 5 6 7>;
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};
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};
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&cpsw_port1 {
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phy-mode = "rgmii-rxid";
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phy-handle = <&phy0>;
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};
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@ -8,13 +8,34 @@
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&cbass_main {
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msmc_ram: sram@70000000 {
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compatible = "mmio-sram";
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reg = <0x0 0x70000000 0x0 0x100000>;
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reg = <0x00 0x70000000 0x00 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x70000000 0x100000>;
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ranges = <0x00 0x00 0x70000000 0x100000>;
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atf-sram@0 {
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reg = <0x0 0x20000>;
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reg = <0x00 0x20000>;
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};
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};
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scm_conf: scm-conf@100000 {
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compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
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reg = <0x00 0x00100000 0x00 0x1c000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x00 0x00100000 0x1c000>;
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serdes_ln_ctrl: serdes-ln-ctrl@4080 {
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compatible = "mmio-mux";
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#mux-control-cells = <1>;
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mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
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<0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
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};
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usb_serdes_mux: mux-controller@4000 {
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compatible = "mmio-mux";
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#mux-control-cells = <1>;
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mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
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};
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};
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@ -40,11 +61,48 @@
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};
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};
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main_navss: navss@30000000 {
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main_gpio_intr: interrupt-controller0 {
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compatible = "ti,sci-intr";
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ti,intr-trigger-type = <1>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <1>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <131>;
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ti,interrupt-ranges = <8 392 56>;
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};
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main_navss: bus@30000000 {
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
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ti,sci-dev-id = <199>;
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main_navss_intr: interrupt-controller1 {
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compatible = "ti,sci-intr";
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ti,intr-trigger-type = <4>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <1>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <213>;
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ti,interrupt-ranges = <0 64 64>,
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<64 448 64>,
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<128 672 64>;
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};
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main_udmass_inta: msi-controller@33d00000 {
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compatible = "ti,sci-inta";
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reg = <0x00 0x33d00000 0x00 0x100000>;
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interrupt-controller;
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#interrupt-cells = <0>;
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interrupt-parent = <&main_navss_intr>;
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msi-controller;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <209>;
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ti,interrupt-ranges = <0 0 256>;
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};
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secure_proxy_main: mailbox@32c00000 {
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compatible = "ti,am654-secure-proxy";
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@ -56,12 +114,174 @@
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interrupt-names = "rx_011";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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};
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hwspinlock: spinlock@30e00000 {
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compatible = "ti,am654-hwspinlock";
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reg = <0x00 0x30e00000 0x00 0x1000>;
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#hwlock-cells = <1>;
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};
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main_pmx0: pinmux@11c000 {
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mailbox0_cluster0: mailbox@31f80000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f80000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&main_navss_intr>;
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};
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mailbox0_cluster1: mailbox@31f81000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f81000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&main_navss_intr>;
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};
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mailbox0_cluster2: mailbox@31f82000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f82000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&main_navss_intr>;
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};
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mailbox0_cluster3: mailbox@31f83000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f83000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&main_navss_intr>;
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};
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mailbox0_cluster4: mailbox@31f84000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f84000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&main_navss_intr>;
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};
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mailbox0_cluster5: mailbox@31f85000 {
|
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compatible = "ti,am654-mailbox";
|
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reg = <0x00 0x31f85000 0x00 0x200>;
|
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#mbox-cells = <1>;
|
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&main_navss_intr>;
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};
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|
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mailbox0_cluster6: mailbox@31f86000 {
|
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f86000 0x00 0x200>;
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#mbox-cells = <1>;
|
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
|
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interrupt-parent = <&main_navss_intr>;
|
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};
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|
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mailbox0_cluster7: mailbox@31f87000 {
|
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compatible = "ti,am654-mailbox";
|
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reg = <0x00 0x31f87000 0x00 0x200>;
|
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#mbox-cells = <1>;
|
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ti,mbox-num-users = <4>;
|
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ti,mbox-num-fifos = <16>;
|
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interrupt-parent = <&main_navss_intr>;
|
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};
|
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|
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mailbox0_cluster8: mailbox@31f88000 {
|
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compatible = "ti,am654-mailbox";
|
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reg = <0x00 0x31f88000 0x00 0x200>;
|
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#mbox-cells = <1>;
|
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ti,mbox-num-users = <4>;
|
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ti,mbox-num-fifos = <16>;
|
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interrupt-parent = <&main_navss_intr>;
|
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};
|
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|
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mailbox0_cluster9: mailbox@31f89000 {
|
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compatible = "ti,am654-mailbox";
|
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reg = <0x00 0x31f89000 0x00 0x200>;
|
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#mbox-cells = <1>;
|
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ti,mbox-num-users = <4>;
|
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ti,mbox-num-fifos = <16>;
|
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interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
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mailbox0_cluster10: mailbox@31f8a000 {
|
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compatible = "ti,am654-mailbox";
|
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reg = <0x00 0x31f8a000 0x00 0x200>;
|
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
mailbox0_cluster11: mailbox@31f8b000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f8b000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&main_navss_intr>;
|
||||
};
|
||||
|
||||
main_ringacc: ringacc@3c000000 {
|
||||
compatible = "ti,am654-navss-ringacc";
|
||||
reg = <0x00 0x3c000000 0x00 0x400000>,
|
||||
<0x00 0x38000000 0x00 0x400000>,
|
||||
<0x00 0x31120000 0x00 0x100>,
|
||||
<0x00 0x33000000 0x00 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||
ti,num-rings = <1024>;
|
||||
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <211>;
|
||||
msi-parent = <&main_udmass_inta>;
|
||||
};
|
||||
|
||||
main_udmap: dma-controller@31150000 {
|
||||
compatible = "ti,j721e-navss-main-udmap";
|
||||
reg = <0x00 0x31150000 0x00 0x100>,
|
||||
<0x00 0x34000000 0x00 0x100000>,
|
||||
<0x00 0x35000000 0x00 0x100000>;
|
||||
reg-names = "gcfg", "rchanrt", "tchanrt";
|
||||
msi-parent = <&main_udmass_inta>;
|
||||
#dma-cells = <1>;
|
||||
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <212>;
|
||||
ti,ringacc = <&main_ringacc>;
|
||||
|
||||
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
|
||||
<0x0f>, /* TX_HCHAN */
|
||||
<0x10>; /* TX_UHCHAN */
|
||||
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
|
||||
<0x0b>, /* RX_HCHAN */
|
||||
<0x0c>; /* RX_UHCHAN */
|
||||
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
|
||||
};
|
||||
|
||||
cpts@310d0000 {
|
||||
compatible = "ti,j721e-cpts";
|
||||
reg = <0x00 0x310d0000 0x00 0x400>;
|
||||
reg-names = "cpts";
|
||||
clocks = <&k3_clks 201 1>;
|
||||
clock-names = "cpts";
|
||||
interrupts-extended = <&main_navss_intr 391>;
|
||||
interrupt-names = "cpts";
|
||||
ti,cpts-periodic-outputs = <6>;
|
||||
ti,cpts-ext-ts-inputs = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
main_pmx0: pinctrl@11c000 {
|
||||
compatible = "pinctrl-single";
|
||||
/* Proxy 0 addressing */
|
||||
reg = <0x0 0x11c000 0x0 0x2b4>;
|
||||
reg = <0x00 0x11c000 0x00 0x2b4>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
|
|
@ -197,28 +417,6 @@
|
|||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_gpio0: gpio@600000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x0 0x00600000 0x0 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 3 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 4 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 5 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 6 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 7 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 105 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_sdhci0: sdhci@4f80000 {
|
||||
compatible = "ti,j721e-sdhci-8bit";
|
||||
reg = <0x0 0x04f80000 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;
|
||||
|
|
@ -259,18 +457,18 @@
|
|||
|
||||
main_i2c0: i2c@2000000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x2000000 0x0 0x100>;
|
||||
reg = <0x00 0x2000000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 187 1>;
|
||||
power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
|
||||
power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
|
||||
};
|
||||
|
||||
main_i2c1: i2c@2010000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x2010000 0x0 0x100>;
|
||||
reg = <0x00 0x2010000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -281,7 +479,7 @@
|
|||
|
||||
main_i2c2: i2c@2020000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x2020000 0x0 0x100>;
|
||||
reg = <0x00 0x2020000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -292,7 +490,7 @@
|
|||
|
||||
main_i2c3: i2c@2030000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x2030000 0x0 0x100>;
|
||||
reg = <0x00 0x2030000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -303,7 +501,7 @@
|
|||
|
||||
main_i2c4: i2c@2040000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x2040000 0x0 0x100>;
|
||||
reg = <0x00 0x2040000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -314,7 +512,7 @@
|
|||
|
||||
main_i2c5: i2c@2050000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x2050000 0x0 0x100>;
|
||||
reg = <0x00 0x2050000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -325,7 +523,7 @@
|
|||
|
||||
main_i2c6: i2c@2060000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x2060000 0x0 0x100>;
|
||||
reg = <0x00 0x2060000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -334,13 +532,35 @@
|
|||
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
usbss0: cdns_usb@4104000 {
|
||||
main_gpio0: gpio@600000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x0 0x00600000 0x0 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 3 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 4 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 5 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 6 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 7 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 105 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
usbss0: cdns-usb@4104000 {
|
||||
compatible = "ti,j721e-usb";
|
||||
reg = <0x00 0x4104000 0x00 0x100>;
|
||||
dma-coherent;
|
||||
power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
|
||||
clock-names = "usb2_refclk", "lpm_clk";
|
||||
clock-names = "ref", "lpm";
|
||||
assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
|
||||
assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
|
||||
#address-cells = <2>;
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
<&secure_proxy_main 13>;
|
||||
|
||||
reg-names = "debug_messages";
|
||||
reg = <0x00 0x44083000 0x0 0x1000>;
|
||||
reg = <0x00 0x44083000 0x00 0x1000>;
|
||||
|
||||
k3_pds: power-controller {
|
||||
compatible = "ti,sci-pm-domain";
|
||||
|
|
@ -34,12 +34,26 @@
|
|||
};
|
||||
};
|
||||
|
||||
chipid: chipid@43000014 {
|
||||
compatible = "ti,am654-chipid";
|
||||
reg = <0x0 0x43000014 0x0 0x4>;
|
||||
mcu_conf: syscon@40f00000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x00 0x40f00000 0x00 0x20000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00 0x00 0x40f00000 0x20000>;
|
||||
|
||||
phy_gmii_sel: phy@4040 {
|
||||
compatible = "ti,am654-phy-gmii-sel";
|
||||
reg = <0x4040 0x4>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
wkup_pmx0: pinmux@4301c000 {
|
||||
chipid@43000014 {
|
||||
compatible = "ti,am654-chipid";
|
||||
reg = <0x00 0x43000014 0x00 0x4>;
|
||||
};
|
||||
|
||||
wkup_pmx0: pinctrl@4301c000 {
|
||||
compatible = "pinctrl-single";
|
||||
/* Proxy 0 addressing */
|
||||
reg = <0x00 0x4301c000 0x00 0x178>;
|
||||
|
|
@ -51,7 +65,7 @@
|
|||
mcu_ram: sram@41c00000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00 0x41c00000 0x00 0x100000>;
|
||||
ranges = <0x0 0x00 0x41c00000 0x100000>;
|
||||
ranges = <0x00 0x00 0x41c00000 0x100000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
|
@ -69,17 +83,6 @@
|
|||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
wkup_i2c0: i2c@42120000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x42120000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 197 1>;
|
||||
power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
mcu_uart0: serial@40a00000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x40a00000 0x00 0x100>;
|
||||
|
|
@ -93,84 +96,47 @@
|
|||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
fss: system-controller@47000000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x0 0x47000000 0x0 0x100>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
hbmc_mux: hbmc-mux {
|
||||
compatible = "mmio-mux";
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x4 0x2>; /* HBMC select */
|
||||
wkup_gpio_intr: interrupt-controller2 {
|
||||
compatible = "ti,sci-intr";
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <137>;
|
||||
ti,interrupt-ranges = <16 960 16>;
|
||||
};
|
||||
|
||||
hbmc: hyperbus@47034000 {
|
||||
compatible = "ti,am654-hbmc";
|
||||
reg = <0x0 0x47034000 0x0 0x100>,
|
||||
<0x5 0x00000000 0x1 0x0000000>;
|
||||
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
mux-controls = <&hbmc_mux 0>;
|
||||
clocks = <&k3_clks 102 5>;
|
||||
assigned-clocks = <&k3_clks 102 5>;
|
||||
assigned-clock-rates = <333333333>;
|
||||
};
|
||||
};
|
||||
|
||||
mcu_i2c0: i2c@40b00000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x40b00000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 194 1>;
|
||||
power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
mcu_i2c1: i2c@40b10000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x40b10000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 195 1>;
|
||||
power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
cbass_mcu_navss: mcu-navss {
|
||||
mcu_navss: bus@28380000 {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
|
||||
ti,sci-dev-id = <232>;
|
||||
|
||||
mcu_ringacc: ringacc@2b800000 {
|
||||
compatible = "ti,am654-navss-ringacc";
|
||||
reg = <0x0 0x2b800000 0x0 0x400000>,
|
||||
<0x0 0x2b000000 0x0 0x400000>,
|
||||
<0x0 0x28590000 0x0 0x100>,
|
||||
<0x0 0x2a500000 0x0 0x40000>;
|
||||
reg = <0x00 0x2b800000 0x00 0x400000>,
|
||||
<0x00 0x2b000000 0x00 0x400000>,
|
||||
<0x00 0x28590000 0x00 0x100>,
|
||||
<0x00 0x2a500000 0x00 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||
ti,num-rings = <286>;
|
||||
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <235>;
|
||||
msi-parent = <&main_udmass_inta>;
|
||||
};
|
||||
|
||||
mcu_udmap: dma-controller@285c0000 {
|
||||
compatible = "ti,j721e-navss-mcu-udmap";
|
||||
reg = <0x0 0x285c0000 0x0 0x100>,
|
||||
<0x0 0x2a800000 0x0 0x40000>,
|
||||
<0x0 0x2aa00000 0x0 0x40000>;
|
||||
reg = <0x00 0x285c0000 0x00 0x100>,
|
||||
<0x00 0x2a800000 0x00 0x40000>,
|
||||
<0x00 0x2aa00000 0x00 0x40000>;
|
||||
reg-names = "gcfg", "rchanrt", "tchanrt";
|
||||
msi-parent = <&main_udmass_inta>;
|
||||
#dma-cells = <1>;
|
||||
|
||||
ti,sci = <&dmsc>;
|
||||
|
|
@ -185,40 +151,13 @@
|
|||
};
|
||||
};
|
||||
|
||||
wkup_gpio0: gpio@42110000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x0 0x42110000 0x0 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ti,ngpio = <84>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 113 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
mcu_conf: scm_conf@40f00000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x0 0x40f00000 0x0 0x20000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x40f00000 0x20000>;
|
||||
|
||||
phy_gmii_sel: phy@4040 {
|
||||
compatible = "ti,am654-cpsw-phy-sel";
|
||||
reg = <0x4040 0x4>;
|
||||
reg-names = "gmii-sel";
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
mcu_cpsw: ethernet@46000000 {
|
||||
compatible = "ti,j721e-cpsw-nuss";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
reg = <0x0 0x46000000 0x0 0x200000>;
|
||||
reg = <0x00 0x46000000 0x00 0x200000>;
|
||||
reg-names = "cpsw_nuss";
|
||||
ranges;
|
||||
ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
|
||||
dma-coherent;
|
||||
clocks = <&k3_clks 18 21>;
|
||||
clock-names = "fck";
|
||||
|
|
@ -244,7 +183,7 @@
|
|||
cpsw_port1: port@1 {
|
||||
reg = <1>;
|
||||
ti,mac-only;
|
||||
ti,label = "port1";
|
||||
label = "port1";
|
||||
ti,syscon-efuse = <&mcu_conf 0x200>;
|
||||
phys = <&phy_gmii_sel 1>;
|
||||
};
|
||||
|
|
@ -252,7 +191,7 @@
|
|||
|
||||
davinci_mdio: mdio@f00 {
|
||||
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
||||
reg = <0x0 0xf00 0x0 0x100>;
|
||||
reg = <0x00 0xf00 0x00 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&k3_clks 18 21>;
|
||||
|
|
@ -260,7 +199,9 @@
|
|||
bus_freq = <1000000>;
|
||||
};
|
||||
|
||||
cpts {
|
||||
cpts@3d000 {
|
||||
compatible = "ti,am65-cpts";
|
||||
reg = <0x00 0x3d000 0x00 0x400>;
|
||||
clocks = <&k3_clks 18 2>;
|
||||
clock-names = "cpts";
|
||||
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -270,6 +211,85 @@
|
|||
};
|
||||
};
|
||||
|
||||
mcu_i2c0: i2c@40b00000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x40b00000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 194 1>;
|
||||
power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
mcu_i2c1: i2c@40b10000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x40b10000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 195 1>;
|
||||
power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
wkup_i2c0: i2c@42120000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x42120000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 197 1>;
|
||||
power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
|
||||
};
|
||||
|
||||
fss: syscon@47000000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x00 0x47000000 0x00 0x100>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
hbmc_mux: hbmc-mux {
|
||||
compatible = "mmio-mux";
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x4 0x2>; /* HBMC select */
|
||||
};
|
||||
|
||||
hbmc: hyperbus@47034000 {
|
||||
compatible = "ti,am654-hbmc";
|
||||
reg = <0x00 0x47034000 0x00 0x100>,
|
||||
<0x05 0x00000000 0x01 0x0000000>;
|
||||
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 102 0>;
|
||||
assigned-clocks = <&k3_clks 102 5>;
|
||||
assigned-clock-rates = <333333333>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
mux-controls = <&hbmc_mux 0>;
|
||||
};
|
||||
};
|
||||
|
||||
tscadc0: tscadc@40200000 {
|
||||
compatible = "ti,am3359-tscadc";
|
||||
reg = <0x00 0x40200000 0x00 0x1000>;
|
||||
interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 0 1>;
|
||||
assigned-clocks = <&k3_clks 0 3>;
|
||||
assigned-clock-rates = <60000000>;
|
||||
clock-names = "adc_tsc_fck";
|
||||
dmas = <&main_udmap 0x7400>,
|
||||
<&main_udmap 0x7401>;
|
||||
dma-names = "fifo0", "fifo1";
|
||||
|
||||
adc {
|
||||
#io-channel-cells = <1>;
|
||||
compatible = "ti,am3359-adc";
|
||||
};
|
||||
};
|
||||
|
||||
mcu_r5fss0: r5fss@41000000 {
|
||||
compatible = "ti,j7200-r5fss";
|
||||
ti,cluster-mode = <1>;
|
||||
|
|
|
|||
|
|
@ -11,8 +11,8 @@
|
|||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 4G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
|
||||
<0x00000008 0x80000000 0x00000000 0x80000000>;
|
||||
reg = <0x00 0x80000000 0x00 0x80000000>,
|
||||
<0x08 0x80000000 0x00 0x80000000>;
|
||||
};
|
||||
|
||||
reserved_memory: reserved-memory {
|
||||
|
|
@ -48,15 +48,112 @@
|
|||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_i2c0_pins_default: main-i2c0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
|
||||
J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&hbmc {
|
||||
/* OSPI and HBMC are muxed inside FSS, Bootloader will enable
|
||||
* appropriate node based on board detection
|
||||
*/
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
|
||||
ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */
|
||||
<0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */
|
||||
ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
|
||||
<0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cypress,hyperflash", "cfi-flash";
|
||||
reg = <0x0 0x0 0x4000000>;
|
||||
reg = <0x00 0x00 0x4000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster7 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster8 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster9 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster10 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster11 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
exp_som: gpio@21 {
|
||||
compatible = "ti,tca6408";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
|
||||
"CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
|
||||
"UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL",
|
||||
"GPIO_LIN_EN", "CAN_STB";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -30,18 +30,10 @@
|
|||
serial9 = &main_uart7;
|
||||
serial10 = &main_uart8;
|
||||
serial11 = &main_uart9;
|
||||
i2c0 = &wkup_i2c0;
|
||||
i2c1 = &mcu_i2c0;
|
||||
i2c2 = &mcu_i2c1;
|
||||
i2c3 = &main_i2c0;
|
||||
i2c4 = &main_i2c1;
|
||||
i2c5 = &main_i2c2;
|
||||
i2c6 = &main_i2c3;
|
||||
i2c7 = &main_i2c4;
|
||||
i2c8 = &main_i2c5;
|
||||
i2c9 = &main_i2c6;
|
||||
};
|
||||
|
||||
chosen { };
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -63,7 +55,7 @@
|
|||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
|
|
@ -77,7 +69,7 @@
|
|||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
|
|
@ -132,11 +124,12 @@
|
|||
#size-cells = <2>;
|
||||
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
|
||||
<0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
|
||||
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
|
||||
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
|
||||
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT */
|
||||
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
|
||||
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
|
||||
|
||||
/* MCUSS_WKUP Range */
|
||||
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
|
||||
|
|
@ -150,7 +143,8 @@
|
|||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>;
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
|
||||
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
|
||||
|
||||
cbass_mcu_wakeup: bus@28380000 {
|
||||
compatible = "simple-bus";
|
||||
|
|
@ -167,7 +161,8 @@
|
|||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>; /* FSS OSPI0 data region 3 */
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
|
||||
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue