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Merge branch '2023-12-15-assorted-TI-platform-updates' into next

Browse source 
- Assorted updates and fixes for some TI K3 platforms and SoCs
This commit is contained in:
Tom Rini 2023-12-15 16:20:24 -05:00
commit 57e584d941
13 changed files with 419 additions and 973 deletions
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66
arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
View file

@ -5,72 +5,6 @@
#include "k3-binman.dtsi"
#ifndef CONFIG_ARM64
&bcfg_yaml {
schema = "../../ti/common/schema.yaml";
};
&pcfg_yaml {
schema = "../../ti/common/schema.yaml";
};
&rcfg_yaml {
schema = "../../ti/common/schema.yaml";
};
&scfg_yaml {
schema = "../../ti/common/schema.yaml";
};
/* combined-tifs-cfg */
&bcfg_yaml_tifs {
schema = "../../ti/common/schema.yaml";
};
&pcfg_yaml_tifs {
schema = "../../ti/common/schema.yaml";
};
&rcfg_yaml_tifs {
schema = "../../ti/common/schema.yaml";
};
&scfg_yaml_tifs {
schema = "../../ti/common/schema.yaml";
};
/* combined-dm-cfg */
&pcfg_yaml_dm {
schema = "../../ti/common/schema.yaml";
};
&rcfg_yaml_dm {
schema = "../../ti/common/schema.yaml";
};
/* combined-sysfw-cfg */
&bcfg_yaml_sysfw {
schema = "../../ti/common/schema.yaml";
};
&pcfg_yaml_sysfw {
schema = "../../ti/common/schema.yaml";
};
&rcfg_yaml_sysfw {
schema = "../../ti/common/schema.yaml";
};
&scfg_yaml_sysfw {
schema = "../../ti/common/schema.yaml";
};
#endif /* CONFIG_ARM64 */
#ifdef CONFIG_TARGET_VERDIN_AM62_R5
&binman {

28
arch/arm/dts/k3-binman.dtsi
View file

@ -32,28 +32,28 @@
filename = "board-cfg.bin";
bcfg_yaml: ti-board-config {
config = "board-cfg.yaml";
schema = "board/ti/common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
};
pm-cfg {
filename = "pm-cfg.bin";
pcfg_yaml: ti-board-config {
config = "pm-cfg.yaml";
schema = "board/ti/common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
};
rm-cfg {
filename = "rm-cfg.bin";
rcfg_yaml: ti-board-config {
config = "rm-cfg.yaml";
schema = "board/ti/common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
};
sec-cfg {
filename = "sec-cfg.bin";
scfg_yaml: ti-board-config {
config = "sec-cfg.yaml";
schema = "board/ti/common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
};
combined-tifs-cfg {
@ -61,19 +61,19 @@
ti-board-config {
bcfg_yaml_tifs: board-cfg {
config = "board-cfg.yaml";
schema = "board/ti/common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
scfg_yaml_tifs: sec-cfg {
config = "sec-cfg.yaml";
schema = "board/ti/common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
pcfg_yaml_tifs: pm-cfg {
config = "pm-cfg.yaml";
schema = "board/ti/common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
rcfg_yaml_tifs: rm-cfg {
config = "rm-cfg.yaml";
schema = "board/ti/common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
};
};
@ -82,11 +82,11 @@
ti-board-config {
pcfg_yaml_dm: pm-cfg {
config = "pm-cfg.yaml";
schema = "board/ti/common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
rcfg_yaml_dm: rm-cfg {
config = "rm-cfg.yaml";
schema = "board/ti/common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
};
};
@ -95,19 +95,19 @@
ti-board-config {
bcfg_yaml_sysfw: board-cfg {
config = "board-cfg.yaml";
schema = "board/ti/common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
scfg_yaml_sysfw: sec-cfg {
config = "sec-cfg.yaml";
schema = "board/ti/common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
pcfg_yaml_sysfw: pm-cfg {
config = "pm-cfg.yaml";
schema = "board/ti/common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
rcfg_yaml_sysfw: rm-cfg {
config = "rm-cfg.yaml";
schema = "board/ti/common/schema.yaml";
schema = "arch/arm/mach-k3/schema.yaml";
};
};
};

271
arch/arm/mach-k3/arm64-mmu.c
View file

@ -12,12 +12,7 @@
#include <asm/system.h>
#include <asm/armv8/mmu.h>
#ifdef CONFIG_SOC_K3_AM654
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
/* ToDo: Add 64bit IO */
struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
struct mm_region k3_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
@ -28,271 +23,12 @@ struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x20000000UL,
.size = 0x1e780000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xa0000000UL,
.phys = 0xa0000000UL,
.size = 0x02100000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xa2100000UL,
.phys = 0xa2100000UL,
.size = 0x5df00000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x880000000UL,
.phys = 0x880000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = am654_mem_map;
#endif /* CONFIG_SOC_K3_AM654 */
#ifdef CONFIG_SOC_K3_J721E
#ifdef CONFIG_SOC_K3_J721E_J7200
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
/* ToDo: Add 64bit IO */
struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xa0000000UL,
.phys = 0xa0000000UL,
.size = 0x04800000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_NON_SHARE
}, {
.virt = 0xa4800000UL,
.phys = 0xa4800000UL,
.size = 0x5b800000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x880000000UL,
.phys = 0x880000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = j7200_mem_map;
#else /* CONFIG_SOC_K3_J721E_J7200 */
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6)
/* ToDo: Add 64bit IO */
struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xa0000000UL,
.phys = 0xa0000000UL,
.size = 0x1bc00000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_NON_SHARE
}, {
.virt = 0xbbc00000UL,
.phys = 0xbbc00000UL,
.size = 0x44400000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x880000000UL,
.phys = 0x880000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x4d80000000UL,
.phys = 0x4d80000000UL,
.size = 0x0002000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_INNER_SHARE
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = j721e_mem_map;
#endif /* CONFIG_SOC_K3_J721E_J7200 */
#endif /* CONFIG_SOC_K3_J721E */
#ifdef CONFIG_SOC_K3_J721S2
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
/* ToDo: Add 64bit IO */
struct mm_region j721s2_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x880000000UL,
.phys = 0x880000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = j721s2_mem_map;
#endif /* CONFIG_SOC_K3_J721S2 */
#if defined(CONFIG_SOC_K3_AM625) || defined(CONFIG_SOC_K3_AM62A7)
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4)
/* ToDo: Add 64bit IO */
struct mm_region am62_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x1E780000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xA0000000UL,
.phys = 0xA0000000UL,
.size = 0x60000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x880000000UL,
.phys = 0x880000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = am62_mem_map;
#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
#ifdef CONFIG_SOC_K3_AM642
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4)
/* ToDo: Add 64bit IO */
struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x1E800000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xA0000000UL,
.phys = 0xA0000000UL,
.size = 0x60000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
@ -315,5 +51,4 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
}
};
struct mm_region *mem_map = am64_mem_map;
#endif /* CONFIG_SOC_K3_AM642 */
struct mm_region *mem_map = k3_mem_map;

0
board/ti/common/schema.yaml → arch/arm/mach-k3/schema.yaml
View file

522
board/ti/am62ax/rm-cfg.yaml
View file

File diff suppressed because it is too large Load diff

481
board/ti/am62x/rm-cfg.yaml
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File diff suppressed because it is too large Load diff

4
board/ti/am65x/evm.c
View file

@ -73,13 +73,13 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = 0x80000000;
gd->bd->bi_dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
gd->bd->bi_dram[1].start = 0x880000000;
gd->bd->bi_dram[1].size = 0x80000000;
gd->ram_size = 0x100000000;
#endif

4
board/ti/j721e/evm.c
View file

@ -61,13 +61,13 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = 0x80000000;
gd->bd->bi_dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
gd->bd->bi_dram[1].start = 0x880000000;
gd->bd->bi_dram[1].size = 0x80000000;
gd->ram_size = 0x100000000;
#endif

4
board/ti/j721s2/evm.c
View file

@ -56,13 +56,13 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = 0x80000000;
gd->bd->bi_dram[0].size = 0x7fffffff;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
gd->bd->bi_dram[1].start = 0x880000000;
gd->bd->bi_dram[1].size = 0x37fffffff;
gd->ram_size = 0x400000000;
#endif

4
include/configs/am62ax_evm.h
View file

@ -12,10 +12,6 @@
#include <env/ti/mmc.h>
#include <env/ti/k3_dfu.h>
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE1 0x880000000
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>

3
include/configs/am65x_evm.h
View file

@ -14,9 +14,6 @@
#include <env/ti/k3_rproc.h>
#include <env/ti/k3_dfu.h>
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE1 0x880000000
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>

2
include/configs/j721e_evm.h
View file

@ -11,8 +11,6 @@
#include <linux/sizes.h>
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE1 0x880000000
/* FLASH Configuration */
#define CFG_SYS_FLASH_BASE 0x000000000

3
include/configs/j721s2_evm.h
View file

@ -12,9 +12,6 @@
#include <linux/sizes.h>
#include <config_distro_bootcmd.h>
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE1 0x880000000
/* SPL Loader Configuration */
#if defined(CONFIG_TARGET_J721S2_A72_EVM)
#define CFG_SYS_UBOOT_BASE 0x50280000