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board: ti: k3: Remove need for CFG_SYS_SDRAM_BASE

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The base address of extended DDR does not change across the K3 family.
Setting this per SoC is not needed. Remove this definition to help
remove the last bits from K3 include/configs/*.h files.

Signed-off-by: Andrew Davis <afd@ti.com>
This commit is contained in:
Andrew Davis 2023-11-30 08:49:11 -06:00 committed by Tom Rini
parent 58a277c207
commit a213289953
7 changed files with 6 additions and 18 deletions
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4
board/ti/am65x/evm.c
View file

@ -73,13 +73,13 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = 0x80000000;
gd->bd->bi_dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
gd->bd->bi_dram[1].start = 0x880000000;
gd->bd->bi_dram[1].size = 0x80000000;
gd->ram_size = 0x100000000;
#endif

4
board/ti/j721e/evm.c
View file

@ -61,13 +61,13 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = 0x80000000;
gd->bd->bi_dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
gd->bd->bi_dram[1].start = 0x880000000;
gd->bd->bi_dram[1].size = 0x80000000;
gd->ram_size = 0x100000000;
#endif

4
board/ti/j721s2/evm.c
View file

@ -56,13 +56,13 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = 0x80000000;
gd->bd->bi_dram[0].size = 0x7fffffff;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
gd->bd->bi_dram[1].start = 0x880000000;
gd->bd->bi_dram[1].size = 0x37fffffff;
gd->ram_size = 0x400000000;
#endif

4
include/configs/am62ax_evm.h
View file

@ -12,10 +12,6 @@
#include <env/ti/mmc.h>
#include <env/ti/k3_dfu.h>
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE1 0x880000000
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>

3
include/configs/am65x_evm.h
View file

@ -14,9 +14,6 @@
#include <env/ti/k3_rproc.h>
#include <env/ti/k3_dfu.h>
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE1 0x880000000
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>

2
include/configs/j721e_evm.h
View file

@ -11,8 +11,6 @@
#include <linux/sizes.h>
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE1 0x880000000
/* FLASH Configuration */
#define CFG_SYS_FLASH_BASE 0x000000000

3
include/configs/j721s2_evm.h
View file

@ -12,9 +12,6 @@
#include <linux/sizes.h>
#include <config_distro_bootcmd.h>
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE1 0x880000000
/* SPL Loader Configuration */
#if defined(CONFIG_TARGET_J721S2_A72_EVM)
#define CFG_SYS_UBOOT_BASE 0x50280000