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Merge git://git.denx.de/u-boot-fsl-qoriq

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This commit is contained in:
Tom Rini 2017-06-03 18:05:04 -04:00
commit 541f538f4c
36 changed files with 516 additions and 104 deletions
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13
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View file

@ -135,6 +135,19 @@ config FSL_LS_PPA
which is loaded during boot stage, and then remains resident in RAM
and runs in the TrustZone after boot.
Say y to enable it.
config SPL_FSL_LS_PPA
bool "FSL Layerscape PPA firmware support for SPL build"
depends on !ARMV8_PSCI
select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
select SEC_FIRMWARE_ARMV8_PSCI
select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
help
The FSL Primary Protected Application (PPA) is a software component
which is loaded during boot stage, and then remains resident in RAM
and runs in the TrustZone after boot. This is to load PPA during SPL
stage instead of the RAM version of U-Boot. Once PPA is initialized,
the rest of U-Boot (including RAM version) runs at EL2.
choice
prompt "FSL Layerscape PPA firmware loading-media select"
depends on FSL_LS_PPA

15
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View file

@ -244,6 +244,14 @@ u64 get_page_table_size(void)
int arch_cpu_init(void)
{
/*
* This function is called before U-Boot relocates itself to speed up
* on system running. It is not necessary to run if performance is not
* critical. Skip if MMU is already enabled by SPL or other means.
*/
if (get_sctlr() & CR_M)
return 0;
icache_enable();
__asm_invalidate_dcache_all();
__asm_invalidate_tlb_all();
@ -464,7 +472,7 @@ int cpu_eth_init(bd_t *bis)
{
int error = 0;
#ifdef CONFIG_FSL_MC_ENET
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
error = fsl_mc_ldpaa_init(bis);
#endif
#ifdef CONFIG_FMAN_ENET
@ -530,6 +538,7 @@ int timer_init(void)
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
/* Update with accurate clock frequency */
if (current_el() == 3)
asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
#endif
@ -608,7 +617,7 @@ phys_size_t board_reserve_ram_top(phys_size_t ram_size)
{
phys_size_t ram_top = ram_size;
#ifdef CONFIG_FSL_MC_ENET
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
/* The start address of MC reserved memory needs to be aligned. */
ram_top -= mc_get_dram_block_size();
ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
@ -723,7 +732,7 @@ int dram_init_banksize(void)
}
#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
#ifdef CONFIG_FSL_MC_ENET
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
/* Assign memory for MC */
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
if (gd->bd->bi_dram[2].size >=

6
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
View file

@ -18,7 +18,7 @@ static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef CONFIG_FSL_MC_ENET
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
int xfi_dpmac[XFI8 + 1];
int sgmii_dpmac[SGMII16 + 1];
#endif
@ -110,7 +110,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
else {
serdes_prtcl_map[lane_prtcl] = 1;
#ifdef CONFIG_FSL_MC_ENET
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
switch (lane_prtcl) {
case QSGMII_A:
case QSGMII_B:
@ -141,7 +141,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
void fsl_serdes_init(void)
{
#ifdef CONFIG_FSL_MC_ENET
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
int i , j;
for (i = XFI1, j = 1; i <= XFI8; i++, j++)

16
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
View file

@ -73,6 +73,9 @@ ENDPROC(smp_kick_all_cpus)
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
1:
#ifdef CONFIG_FSL_LSCH3
/* Set Wuo bit for RN-I 20 */
@ -193,6 +196,7 @@ ENTRY(lowlevel_init)
#endif
#endif
100:
branch_if_master x0, x1, 2f
#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
@ -201,6 +205,8 @@ ENTRY(lowlevel_init)
#endif
2:
switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
1:
#ifdef CONFIG_FSL_TZPC_BP147
/* Set Non Secure access for all devices protected via TZPC */
ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
@ -266,8 +272,11 @@ ENTRY(lowlevel_init)
isb
dsb sy
#endif
100:
1:
#ifdef CONFIG_ARCH_LS1046A
switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
1:
/* Initialize the L2 RAM latency */
mrs x1, S3_1_c11_c0_2
mov x0, #0x1C7
@ -279,6 +288,7 @@ ENTRY(lowlevel_init)
orr x1, x1, #0x80
msr S3_1_c11_c0_2, x1
isb
100:
#endif
#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
@ -379,11 +389,14 @@ ENTRY(__asm_flush_l3_dcache)
/*
* Return status in x0
* success 0
* tmeout 1 for setting SFONLY, 2 for FAM, 3 for both
* timeout 1 for setting SFONLY, 2 for FAM, 3 for both
*/
mov x29, lr
mov x8, #0
switch_el x0, 1f, 100f, 100f /* skip if not in EL3 */
1:
dsb sy
mov x0, #0x1 /* HNFPSTAT_SFONLY */
bl hnf_set_pstate
@ -401,6 +414,7 @@ ENTRY(__asm_flush_l3_dcache)
bl hnf_pstate_poll
cbz x0, 1f
add x8, x8, #0x2
100:
1:
mov x0, x8
mov lr, x29

7
arch/arm/cpu/armv8/fsl-layerscape/ppa.c
View file

@ -32,6 +32,7 @@ DECLARE_GLOBAL_DATA_PTR;
int ppa_init(void)
{
unsigned int el = current_el();
void *ppa_fit_addr;
u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
int ret;
@ -45,6 +46,12 @@ int ppa_init(void)
#endif
#endif
/* Skip if running at lower exception level */
if (el < 3) {
debug("Skipping PPA init, running at EL%d\n", el);
return 0;
}
#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
debug("%s: PPA image load from XIP\n", __func__);

12
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View file

@ -134,7 +134,7 @@ void erratum_a009635(void)
static void erratum_rcw_src(void)
{
#if defined(CONFIG_SPL)
#if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
u32 val;
@ -288,6 +288,10 @@ static void erratum_a008850_early(void)
struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
/* Skip if running at lower exception level */
if (current_el() < 3)
return;
/* disables propagation of barrier transactions to DDRC from CCI400 */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
@ -304,6 +308,10 @@ void erratum_a008850_post(void)
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
u32 tmp;
/* Skip if running at lower exception level */
if (current_el() < 3)
return;
/* enable propagation of barrier transactions to DDRC from CCI400 */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
@ -455,8 +463,10 @@ void fsl_lsch2_early_init_f(void)
* Enable snoop requests and DVM message requests for
* Slave insterface S4 (A53 core cluster)
*/
if (current_el() == 3) {
out_le32(&cci->slave[4].snoop_ctrl,
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
}
/* Erratum */
erratum_a008850_early(); /* part 1 of 2 */

41
arch/arm/cpu/armv8/fsl-layerscape/spl.c
View file

@ -9,6 +9,9 @@
#include <asm/io.h>
#include <fsl_ifc.h>
#include <i2c.h>
#include <fsl_csu.h>
#include <asm/arch/fdt.h>
#include <asm/arch/ppa.h>
DECLARE_GLOBAL_DATA_PTR;
@ -57,6 +60,12 @@ void spl_board_init(void)
val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
out_le32(SMMU_NSCR0, val);
#endif
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
#ifdef CONFIG_SPL_FSL_LS_PPA
ppa_init();
#endif
}
void board_init_f(ulong dummy)
@ -76,5 +85,35 @@ void board_init_f(ulong dummy)
i2c_init_all();
#endif
dram_init();
}
#ifdef CONFIG_SPL_FSL_LS_PPA
#ifndef CONFIG_SYS_MEM_RESERVE_SECURE
#error Need secure RAM for PPA
#endif
/*
* Secure memory location is determined in dram_init_banksize().
* gd->ram_size is deducted by the size of secure ram.
*/
dram_init_banksize();
/*
* After dram_init_bank_size(), we know U-Boot only uses the first
* memory bank regardless how big the memory is.
*/
gd->ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
/*
* If PPA is loaded, U-Boot will resume running at EL2.
* Cache and MMU will be enabled. Need a place for TLB.
* U-Boot will be relocated to the end of available memory
* in first bank. At this point, we cannot know how much
* memory U-Boot uses. Put TLB table lower by SPL_TLB_SETBACK
* to avoid overlapping. As soon as the RAM version U-Boot sets
* up new MMU, this space is no longer needed.
*/
gd->ram_top -= SPL_TLB_SETBACK;
gd->arch.tlb_size = PGTABLE_SIZE;
gd->arch.tlb_addr = (gd->ram_top - gd->arch.tlb_size) & ~(0x10000 - 1);
gd->arch.tlb_allocated = gd->arch.tlb_addr;
#endif /* CONFIG_SPL_FSL_LS_PPA */
}
#endif /* CONFIG_SPL_BUILD */

2
arch/arm/cpu/armv8/sec_firmware.c
View file

@ -224,7 +224,7 @@ __weak bool sec_firmware_is_valid(const void *sec_firmware_img)
*/
unsigned int sec_firmware_support_psci_version(void)
{
if (sec_firmware_addr & SEC_FIRMWARE_RUNNING)
if (current_el() == SEC_FIRMWARE_TARGET_EL)
return _sec_firmware_support_psci_version();
return PSCI_INVALID_VER;

3
arch/arm/cpu/armv8/start.S
View file

@ -91,9 +91,12 @@ save_boot_params_ret:
* this bit should be set for A53/A57/A72.
*/
#ifdef CONFIG_ARMV8_SET_SMPEN
switch_el x1, 3f, 1f, 1f
3:
mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */
orr x0, x0, #0x40
msr S3_1_c15_c2_1, x0
1:
#endif
/* Apply ARM core specific erratas */

1
arch/arm/include/asm/arch-fsl-layerscape/config.h
View file

@ -17,6 +17,7 @@
* To be aligned with MMU block size
*/
#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
#ifdef CONFIG_ARCH_LS2080A
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }

3
board/freescale/common/ns_access.c
View file

@ -39,6 +39,9 @@ static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
void enable_layerscape_ns_access(void)
{
#ifdef CONFIG_ARM64
if (current_el() == 3)
#endif
enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
}

12
board/freescale/ls2080a/ls2080a.c
View file

@ -64,13 +64,13 @@ int board_eth_init(bd_t *bis)
error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
#ifdef CONFIG_FSL_MC_ENET
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
error = cpu_eth_init(bis);
#endif
return error;
}
#ifdef CONFIG_FSL_MC_ENET
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
void fdt_fixup_board_enet(void *fdt)
{
int offset;
@ -128,10 +128,16 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory_banks(blob, base, size, 2);
#ifdef CONFIG_FSL_MC_ENET
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
fdt_fixup_board_enet(blob);
#endif
return 0;
}
#endif
#if defined(CONFIG_RESET_PHY_R)
void reset_phy(void)
{
}
#endif

1
board/freescale/ls2080aqds/MAINTAINERS
View file

@ -7,6 +7,7 @@ F: include/configs/ls2080aqds.h
F: configs/ls2080aqds_defconfig
F: configs/ls2080aqds_nand_defconfig
F: configs/ls2080aqds_qspi_defconfig
F: configs/ls2080aqds_sdcard_defconfig
LS2080A_SECURE_BOOT BOARD
M: Saksham Jain <saksham.jain@nxp.freescale.com>

13
board/freescale/ls2080aqds/README
View file

@ -102,6 +102,19 @@ DPAA2 DPL 0x00D00000
DPAA2 DPC 0x00E00000
Kernel.itb 0x01000000
Memory map for SD boot
-------------------------
Image Flash Offset SD Card
Start Block No.
RCW+PBI 0x00000000 0x00008
Boot firmware (U-Boot) 0x00100000 0x00800
Boot firmware Environment 0x00300000 0x01800
PPA firmware 0x00400000 0x02000
DPAA2 MC 0x00A00000 0x05000
DPAA2 DPL 0x00D00000 0x06800
DPAA2 DPC 0x00E00000 0x07000
Kernel.itb 0x01000000 0x08000
Environment Variables
---------------------
- mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined

18
board/freescale/ls2080aqds/eth.c
View file

@ -14,6 +14,7 @@
#include <fm_eth.h>
#include <i2c.h>
#include <miiphy.h>
#include <fsl-mc/fsl_mc.h>
#include <fsl-mc/ldpaa_wriop.h>
#include "../common/qixis.h"
@ -22,7 +23,7 @@
#define MC_BOOT_ENV_VAR "mcinitcmd"
#ifdef CONFIG_FSL_MC_ENET
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
/* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
* Bank 1 -> Lanes A, B, C, D, E, F, G, H
* Bank 2 -> Lanes A,B, C, D, E, F, G, H
@ -834,8 +835,7 @@ void ls2080a_handle_phy_interface_xsgmii(int i)
int board_eth_init(bd_t *bis)
{
int error;
char *mc_boot_env_var;
#ifdef CONFIG_FSL_MC_ENET
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
@ -902,9 +902,6 @@ int board_eth_init(bd_t *bis)
}
}
mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
if (mc_boot_env_var)
run_command_list(mc_boot_env_var, -1, 0);
error = cpu_eth_init(bis);
if (hwconfig_f("xqsgmii", env_hwconfig)) {
@ -919,6 +916,9 @@ int board_eth_init(bd_t *bis)
return error;
}
#ifdef CONFIG_FSL_MC_ENET
#endif
#if defined(CONFIG_RESET_PHY_R)
void reset_phy(void)
{
mc_env_boot();
}
#endif /* CONFIG_RESET_PHY_R */

4
board/freescale/ls2080aqds/ls2080aqds.c
View file

@ -280,7 +280,7 @@ int arch_misc_init(void)
}
#endif
#ifdef CONFIG_FSL_MC_ENET
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
void fdt_fixup_board_enet(void *fdt)
{
int offset;
@ -336,7 +336,7 @@ int ft_board_setup(void *blob, bd_t *bd)
fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_FSL_MC_ENET
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
fdt_fixup_board_enet(blob);
#endif

15
board/freescale/ls2080ardb/eth_ls2080rdb.c
View file

@ -16,15 +16,14 @@
#include <asm/io.h>
#include <exports.h>
#include <asm/arch/fsl_serdes.h>
#include <fsl-mc/fsl_mc.h>
#include <fsl-mc/ldpaa_wriop.h>
DECLARE_GLOBAL_DATA_PTR;
#define MC_BOOT_ENV_VAR "mcinitcmd"
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
char *mc_boot_env_var;
int i, interface;
struct memac_mdio_info mdio_info;
struct mii_dev *dev;
@ -98,11 +97,8 @@ int board_eth_init(bd_t *bis)
}
}
mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
if (mc_boot_env_var)
run_command_list(mc_boot_env_var, -1, 0);
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
#endif /* CONFIG_FSL_MC_ENET */
#ifdef CONFIG_PHY_AQUANTIA
/*
@ -118,3 +114,10 @@ int board_eth_init(bd_t *bis)
#endif
return pci_eth_init(bis);
}
#if defined(CONFIG_RESET_PHY_R)
void reset_phy(void)
{
mc_env_boot();
}
#endif /* CONFIG_RESET_PHY_R */

1
configs/ls1043ardb_sdcard_defconfig
View file

@ -3,6 +3,7 @@ CONFIG_TARGET_LS1043ARDB=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y

1
configs/ls1046aqds_nand_defconfig
View file

@ -8,6 +8,7 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_HUSH_PARSER=y

1
configs/ls1046aqds_sdcard_ifc_defconfig
View file

@ -8,6 +8,7 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_HUSH_PARSER=y

1
configs/ls1046aqds_sdcard_qspi_defconfig
View file

@ -8,6 +8,7 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT_QSPI"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_HUSH_PARSER=y

1
configs/ls1046ardb_emmc_defconfig
View file

@ -8,6 +8,7 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,EMMC_BOOT"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_HUSH_PARSER=y

1
configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_CRYPTO_SUPPORT=y

2
configs/ls1046ardb_sdcard_defconfig
View file

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_FSL_LS_PPA=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -8,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_HUSH_PARSER=y

1
configs/ls2080aqds_nand_defconfig
View file

@ -10,6 +10,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_NAND_BOOT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y

56
configs/ls2080aqds_sdcard_defconfig Normal file
View file

@ -0,0 +1,56 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2080AQDS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_FSL_LS_PPA=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

1
configs/ls2080ardb_nand_defconfig
View file

@ -10,6 +10,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_NAND_BOOT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y

274
drivers/net/fsl-mc/mc.c
View file

@ -27,6 +27,7 @@
#define MC_MEM_SIZE_ENV_VAR "mcmemsize"
#define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout"
#define MC_BOOT_ENV_VAR "mcinitcmd"
DECLARE_GLOBAL_DATA_PTR;
static int mc_boot_status = -1;
@ -155,19 +156,142 @@ int parse_mc_firmware_fit_image(u64 mc_fw_addr,
}
#endif
static int mc_fixup_dpc_mac_addr(void *blob, int noff, int dpmac_id,
#define MC_DT_INCREASE_SIZE 64
enum mc_fixup_type {
MC_FIXUP_DPL,
MC_FIXUP_DPC
};
static int mc_fixup_mac_addr(void *blob, int nodeoffset,
const char *propname, struct eth_device *eth_dev,
enum mc_fixup_type type)
{
int err = 0, len = 0, size, i;
unsigned char env_enetaddr[ARP_HLEN];
unsigned int enetaddr_32[ARP_HLEN];
void *val = NULL;
switch (type) {
case MC_FIXUP_DPL:
/* DPL likes its addresses on 32 * ARP_HLEN bits */
for (i = 0; i < ARP_HLEN; i++)
enetaddr_32[i] = cpu_to_fdt32(eth_dev->enetaddr[i]);
val = enetaddr_32;
len = sizeof(enetaddr_32);
break;
case MC_FIXUP_DPC:
val = eth_dev->enetaddr;
len = ARP_HLEN;
break;
}
/* MAC address property present */
if (fdt_get_property(blob, nodeoffset, propname, NULL)) {
/* u-boot MAC addr randomly assigned - leave the present one */
if (!eth_getenv_enetaddr_by_index("eth", eth_dev->index,
env_enetaddr))
return err;
} else {
size = MC_DT_INCREASE_SIZE + strlen(propname) + len;
/* make room for mac address property */
err = fdt_increase_size(blob, size);
if (err) {
printf("fdt_increase_size: err=%s\n",
fdt_strerror(err));
return err;
}
}
err = fdt_setprop(blob, nodeoffset, propname, val, len);
if (err) {
printf("fdt_setprop: err=%s\n", fdt_strerror(err));
return err;
}
return err;
}
#define is_dpni(s) (s != NULL ? !strncmp(s, "dpni@", 5) : 0)
const char *dpl_get_connection_endpoint(void *blob, char *endpoint)
{
int connoffset = fdt_path_offset(blob, "/connections"), off;
const char *s1, *s2;
for (off = fdt_first_subnode(blob, connoffset);
off >= 0;
off = fdt_next_subnode(blob, off)) {
s1 = fdt_stringlist_get(blob, off, "endpoint1", 0, NULL);
s2 = fdt_stringlist_get(blob, off, "endpoint2", 0, NULL);
if (!s1 || !s2)
continue;
if (strcmp(endpoint, s1) == 0)
return s2;
if (strcmp(endpoint, s2) == 0)
return s1;
}
return NULL;
}
static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id,
struct eth_device *eth_dev)
{
int nodeoffset, err = 0;
int objoff = fdt_path_offset(blob, "/objects");
int dpmacoff = -1, dpnioff = -1;
const char *endpoint;
char mac_name[10];
const char link_type_mode[] = "FIXED_LINK";
unsigned char env_enetaddr[6];
int err;
sprintf(mac_name, "dpmac@%d", dpmac_id);
dpmacoff = fdt_subnode_offset(blob, objoff, mac_name);
if (dpmacoff < 0)
/* dpmac not defined in DPL, so skip it. */
return 0;
err = mc_fixup_mac_addr(blob, dpmacoff, "mac_addr", eth_dev,
MC_FIXUP_DPL);
if (err) {
printf("Error fixing up dpmac mac_addr in DPL\n");
return err;
}
/* now we need to figure out if there is any
* DPNI connected to this MAC, so we walk the
* connection list
*/
endpoint = dpl_get_connection_endpoint(blob, mac_name);
if (!is_dpni(endpoint))
return 0;
/* let's see if we can fixup the DPNI as well */
dpnioff = fdt_subnode_offset(blob, objoff, endpoint);
if (dpnioff < 0)
/* DPNI not defined in DPL in the objects area */
return 0;
return mc_fixup_mac_addr(blob, dpnioff, "mac_addr", eth_dev,
MC_FIXUP_DPL);
}
static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
struct eth_device *eth_dev)
{
int nodeoffset = fdt_path_offset(blob, "/board_info/ports"), noff;
int err = 0;
char mac_name[10];
const char link_type_mode[] = "MAC_LINK_TYPE_FIXED";
sprintf(mac_name, "mac@%d", dpmac_id);
/* node not found - create it */
nodeoffset = fdt_subnode_offset(blob, noff, (const char *) mac_name);
if (nodeoffset < 0) {
noff = fdt_subnode_offset(blob, nodeoffset, (const char *)mac_name);
if (noff < 0) {
err = fdt_increase_size(blob, 200);
if (err) {
printf("fdt_increase_size: err=%s\n",
@ -175,10 +299,15 @@ static int mc_fixup_dpc_mac_addr(void *blob, int noff, int dpmac_id,
return err;
}
nodeoffset = fdt_add_subnode(blob, noff, mac_name);
noff = fdt_add_subnode(blob, nodeoffset, mac_name);
if (noff < 0) {
printf("fdt_add_subnode: err=%s\n",
fdt_strerror(err));
return err;
}
/* add default property of fixed link */
err = fdt_appendprop_string(blob, nodeoffset,
err = fdt_appendprop_string(blob, noff,
"link_type", link_type_mode);
if (err) {
printf("fdt_appendprop_string: err=%s\n",
@ -187,49 +316,53 @@ static int mc_fixup_dpc_mac_addr(void *blob, int noff, int dpmac_id,
}
}
/* port_mac_address property present in DPC */
if (fdt_get_property(blob, nodeoffset, "port_mac_address", NULL)) {
/* MAC addr randomly assigned - leave the one in DPC */
eth_getenv_enetaddr_by_index("eth", eth_dev->index,
env_enetaddr);
if (is_zero_ethaddr(env_enetaddr))
return err;
return mc_fixup_mac_addr(blob, noff, "port_mac_address", eth_dev,
MC_FIXUP_DPC);
}
/* replace DPC MAC address with u-boot env one */
err = fdt_setprop(blob, nodeoffset, "port_mac_address",
eth_dev->enetaddr, 6);
if (err) {
printf("fdt_setprop mac: err=%s\n", fdt_strerror(err));
return err;
static int mc_fixup_mac_addrs(void *blob, enum mc_fixup_type type)
{
int i, err = 0, ret = 0;
char ethname[10];
struct eth_device *eth_dev;
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
/* port not enabled */
if ((wriop_is_enabled_dpmac(i) != 1) ||
(wriop_get_phy_address(i) == -1))
continue;
sprintf(ethname, "DPMAC%d@%s", i,
phy_interface_strings[wriop_get_enet_if(i)]);
eth_dev = eth_get_dev_by_name(ethname);
if (eth_dev == NULL)
continue;
switch (type) {
case MC_FIXUP_DPL:
err = mc_fixup_dpl_mac_addr(blob, i, eth_dev);
break;
case MC_FIXUP_DPC:
err = mc_fixup_dpc_mac_addr(blob, i, eth_dev);
break;
default:
break;
}
return 0;
if (err)
printf("fsl-mc: ERROR fixing mac address for %s\n",
ethname);
ret |= err;
}
/* append port_mac_address property to mac node in DPC */
err = fdt_increase_size(blob, 80);
if (err) {
printf("fdt_increase_size: err=%s\n", fdt_strerror(err));
return err;
}
err = fdt_appendprop(blob, nodeoffset,
"port_mac_address", eth_dev->enetaddr, 6);
if (err) {
printf("fdt_appendprop: err=%s\n", fdt_strerror(err));
return err;
}
return err;
return ret;
}
static int mc_fixup_dpc(u64 dpc_addr)
{
void *blob = (void *)dpc_addr;
int nodeoffset, err = 0;
char ethname[10];
struct eth_device *eth_dev;
int i;
/* delete any existing ICID pools */
nodeoffset = fdt_path_offset(blob, "/resources/icid_pools");
@ -254,30 +387,9 @@ static int mc_fixup_dpc(u64 dpc_addr)
/* fixup MAC addresses for dpmac ports */
nodeoffset = fdt_path_offset(blob, "/board_info/ports");
if (nodeoffset < 0)
goto out;
return 0;
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
/* port not enabled */
if ((wriop_is_enabled_dpmac(i) != 1) ||
(wriop_get_phy_address(i) == -1))
continue;
sprintf(ethname, "DPMAC%d@%s", i,
phy_interface_strings[wriop_get_enet_if(i)]);
eth_dev = eth_get_dev_by_name(ethname);
if (eth_dev == NULL)
continue;
err = mc_fixup_dpc_mac_addr(blob, nodeoffset, i, eth_dev);
if (err) {
printf("mc_fixup_dpc_mac_addr failed: err=%s\n",
fdt_strerror(err));
goto out;
}
}
out:
err = mc_fixup_mac_addrs(blob, MC_FIXUP_DPC);
flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob));
return err;
@ -340,6 +452,25 @@ static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr)
return 0;
}
static int mc_fixup_dpl(u64 dpl_addr)
{
void *blob = (void *)dpl_addr;
u32 ver = fdt_getprop_u32_default(blob, "/", "dpl-version", 0);
int err = 0;
/* The DPL fixup for mac addresses is only relevant
* for old-style DPLs
*/
if (ver >= 10)
return 0;
err = mc_fixup_mac_addrs(blob, MC_FIXUP_DPL);
flush_dcache_range(dpl_addr, dpl_addr + fdt_totalsize(blob));
return err;
}
static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr)
{
u64 mc_dpl_offset;
@ -386,6 +517,8 @@ static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr)
(u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset);
#endif /* not defined CONFIG_SYS_LS_MC_DPL_IN_DDR */
if (mc_fixup_dpl(mc_ram_addr + mc_dpl_offset))
return -EINVAL;
dump_ram_words("DPL", (void *)(mc_ram_addr + mc_dpl_offset));
return 0;
}
@ -1368,3 +1501,18 @@ U_BOOT_CMD(
"fsl_mc lazyapply DPL [DPL_addr] - Apply DPL file on exit\n"
"fsl_mc start aiop [FW_addr] - Start AIOP\n"
);
void mc_env_boot(void)
{
#if defined(CONFIG_FSL_MC_ENET)
char *mc_boot_env_var;
/* The MC may only be initialized in the reset PHY function
* because otherwise U-Boot has not yet set up all the MAC
* address info properly. Without MAC addresses, the MC code
* can not properly initialize the DPC.
*/
mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
if (mc_boot_env_var)
run_command_list(mc_boot_env_var, -1, 0);
#endif /* CONFIG_FSL_MC_ENET */
}

36
drivers/qe/qe.c
View file

@ -8,6 +8,7 @@
*/
#include <common.h>
#include <malloc.h>
#include <command.h>
#include <linux/errno.h>
#include <asm/io.h>
@ -17,6 +18,10 @@
#include <asm/arch/immap_ls102xa.h>
#endif
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
#include <mmc.h>
#endif
#define MPC85xx_DEVDISR_QE_DISABLE 0x1
qe_map_t *qe_immr = NULL;
@ -194,8 +199,37 @@ void u_qe_init(void)
{
qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
u_qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
int dev = CONFIG_SYS_MMC_ENV_DEV;
u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
u32 blk = CONFIG_SYS_QE_FW_ADDR / 512;
if (mmc_initialize(gd->bd)) {
printf("%s: mmc_initialize() failed\n", __func__);
return;
}
addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
if (!mmc) {
free(addr);
printf("\nMMC cannot find device for ucode\n");
} else {
printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
(void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
addr);
/* flush cache after read */
flush_cache((ulong)addr, cnt * 512);
}
#endif
u_qe_upload_firmware(addr);
out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
free(addr);
#endif
}
#endif

1
include/configs/ls1021aqds.h
View file

@ -125,6 +125,7 @@ unsigned long get_board_ddr_clk(void);
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
!defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#endif
/*

1
include/configs/ls1021atwr.h
View file

@ -149,6 +149,7 @@
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
!defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#endif
/*

2
include/configs/ls1043a_common.h
View file

@ -216,6 +216,7 @@
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08)
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
@ -227,6 +228,7 @@
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
/* FMan fireware Pre-load address */
#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
#define CONFIG_SYS_QE_FW_ADDR 0x60940000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)

4
include/configs/ls1043ardb.h
View file

@ -280,11 +280,9 @@
/* QE */
#ifndef SPL_NO_QE
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
!defined(CONFIG_QSPI_BOOT)
#if !defined(CONFIG_NAND_BOOT) && !defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
#endif
#define CONFIG_SYS_QE_FW_ADDR 0x60940000
#endif
/* USB */

14
include/configs/ls2080a_common.h
View file

@ -156,6 +156,11 @@ unsigned long long get_qixis_addr(void);
#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
/* Define phy_reset function to boot the MC based on mcinitcmd.
* This happens late enough to properly fixup u-boot env MAC addresses.
*/
#define CONFIG_RESET_PHY_R
/*
* Carve out a DDR region which will not be used by u-boot/Linux
*
@ -203,9 +208,16 @@ unsigned long long get_qixis_addr(void);
"earlycon=uart8250,mmio,0x21c0500 " \
"ramdisk_size=0x2000000 default_hugepagesz=2m" \
" hugepagesz=2m hugepages=256"
#ifdef CONFIG_SD_BOOT
#define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\
" fsl_mc apply dpl 0x80200000 &&" \
" mmc read $kernel_load $kernel_start" \
" $kernel_size && bootm $kernel_load"
#else
#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
" cp.b $kernel_start $kernel_load" \
" $kernel_size && bootm $kernel_load"
#endif
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
@ -228,8 +240,10 @@ unsigned long long get_qixis_addr(void);
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x1800a000
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#endif
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
#define CONFIG_SYS_MONITOR_LEN (640 * 1024)

29
include/configs/ls2080aqds.h
View file

@ -166,12 +166,14 @@ unsigned long get_board_ddr_clk(void);
#define QIXIS_LBMAP_DFLTBANK 0x00
#define QIXIS_LBMAP_ALTBANK 0x04
#define QIXIS_LBMAP_NAND 0x09
#define QIXIS_LBMAP_SD 0x00
#define QIXIS_LBMAP_QSPI 0x0f
#define QIXIS_RST_CTL_RESET 0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_RCW_SRC_NAND 0x107
#define QIXIS_RCW_SRC_SD 0x40
#define QIXIS_RCW_SRC_QSPI 0x62
#define QIXIS_RST_FORCE_MEM 0x01
@ -198,7 +200,8 @@ unsigned long get_board_ddr_clk(void);
FTIM2_GPCM_TWP(0x3E))
#define CONFIG_SYS_CS3_FTIM3 0x0
#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
#if defined(CONFIG_SPL)
#if defined(CONFIG_NAND_BOOT)
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
@ -234,6 +237,12 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET 0x200000
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x20000
#endif
#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
@ -366,6 +375,22 @@ unsigned long get_board_ddr_clk(void);
"esbc_validate 0x580740000;" \
"fsl_mc start mc 0x580a00000" \
" 0x580e00000 \0"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x90100000\0" \
"kernel_addr=0x800\0" \
"ramdisk_addr=0x800000\0" \
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
"kernel_start=0x8000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x14000\0" \
"mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
"mmc read 0x80100000 0x7000 0x800;" \
"fsl_mc start mc 0x80000000 0x80100000\0" \
"mcmemsize=0x70000000 \0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
@ -384,7 +409,7 @@ unsigned long get_board_ddr_clk(void);
#endif /* CONFIG_SECURE_BOOT */
#ifdef CONFIG_FSL_MC_ENET
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
#define CONFIG_FSL_MEMAC
#define CONFIG_PHYLIB
#define CONFIG_PHYLIB_10G

1
include/fsl-mc/fsl_mc.h
View file

@ -61,4 +61,5 @@ u64 mc_get_dram_addr(void);
unsigned long mc_get_dram_block_size(void);
int fsl_mc_ldpaa_init(bd_t *bis);
int fsl_mc_ldpaa_exit(bd_t *bd);
void mc_env_boot(void);
#endif