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Merge git://git.denx.de/u-boot-sunxi

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This commit is contained in:
Tom Rini 2017-06-03 18:04:54 -04:00
commit b07d044d5b
19 changed files with 1031 additions and 606 deletions
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5
arch/arm/dts/Makefile
View file

@ -309,6 +309,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-orangepi-pc-plus.dtb \
sun8i-h3-orangepi-plus.dtb \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-h3-nanopi-m1.dtb \
sun8i-h3-nanopi-neo.dtb \
sun8i-h3-nanopi-neo-air.dtb
dtb-$(CONFIG_MACH_SUN8I_R40) += \
@ -316,8 +317,10 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
dtb-$(CONFIG_MACH_SUN8I_V3S) += \
sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-orangepi-pc2.dtb
sun50i-h5-orangepi-pc2.dtb \
sun50i-h5-orangepi-prime.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-bananapi-m64.dtb \
sun50i-a64-pine64-plus.dtb \
sun50i-a64-pine64.dtb
dtb-$(CONFIG_MACH_SUN9I) += \

121
arch/arm/dts/sun50i-a64-bananapi-m64.dts Normal file
View file

@ -0,0 +1,121 @@
/*
* Copyright (c) 2016 ARM Ltd.
* Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun50i-a64.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "BananaPi-M64";
compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64";
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
&i2c1_pins {
bias-pull-up;
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_vcc3v3>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
disable-wp;
bus-width = <4>;
status = "okay";
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
non-removable;
status = "okay";
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
status = "okay";
};

50
arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi Normal file
View file

@ -0,0 +1,50 @@
/ {
aliases {
ethernet0 = &emac;
};
soc {
emac: ethernet@01c30000 {
compatible = "allwinner,sun50i-a64-emac";
reg = <0x01c30000 0x2000>, <0x01c00030 0x4>;
reg-names = "emac", "syscon";
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ccu RST_BUS_EMAC>;
reset-names = "ahb";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "ahb";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
phy = <&phy1>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
};
};
&pio {
rmii_pins: rmii_pins {
allwinner,pins = "PD10", "PD11", "PD13", "PD14",
"PD17", "PD18", "PD19", "PD20",
"PD22", "PD23";
allwinner,function = "emac";
allwinner,drive = <3>;
allwinner,pull = <0>;
};
rgmii_pins: rgmii_pins {
allwinner,pins = "PD8", "PD9", "PD10", "PD11",
"PD12", "PD13", "PD15",
"PD16", "PD17", "PD18", "PD19",
"PD20", "PD21", "PD22", "PD23";
allwinner,function = "emac";
allwinner,drive = <3>;
allwinner,pull = <0>;
};
};

26
arch/arm/dts/sun50i-a64-pine64-plus.dts
View file

@ -40,33 +40,11 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun50i-a64-pine64-common.dtsi"
#include "sun50i-a64-pine64.dts"
/ {
model = "Pine64+";
compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
chosen {
stdout-path = "serial0:115200n8";
};
/* There is a model with 2GB of DRAM, but U-Boot fixes this for us. */
memory {
reg = <0x40000000 0x40000000>;
};
/* TODO: Camera, Ethernet PHY, touchscreen, etc. */
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
phy = <&phy1>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};

59
arch/arm/dts/sun50i-a64-pine64.dts
View file

@ -42,17 +42,70 @@
/dts-v1/;
#include "sun50i-a64-pine64-common.dtsi"
#include "sun50i-a64.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Pine64";
compatible = "pine64,pine64", "allwinner,sun50i-a64";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
reg = <0x40000000 0x20000000>;
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&ehci1 {
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
&i2c1_pins {
bias-pull-up;
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_vcc3v3>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
disable-wp;
bus-width = <4>;
status = "okay";
};
&ohci1 {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&usb_otg {
dr_mode = "host";
status = "okay";
};
&usbphy {
status = "okay";
};

645
arch/arm/dts/sun50i-a64.dtsi
View file

@ -42,8 +42,9 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/clock/sun50i-a64-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>
/ {
interrupt-parent = <&gic>;
@ -54,28 +55,28 @@
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
};
cpu@1 {
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <1>;
enable-method = "psci";
};
cpu@2 {
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <2>;
enable-method = "psci";
};
cpu@3 {
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <3>;
@ -83,30 +84,33 @@
};
};
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "osc24M";
};
osc32k: osc32k_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "osc32k";
};
iosc: internal-osc-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <16000000>;
clock-accuracy = <300000000>;
clock-output-names = "iosc";
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
memory {
device_type = "memory";
reg = <0x40000000 0>;
};
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <0>;
reg = <0x01c81000 0x1000>,
<0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
@ -119,199 +123,6 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "osc24M";
};
osc32k: osc32k_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "osc32k";
};
pll1: pll1_clk@1c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll1";
};
pll6: pll6_clk@1c20028 {
#clock-cells = <1>;
compatible = "allwinner,sun6i-a31-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll6", "pll6x2";
};
pll6d2: pll6d2_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <2>;
clock-mult = <1>;
clocks = <&pll6 0>;
clock-output-names = "pll6d2";
};
pll7: pll7_clk@1c2002c {
#clock-cells = <1>;
compatible = "allwinner,sun6i-a31-pll6-clk";
reg = <0x01c2002c 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll7", "pll7x2";
};
cpu: cpu_clk@1c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-cpu-clk";
reg = <0x01c20050 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
clock-output-names = "cpu";
critical-clocks = <0>;
};
axi: axi_clk@1c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-axi-clk";
reg = <0x01c20050 0x4>;
clocks = <&cpu>;
clock-output-names = "axi";
};
ahb1: ahb1_clk@1c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun6i-a31-ahb1-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
clock-output-names = "ahb1";
};
ahb2: ahb2_clk@1c2005c {
#clock-cells = <0>;
compatible = "allwinner,sun8i-h3-ahb2-clk";
reg = <0x01c2005c 0x4>;
clocks = <&ahb1>, <&pll6d2>;
clock-output-names = "ahb2";
};
apb1: apb1_clk@1c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb0-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb1>;
clock-output-names = "apb1";
};
apb2: apb2_clk@1c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
clock-output-names = "apb2";
};
bus_gates: bus_gates_clk@1c20060 {
#clock-cells = <1>;
compatible = "allwinner,sun50i-a64-bus-gates-clk",
"allwinner,sunxi-multi-bus-gates-clk";
reg = <0x01c20060 0x14>;
ahb1_parent {
clocks = <&ahb1>;
clock-indices = <1>, <5>,
<6>, <8>,
<9>, <10>,
<13>, <14>,
<18>, <19>,
<20>, <21>,
<23>, <24>,
<25>, <28>,
<32>, <35>,
<36>, <37>,
<40>, <43>,
<44>, <52>,
<53>, <54>,
<135>;
clock-output-names = "bus_mipidsi", "bus_ce",
"bus_dma", "bus_mmc0",
"bus_mmc1", "bus_mmc2",
"bus_nand", "bus_sdram",
"bus_ts", "bus_hstimer",
"bus_spi0", "bus_spi1",
"bus_otg", "bus_otg_ehci0",
"bus_ehci0", "bus_otg_ohci0",
"bus_ve", "bus_lcd0",
"bus_lcd1", "bus_deint",
"bus_csi", "bus_hdmi",
"bus_de", "bus_gpu",
"bus_msgbox", "bus_spinlock",
"bus_dbg";
};
ahb2_parent {
clocks = <&ahb2>;
clock-indices = <17>, <29>;
clock-output-names = "bus_gmac", "bus_ohci0";
};
apb1_parent {
clocks = <&apb1>;
clock-indices = <64>, <65>,
<69>, <72>,
<76>, <77>,
<78>;
clock-output-names = "bus_codec", "bus_spdif",
"bus_pio", "bus_ths",
"bus_i2s0", "bus_i2s1",
"bus_i2s2";
};
abp2_parent {
clocks = <&apb2>;
clock-indices = <96>, <97>,
<98>, <101>,
<112>, <113>,
<114>, <115>,
<116>;
clock-output-names = "bus_i2c0", "bus_i2c1",
"bus_i2c2", "bus_scr",
"bus_uart0", "bus_uart1",
"bus_uart2", "bus_uart3",
"bus_uart4";
};
};
mmc0_clk: mmc0_clk@1c20088 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
clock-output-names = "mmc0";
};
mmc1_clk: mmc1_clk@1c2008c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c2008c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
clock-output-names = "mmc1";
};
mmc2_clk: mmc2_clk@1c20090 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20090 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
clock-output-names = "mmc2";
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
@ -319,230 +130,171 @@
ranges;
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun50i-a64-mmc",
"allwinner,sun5i-a13-mmc";
compatible = "allwinner,sun50i-a64-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&bus_gates 8>, <&mmc0_clk>,
<&mmc0_clk>, <&mmc0_clk>;
clock-names = "ahb", "mmc",
"output", "sample";
resets = <&ahb_rst 8>;
clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
max-frequency = <150000000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc1: mmc@1c10000 {
compatible = "allwinner,sun50i-a64-mmc",
"allwinner,sun5i-a13-mmc";
compatible = "allwinner,sun50i-a64-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&bus_gates 9>, <&mmc1_clk>,
<&mmc1_clk>, <&mmc1_clk>;
clock-names = "ahb", "mmc",
"output", "sample";
resets = <&ahb_rst 9>;
clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
max-frequency = <150000000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc2: mmc@1c11000 {
compatible = "allwinner,sun50i-a64-mmc",
"allwinner,sun5i-a13-mmc";
compatible = "allwinner,sun50i-a64-emmc";
reg = <0x01c11000 0x1000>;
clocks = <&bus_gates 10>, <&mmc2_clk>,
<&mmc2_clk>, <&mmc2_clk>;
clock-names = "ahb", "mmc",
"output", "sample";
resets = <&ahb_rst 10>;
clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC2>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
max-frequency = <200000000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
usb_otg: usb@01c19000 {
compatible = "allwinner,sun8i-a33-musb";
reg = <0x01c19000 0x0400>;
clocks = <&ccu CLK_BUS_OTG>;
resets = <&ccu RST_BUS_OTG>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
status = "disabled";
};
usbphy: phy@01c19400 {
compatible = "allwinner,sun50i-a64-usb-phy";
reg = <0x01c19400 0x14>,
<0x01c1a800 0x4>,
<0x01c1b800 0x4>;
reg-names = "phy_ctrl",
"pmu0",
"pmu1";
clocks = <&ccu CLK_USB_PHY0>,
<&ccu CLK_USB_PHY1>;
clock-names = "usb0_phy",
"usb1_phy";
resets = <&ccu RST_USB_PHY0>,
<&ccu RST_USB_PHY1>;
reset-names = "usb0_reset",
"usb1_reset";
status = "disabled";
#phy-cells = <1>;
};
ehci1: usb@01c1b000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI1>,
<&ccu CLK_BUS_EHCI1>,
<&ccu CLK_USB_OHCI1>;
resets = <&ccu RST_BUS_OHCI1>,
<&ccu RST_BUS_EHCI1>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
ohci1: usb@01c1b400 {
compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
reg = <0x01c1b400 0x100>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI1>,
<&ccu CLK_USB_OHCI1>;
resets = <&ccu RST_BUS_OHCI1>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
ccu: clock@01c20000 {
compatible = "allwinner,sun50i-a64-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&osc32k>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
};
pio: pinctrl@1c20800 {
compatible = "allwinner,sun50i-a64-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 69>;
clocks = <&ccu 58>;
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <2>;
uart0_pins_a: uart0@0 {
allwinner,pins = "PB8", "PB9";
allwinner,function = "uart0";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart0_pins_b: uart0@1 {
allwinner,pins = "PF2", "PF3";
allwinner,function = "uart0";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart1_2pins: uart1_2@0 {
allwinner,pins = "PG6", "PG7";
allwinner,function = "uart1";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart1_4pins: uart1_4@0 {
allwinner,pins = "PG6", "PG7", "PG8", "PG9";
allwinner,function = "uart1";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart2_2pins: uart2_2@0 {
allwinner,pins = "PB0", "PB1";
allwinner,function = "uart2";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart2_4pins: uart2_4@0 {
allwinner,pins = "PB0", "PB1", "PB2", "PB3";
allwinner,function = "uart2";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart3_pins_a: uart3@0 {
allwinner,pins = "PD0", "PD1";
allwinner,function = "uart3";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart3_2pins_b: uart3_2@1 {
allwinner,pins = "PH4", "PH5";
allwinner,function = "uart3";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart3_4pins_b: uart3_4@1 {
allwinner,pins = "PH4", "PH5", "PH6", "PH7";
allwinner,function = "uart3";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart4_2pins: uart4_2@0 {
allwinner,pins = "PD2", "PD3";
allwinner,function = "uart4";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart4_4pins: uart4_4@0 {
allwinner,pins = "PD2", "PD3", "PD4", "PD5";
allwinner,function = "uart4";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_pins: mmc0@0 {
allwinner,pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
allwinner,function = "mmc0";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_default_cd_pin: mmc0_cd_pin@0 {
allwinner,pins = "PF6";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
};
mmc1_pins: mmc1@0 {
allwinner,pins = "PG0", "PG1", "PG2", "PG3",
"PG4", "PG5";
allwinner,function = "mmc1";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc2_pins: mmc2@0 {
allwinner,pins = "PC1", "PC5", "PC6", "PC8",
"PC9", "PC10";
allwinner,function = "mmc2";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c0_pins: i2c0_pins {
allwinner,pins = "PH0", "PH1";
allwinner,function = "i2c0";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
#interrupt-cells = <3>;
i2c1_pins: i2c1_pins {
allwinner,pins = "PH2", "PH3";
allwinner,function = "i2c1";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
pins = "PH2", "PH3";
function = "i2c1";
};
i2c2_pins: i2c2_pins {
allwinner,pins = "PE14", "PE15";
allwinner,function = "i2c2";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
function = "mmc0";
drive-strength = <30>;
bias-pull-up;
};
rmii_pins: rmii_pins {
allwinner,pins = "PD10", "PD11", "PD13", "PD14",
"PD17", "PD18", "PD19", "PD20",
"PD22", "PD23";
allwinner,function = "emac";
allwinner,drive = <SUN4I_PINCTRL_40_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
mmc1_pins: mmc1-pins {
pins = "PG0", "PG1", "PG2", "PG3",
"PG4", "PG5";
function = "mmc1";
drive-strength = <30>;
bias-pull-up;
};
rgmii_pins: rgmii_pins {
allwinner,pins = "PD8", "PD9", "PD10", "PD11",
"PD12", "PD13", "PD15",
"PD16", "PD17", "PD18", "PD19",
"PD20", "PD21", "PD22", "PD23";
allwinner,function = "emac";
allwinner,drive = <SUN4I_PINCTRL_40_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
mmc2_pins: mmc2-pins {
pins = "PC1", "PC5", "PC6", "PC8", "PC9",
"PC10","PC11", "PC12", "PC13",
"PC14", "PC15", "PC16";
function = "mmc2";
drive-strength = <30>;
bias-pull-up;
};
};
ahb_rst: reset@1c202c0 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x01c202c0 0xc>;
};
uart0_pins_a: uart0@0 {
pins = "PB8", "PB9";
function = "uart0";
};
apb1_rst: reset@1c202d0 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x01c202d0 0x4>;
};
uart1_pins: uart1_pins {
pins = "PG6", "PG7";
function = "uart1";
};
apb2_rst: reset@1c202d8 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x01c202d8 0x4>;
uart1_rts_cts_pins: uart1_rts_cts_pins {
pins = "PG8", "PG9";
function = "uart1";
};
};
uart0: serial@1c28000 {
@ -551,8 +303,8 @@
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&bus_gates 112>;
resets = <&apb2_rst 16>;
clocks = <&ccu 67>;
resets = <&ccu 46>;
status = "disabled";
};
@ -562,8 +314,8 @@
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&bus_gates 113>;
resets = <&apb2_rst 17>;
clocks = <&ccu 68>;
resets = <&ccu 47>;
status = "disabled";
};
@ -573,8 +325,8 @@
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&bus_gates 114>;
resets = <&apb2_rst 18>;
clocks = <&ccu 69>;
resets = <&ccu 48>;
status = "disabled";
};
@ -584,8 +336,8 @@
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&bus_gates 115>;
resets = <&apb2_rst 19>;
clocks = <&ccu 70>;
resets = <&ccu 49>;
status = "disabled";
};
@ -595,24 +347,17 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&bus_gates 116>;
resets = <&apb2_rst 20>;
clocks = <&ccu 71>;
resets = <&ccu 50>;
status = "disabled";
};
rtc: rtc@1f00000 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
i2c0: i2c@1c2ac00 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 96>;
resets = <&apb2_rst 0>;
clocks = <&ccu 63>;
resets = <&ccu 42>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@ -622,8 +367,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 97>;
resets = <&apb2_rst 1>;
clocks = <&ccu 64>;
resets = <&ccu 43>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@ -633,54 +378,50 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 98>;
resets = <&apb2_rst 2>;
clocks = <&ccu 65>;
resets = <&ccu 44>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
emac: ethernet@01c30000 {
compatible = "allwinner,sun50i-a64-emac";
reg = <0x01c30000 0x2000>, <0x01c00030 0x4>;
reg-names = "emac", "syscon";
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ahb_rst 17>;
reset-names = "ahb";
clocks = <&bus_gates 17>;
clock-names = "ahb";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-controller;
#interrupt-cells = <3>;
};
usbphy: phy@1c1b810 {
compatible = "allwinner,sun50i-a64-usb-phy",
"allwinner,sun8i-a33-usb-phy";
reg = <0x01c1b810 0x14>, <0x01c1b800 0x4>;
reg-names = "phy_ctrl", "pmu1";
status = "disabled";
#phy-cells = <1>;
rtc: rtc@1f00000 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
ehci1: usb@01c1b000 {
compatible = "allwinner,sun50i-a64-ehci",
"generic-ehci";
reg = <0x01c1b000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
r_ccu: clock@1f01400 {
compatible = "allwinner,sun50i-a64-r-ccu";
reg = <0x01f01400 0x100>;
clocks = <&osc24M>, <&osc32k>, <&iosc>;
clock-names = "hosc", "losc", "iosc";
#clock-cells = <1>;
#reset-cells = <1>;
};
ohci1: usb@01c1b400 {
compatible = "allwinner,sun50i-a64-ohci",
"generic-ohci";
reg = <0x01c1b400 0x100>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "enabled";
r_pio: pinctrl@01f02c00 {
compatible = "allwinner,sun50i-a64-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
};
};
};

38
arch/arm/dts/sun50i-h5-orangepi-pc2.dts
View file

@ -42,40 +42,14 @@
/dts-v1/;
#include "sun8i-h3.dtsi"
#include "sun50i-h5.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "OrangePi PC 2";
compatible = "xunlong,orangepi-pc-2", "allwinner,sun50i-h5";
cpus {
cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
enable-method = "psci";
};
cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
enable-method = "psci";
};
cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
enable-method = "psci";
};
cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
};
chosen {
stdout-path = "serial0:115200n8";
};
@ -99,10 +73,6 @@
};
};
&gic {
compatible = "arm,gic-400";
};
&mmc0 {
compatible = "allwinner,sun50i-h5-mmc",
"allwinner,sun50i-a64-mmc",
@ -111,7 +81,7 @@
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 0>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
status = "okay";
};

39
arch/arm/dts/sun50i-a64-pine64-common.dtsi → arch/arm/dts/sun50i-h5-orangepi-prime.dts
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 ARM Ltd.
* Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -40,13 +40,26 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "sun50i-a64.dtsi"
/dts-v1/;
#include "sun50i-h5.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "OrangePi Prime";
compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5";
aliases {
serial0 = &uart0;
ethernet0 = &emac;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
reg = <0x40000000 0x80000000>;
};
soc {
@ -60,10 +73,14 @@
};
&mmc0 {
compatible = "allwinner,sun50i-h5-mmc",
"allwinner,sun50i-a64-mmc",
"allwinner,sun5i-a13-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>;
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
cd-gpios = <&pio 5 6 0>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
status = "okay";
};
@ -74,20 +91,14 @@
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
&usbphy {
status = "okay";
};
&usbphy {
status = "okay";
};
&ohci1 {
status = "okay";
status = "okay";
};
&ehci1 {
status = "okay";
status = "okay";
};

77
arch/arm/dts/sun50i-h5.dtsi Normal file
View file

@ -0,0 +1,77 @@
/*
* Copyright (c) 2016 ARM Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "sun8i-h3.dtsi"
/ {
cpus {
cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
enable-method = "psci";
};
cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
enable-method = "psci";
};
cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
enable-method = "psci";
};
cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
};
};
&gic {
compatible = "arm,gic-400";
};

64
arch/arm/dts/sun8i-h3-nanopi-m1.dts Normal file
View file

@ -0,0 +1,64 @@
/*
* Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "sun8i-h3-nanopi.dtsi"
/ {
model = "FriendlyArm NanoPi M1";
compatible = "friendlyarm,nanopi-m1", "allwinner,sun8i-h3";
};
&ehci1 {
status = "okay";
};
&ehci2 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&ohci2 {
status = "okay";
};

79
arch/arm/dts/sun8i-h3-nanopi-neo.dts
View file

@ -40,88 +40,11 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun8i-h3.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#include "sun8i-h3-nanopi.dtsi"
/ {
model = "FriendlyARM NanoPi NEO";
compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
pwr {
label = "nanopi:green:pwr";
gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
default-state = "on";
};
status {
label = "nanopi:blue:status";
gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
};
};
};
&ehci3 {
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
cd-inverted;
status = "okay";
};
&ohci3 {
status = "okay";
};
&pio {
leds_opc: led-pins {
allwinner,pins = "PA10";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
&r_pio {
leds_r_opc: led-pins {
allwinner,pins = "PL10";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&usbphy {
/* USB VBUS is always on */
status = "okay";
};
&emac {

137
arch/arm/dts/sun8i-h3-nanopi.dtsi Normal file
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@ -0,0 +1,137 @@
/*
* Copyright (C) 2016 James Pettigrew <james@innovum.com.au>
* Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun8i-h3.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_npi>, <&leds_r_npi>;
status {
label = "nanopi:blue:status";
gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
pwr {
label = "nanopi:green:pwr";
gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
r_gpio_keys {
compatible = "gpio-keys";
input-name = "k1";
pinctrl-names = "default";
pinctrl-0 = <&sw_r_npi>;
k1@0 {
label = "k1";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
};
};
};
&ehci3 {
status = "okay";
};
&mmc0 {
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
status = "okay";
vmmc-supply = <&reg_vcc3v3>;
};
&ohci3 {
status = "okay";
};
&pio {
leds_npi: led_pins@0 {
pins = "PA10";
function = "gpio_out";
};
};
&r_pio {
leds_r_npi: led_pins@0 {
pins = "PL10";
function = "gpio_out";
};
sw_r_npi: key_pins@0 {
pins = "PL3";
function = "gpio_in";
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&usbphy {
status = "okay";
};

15
board/sunxi/MAINTAINERS
View file

@ -114,6 +114,11 @@ S: Maintained
F: configs/Bananapi_M2_Ultra_defconfig
F: arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
BANANAPI M64
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/bananapi_m64_defconfig
COLOMBUS BOARD
M: Maxime Ripard <maxime.ripard@free-electrons.com>
S: Maintained
@ -237,6 +242,11 @@ M: Siarhei Siamashka <siarhei.siamashka@gmail.com>
S: Maintained
F: configs/MSI_Primo81_defconfig
NANOPI-M1 BOARD
M: Mylène Josserand <mylene.josserand@free-electrons.com>
S: Maintained
F: configs/nanopi_m1_defconfig
NANOPI-NEO BOARD
M: Jelle van der Waa <jelle@vdwaa.nl>
S: Maintained
@ -262,6 +272,11 @@ M: Andre Przywara <andre.przywara@arm.com>
S: Maintained
F: configs/orangepi_pc2_defconfig
ORANGEPI PRIME BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/orangepi_prime_defconfig
PINE64 BOARDS
M: Andre Przywara <andre.przywara@arm.com>
S: Maintained

1
configs/Sinlinx_SinA33_defconfig
View file

@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_CONS_INDEX=1
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=15291

17
configs/bananapi_m64_defconfig Normal file
View file

@ -0,0 +1,17 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-bananapi-m64"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y

16
configs/nanopi_m1_defconfig Normal file
View file

@ -0,0 +1,16 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_EHCI_HCD=y

16
configs/orangepi_prime_defconfig Normal file
View file

@ -0,0 +1,16 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881977
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y

134
include/dt-bindings/clock/sun50i-a64-ccu.h Normal file
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@ -0,0 +1,134 @@
/*
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
#define _DT_BINDINGS_CLK_SUN50I_A64_H_
#define CLK_BUS_MIPI_DSI 28
#define CLK_BUS_CE 29
#define CLK_BUS_DMA 30
#define CLK_BUS_MMC0 31
#define CLK_BUS_MMC1 32
#define CLK_BUS_MMC2 33
#define CLK_BUS_NAND 34
#define CLK_BUS_DRAM 35
#define CLK_BUS_EMAC 36
#define CLK_BUS_TS 37
#define CLK_BUS_HSTIMER 38
#define CLK_BUS_SPI0 39
#define CLK_BUS_SPI1 40
#define CLK_BUS_OTG 41
#define CLK_BUS_EHCI0 42
#define CLK_BUS_EHCI1 43
#define CLK_BUS_OHCI0 44
#define CLK_BUS_OHCI1 45
#define CLK_BUS_VE 46
#define CLK_BUS_TCON0 47
#define CLK_BUS_TCON1 48
#define CLK_BUS_DEINTERLACE 49
#define CLK_BUS_CSI 50
#define CLK_BUS_HDMI 51
#define CLK_BUS_DE 52
#define CLK_BUS_GPU 53
#define CLK_BUS_MSGBOX 54
#define CLK_BUS_SPINLOCK 55
#define CLK_BUS_CODEC 56
#define CLK_BUS_SPDIF 57
#define CLK_BUS_PIO 58
#define CLK_BUS_THS 59
#define CLK_BUS_I2S0 60
#define CLK_BUS_I2S1 61
#define CLK_BUS_I2S2 62
#define CLK_BUS_I2C0 63
#define CLK_BUS_I2C1 64
#define CLK_BUS_I2C2 65
#define CLK_BUS_SCR 66
#define CLK_BUS_UART0 67
#define CLK_BUS_UART1 68
#define CLK_BUS_UART2 69
#define CLK_BUS_UART3 70
#define CLK_BUS_UART4 71
#define CLK_BUS_DBG 72
#define CLK_THS 73
#define CLK_NAND 74
#define CLK_MMC0 75
#define CLK_MMC1 76
#define CLK_MMC2 77
#define CLK_TS 78
#define CLK_CE 79
#define CLK_SPI0 80
#define CLK_SPI1 81
#define CLK_I2S0 82
#define CLK_I2S1 83
#define CLK_I2S2 84
#define CLK_SPDIF 85
#define CLK_USB_PHY0 86
#define CLK_USB_PHY1 87
#define CLK_USB_HSIC 88
#define CLK_USB_HSIC_12M 89
#define CLK_USB_OHCI0 91
#define CLK_USB_OHCI1 93
#define CLK_DRAM_VE 95
#define CLK_DRAM_CSI 96
#define CLK_DRAM_DEINTERLACE 97
#define CLK_DRAM_TS 98
#define CLK_DE 99
#define CLK_TCON0 100
#define CLK_TCON1 101
#define CLK_DEINTERLACE 102
#define CLK_CSI_MISC 103
#define CLK_CSI_SCLK 104
#define CLK_CSI_MCLK 105
#define CLK_VE 106
#define CLK_AC_DIG 107
#define CLK_AC_DIG_4X 108
#define CLK_AVS 109
#define CLK_HDMI 110
#define CLK_HDMI_DDC 111
#define CLK_DSI_DPHY 113
#define CLK_GPU 114
#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */

98
include/dt-bindings/reset/sun50i-a64-ccu.h Normal file
View file

@ -0,0 +1,98 @@
/*
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_
#define _DT_BINDINGS_RST_SUN50I_A64_H_
#define RST_USB_PHY0 0
#define RST_USB_PHY1 1
#define RST_USB_HSIC 2
#define RST_DRAM 3
#define RST_MBUS 4
#define RST_BUS_MIPI_DSI 5
#define RST_BUS_CE 6
#define RST_BUS_DMA 7
#define RST_BUS_MMC0 8
#define RST_BUS_MMC1 9
#define RST_BUS_MMC2 10
#define RST_BUS_NAND 11
#define RST_BUS_DRAM 12
#define RST_BUS_EMAC 13
#define RST_BUS_TS 14
#define RST_BUS_HSTIMER 15
#define RST_BUS_SPI0 16
#define RST_BUS_SPI1 17
#define RST_BUS_OTG 18
#define RST_BUS_EHCI0 19
#define RST_BUS_EHCI1 20
#define RST_BUS_OHCI0 21
#define RST_BUS_OHCI1 22
#define RST_BUS_VE 23
#define RST_BUS_TCON0 24
#define RST_BUS_TCON1 25
#define RST_BUS_DEINTERLACE 26
#define RST_BUS_CSI 27
#define RST_BUS_HDMI0 28
#define RST_BUS_HDMI1 29
#define RST_BUS_DE 30
#define RST_BUS_GPU 31
#define RST_BUS_MSGBOX 32
#define RST_BUS_SPINLOCK 33
#define RST_BUS_DBG 34
#define RST_BUS_LVDS 35
#define RST_BUS_CODEC 36
#define RST_BUS_SPDIF 37
#define RST_BUS_THS 38
#define RST_BUS_I2S0 39
#define RST_BUS_I2S1 40
#define RST_BUS_I2S2 41
#define RST_BUS_I2C0 42
#define RST_BUS_I2C1 43
#define RST_BUS_I2C2 44
#define RST_BUS_SCR 45
#define RST_BUS_UART0 46
#define RST_BUS_UART1 47
#define RST_BUS_UART2 48
#define RST_BUS_UART3 49
#define RST_BUS_UART4 50
#endif /* _DT_BINDINGS_RST_SUN50I_A64_H_ */