diff --git a/Kconfig b/Kconfig
index cbb691e160..e0c899210e 100644
--- a/Kconfig
+++ b/Kconfig
@@ -91,7 +91,7 @@ config SYS_EXTRA_OPTIONS
 	depends on !SPL_BUILD
 	help
 	  The old configuration infrastructure (= mkconfig + boards.cfg)
-	  provided the extra options field. It you have something like
+	  provided the extra options field. If you have something like
 	  "HAS_BAR,BAZ=64", the optional options
 	    #define CONFIG_HAS
 	    #define CONFIG_BAZ	64
@@ -103,3 +103,15 @@ config SYS_EXTRA_OPTIONS
 endmenu		# Boot images
 
 source "arch/Kconfig"
+
+source "common/Kconfig"
+
+source "dts/Kconfig"
+
+source "net/Kconfig"
+
+source "drivers/Kconfig"
+
+source "fs/Kconfig"
+
+source "lib/Kconfig"
diff --git a/MAINTAINERS b/MAINTAINERS
index af194ca755..aafa061ed8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -149,6 +149,15 @@ F:	arch/arm/include/asm/arch-davinci/
 F:	arch/arm/include/asm/arch-omap*/
 F:	arch/arm/include/asm/ti-common/
 
+ARM UNIPHIER
+M:	Masahiro Yamada <yamada.m@jp.panasonic.com>
+S:	Maintained
+T:	git git://git.denx.de/u-boot-uniphier.git
+F:	arch/arm/cpu/armv7/uniphier/
+F:	arch/arm/include/asm/arch-uniphier/
+F:	configs/ph1_*_defconfig
+F:	drivers/serial/serial_uniphier.c
+
 ARM ZYNQ
 M:	Michal Simek <monstr@monstr.eu>
 S:	Maintained
diff --git a/Makefile b/Makefile
index 1fccd0b7e2..62211132b0 100644
--- a/Makefile
+++ b/Makefile
@@ -613,11 +613,9 @@ libs-y += fs/
 libs-y += net/
 libs-y += disk/
 libs-y += drivers/
-libs-$(CONFIG_DM) += drivers/core/
 libs-y += drivers/dma/
 libs-y += drivers/gpio/
 libs-y += drivers/i2c/
-libs-y += drivers/input/
 libs-y += drivers/mmc/
 libs-y += drivers/mtd/
 libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/
@@ -649,7 +647,6 @@ libs-$(CONFIG_API) += api/
 libs-$(CONFIG_HAS_POST) += post/
 libs-y += test/
 libs-y += test/dm/
-libs-$(CONFIG_DM_DEMO) += drivers/demo/
 
 ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
 libs-y += arch/$(ARCH)/imx-common/
diff --git a/README b/README
index 0a0f528af1..46def0086b 100644
--- a/README
+++ b/README
@@ -272,7 +272,7 @@ board. This allows feature development which is not board- or architecture-
 specific to be undertaken on a native platform. The sandbox is also used to
 run some of U-Boot's tests.
 
-See board/sandbox/sandbox/README.sandbox for more details.
+See board/sandbox/README.sandbox for more details.
 
 
 Configuration Options:
@@ -538,6 +538,12 @@ The following options need to be configured:
 		interleaving mode, handled by Dickens for Freescale layerscape
 		SoCs with ARM core.
 
+		CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
+		Number of controllers used as main memory.
+
+		CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
+		Number of controllers used for other than main memory.
+
 - Intel Monahans options:
 		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 
@@ -1629,6 +1635,16 @@ The following options need to be configured:
 		downloads. This buffer should be as large as possible for a
 		platform. Define this to the size available RAM for fastboot.
 
+		CONFIG_FASTBOOT_FLASH
+		The fastboot protocol includes a "flash" command for writing
+		the downloaded image to a non-volatile storage device. Define
+		this to enable the "fastboot flash" command.
+
+		CONFIG_FASTBOOT_FLASH_MMC_DEV
+		The fastboot "flash" command requires additional information
+		regarding the non-volatile storage device. Define this to
+		the eMMC device that fastboot should use to store the image.
+
 - Journaling Flash filesystem support:
 		CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
 		CONFIG_JFFS2_NAND_DEV
@@ -3849,12 +3865,9 @@ Configuration Settings:
 		The memory will be freed (or in fact just forgotton) when
 		U-Boot relocates itself.
 
-		Pre-relocation malloc() is only supported on sandbox
+		Pre-relocation malloc() is only supported on ARM and sandbox
 		at present but is fairly easy to enable for other archs.
 
-		Pre-relocation malloc() is only supported on ARM at present
-		but is fairly easy to enable for other archs.
-
 - CONFIG_SYS_BOOTM_LEN:
 		Normally compressed uImages are limited to an
 		uncompressed size of 8 MBytes. If this is not enough,
diff --git a/arch/Kconfig b/arch/Kconfig
index c9ccb7db17..bf2676469c 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -7,6 +7,7 @@ config ARC
 
 config ARM
 	bool "ARM architecture"
+	select SUPPORT_OF_CONTROL
 
 config AVR32
 	bool "AVR32 architecture"
@@ -19,6 +20,7 @@ config M68K
 
 config MICROBLAZE
 	bool "MicroBlaze architecture"
+	select SUPPORT_OF_CONTROL
 
 config MIPS
 	bool "MIPS architecture"
@@ -37,6 +39,7 @@ config PPC
 
 config SANDBOX
 	bool "Sandbox"
+	select SUPPORT_OF_CONTROL
 
 config SH
 	bool "SuperH architecture"
@@ -46,6 +49,7 @@ config SPARC
 
 config X86
 	bool "x86 architecture"
+	select SUPPORT_OF_CONTROL
 
 endchoice
 
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c8537bbe88..43ba33a2af 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -4,6 +4,9 @@ menu "ARM architecture"
 config SYS_ARCH
 	default "arm"
 
+config ARM64
+	bool
+
 choice
 	prompt "Target select"
 
@@ -423,6 +426,9 @@ config OMAP54XX
 config RMOBILE
 	bool "Renesas ARM SoCs"
 
+config TARGET_CM_FX6
+	bool "Support cm_fx6"
+
 config TARGET_S5P_GONI
 	bool "Support s5p_goni"
 
@@ -456,18 +462,19 @@ config ZYNQ
 config TEGRA
 	bool "NVIDIA Tegra"
 	select SPL
+	select OF_CONTROL if !SPL_BUILD
 
 config TARGET_VEXPRESS_AEMV8A
 	bool "Support vexpress_aemv8a"
-
-config TARGET_VEXPRESS_AEMV8A_SEMI
-	bool "Support vexpress_aemv8a_semi"
+	select ARM64
 
 config TARGET_LS2085A_EMU
 	bool "Support ls2085a_emu"
+	select ARM64
 
 config TARGET_LS2085A_SIMU
 	bool "Support ls2085a_simu"
+	select ARM64
 
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds_nor"
@@ -514,8 +521,13 @@ config TARGET_COLIBRI_PXA270
 config TARGET_JORNADA
 	bool "Support jornada"
 
+config ARCH_UNIPHIER
+	bool "Panasonic UniPhier platform"
+
 endchoice
 
+source "arch/arm/cpu/armv8/Kconfig"
+
 source "arch/arm/cpu/arm926ejs/davinci/Kconfig"
 
 source "arch/arm/cpu/armv7/exynos/Kconfig"
@@ -540,6 +552,8 @@ source "arch/arm/cpu/armv7/rmobile/Kconfig"
 
 source "arch/arm/cpu/armv7/tegra-common/Kconfig"
 
+source "arch/arm/cpu/armv7/uniphier/Kconfig"
+
 source "arch/arm/cpu/arm926ejs/versatile/Kconfig"
 
 source "arch/arm/cpu/armv7/zynq/Kconfig"
@@ -584,6 +598,7 @@ source "board/cirrus/edb93xx/Kconfig"
 source "board/cm4008/Kconfig"
 source "board/cm41xx/Kconfig"
 source "board/compulab/cm_t335/Kconfig"
+source "board/compulab/cm_fx6/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
 source "board/creative/xfi3/Kconfig"
 source "board/davedenx/qong/Kconfig"
diff --git a/arch/arm/cpu/arm1176/tnetv107x/clock.c b/arch/arm/cpu/arm1176/tnetv107x/clock.c
index 3708b6f59f..47c23bb268 100644
--- a/arch/arm/cpu/arm1176/tnetv107x/clock.c
+++ b/arch/arm/cpu/arm1176/tnetv107x/clock.c
@@ -362,7 +362,7 @@ static void init_pll(const struct pll_init_data *data)
 	pllctl_reg_write(data->pll, ctl, tmp);
 
 	mult = data->pll_freq / fpll;
-	for (mult = MAX(mult, 1); mult <= MAX_MULT; mult++) {
+	for (mult = max(mult, 1); mult <= MAX_MULT; mult++) {
 		div = (fpll * mult) / data->pll_freq;
 		if (div < 1 || div > MAX_DIV)
 			continue;
diff --git a/arch/arm/cpu/armv7/at91/clock.c b/arch/arm/cpu/armv7/at91/clock.c
index 1588e0c8ea..36ed4a6394 100644
--- a/arch/arm/cpu/armv7/at91/clock.c
+++ b/arch/arm/cpu/armv7/at91/clock.c
@@ -114,9 +114,25 @@ int at91_clock_init(unsigned long main_clock)
 void at91_periph_clk_enable(int id)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	u32 regval;
 
-	if (id > 31)
-		writel(1 << (id - 32), &pmc->pcer1);
-	else
-		writel(1 << id, &pmc->pcer);
+	if (id > AT91_PMC_PCR_PID_MASK)
+		return;
+
+	regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id;
+
+	writel(regval, &pmc->pcr);
+}
+
+void at91_periph_clk_disable(int id)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	u32 regval;
+
+	if (id > AT91_PMC_PCR_PID_MASK)
+		return;
+
+	regval = AT91_PMC_PCR_CMD_WRITE | id;
+
+	writel(regval, &pmc->pcr);
 }
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig
index d132f03514..e7c93d8c1f 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -23,18 +23,23 @@ config TARGET_ODROID
 
 config TARGET_ARNDALE
 	bool "Exynos5250 Arndale board"
+	select OF_CONTROL if !SPL_BUILD
 
 config TARGET_SMDK5250
 	bool "SMDK5250 board"
+	select OF_CONTROL if !SPL_BUILD
 
 config TARGET_SNOW
 	bool "Snow board"
+	select OF_CONTROL if !SPL_BUILD
 
 config TARGET_SMDK5420
 	bool "SMDK5420 board"
+	select OF_CONTROL if !SPL_BUILD
 
 config TARGET_PEACH_PIT
 	bool "Peach Pi board"
+	select OF_CONTROL if !SPL_BUILD
 
 endchoice
 
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c
index 2391e794e8..2eabec10f9 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -10,6 +10,7 @@
 #include <asm/io.h>
 #include <common.h>
 #include <asm/arch/ddr3.h>
+#include <asm/arch/psc_defs.h>
 
 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
 {
@@ -86,3 +87,77 @@ void ddr3_reset_ddrphy(void)
 	tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
 	__raw_writel(tmp, KS2_DDR3APLLCTL1);
 }
+
+#ifdef CONFIG_SOC_K2HK
+/**
+ * ddr3_reset_workaround - reset workaround in case if leveling error
+ * detected for PG 1.0 and 1.1 k2hk SoCs
+ */
+void ddr3_err_reset_workaround(void)
+{
+	unsigned int tmp;
+	unsigned int tmp_a;
+	unsigned int tmp_b;
+
+	/*
+	 * Check for PGSR0 error bits of DDR3 PHY.
+	 * Check for WLERR, QSGERR, WLAERR,
+	 * RDERR, WDERR, REERR, WEERR error to see if they are set or not
+	 */
+	tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
+	tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
+
+	if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) {
+		printf("DDR Leveling Error Detected!\n");
+		printf("DDR3A PGSR0 = 0x%x\n", tmp_a);
+		printf("DDR3B PGSR0 = 0x%x\n", tmp_b);
+
+		/*
+		 * Write Keys to KICK registers to enable writes to registers
+		 * in boot config space
+		 */
+		__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
+		__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
+
+		/*
+		 * Move DDR3A Module out of reset isolation by setting
+		 * MDCTL23[12] = 0
+		 */
+		tmp_a = __raw_readl(KS2_PSC_BASE +
+				    PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
+
+		tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0);
+		__raw_writel(tmp_a, KS2_PSC_BASE +
+			     PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
+
+		/*
+		 * Move DDR3B Module out of reset isolation by setting
+		 * MDCTL24[12] = 0
+		 */
+		tmp_b = __raw_readl(KS2_PSC_BASE +
+				    PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
+		tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0);
+		__raw_writel(tmp_b, KS2_PSC_BASE +
+			     PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
+
+		/*
+		 * Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes
+		 * to RSTCTRL and RSTCFG
+		 */
+		tmp = __raw_readl(KS2_RSTCTRL);
+		tmp &= KS2_RSTCTRL_MASK;
+		tmp |= KS2_RSTCTRL_KEY;
+		__raw_writel(tmp, KS2_RSTCTRL);
+
+		/*
+		 * Set PLL Controller to drive hard reset on SW trigger by
+		 * setting RSTCFG[13] = 0
+		 */
+		tmp = __raw_readl(KS2_RSTCTRL_RSCFG);
+		tmp &= ~KS2_RSTYPE_PLL_SOFT;
+		__raw_writel(tmp, KS2_RSTCTRL_RSCFG);
+
+		reset_cpu(0);
+	}
+}
+#endif
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 820b8d5154..336e557a27 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -36,6 +36,35 @@ void enable_ocotp_clk(unsigned char enable)
 }
 #endif
 
+#ifdef CONFIG_NAND_MXS
+void setup_gpmi_io_clk(u32 cfg)
+{
+	/* Disable clocks per ERR007177 from MX6 errata */
+	clrbits_le32(&imx_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+
+	clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+	clrsetbits_le32(&imx_ccm->cs2cdr,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+			cfg);
+
+	setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+	setbits_le32(&imx_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+}
+#endif
+
 void enable_usboh3_clk(unsigned char enable)
 {
 	u32 reg;
@@ -49,6 +78,67 @@ void enable_usboh3_clk(unsigned char enable)
 
 }
 
+#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
+void enable_enet_clk(unsigned char enable)
+{
+	u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
+
+	if (enable)
+		setbits_le32(&imx_ccm->CCGR1, mask);
+	else
+		clrbits_le32(&imx_ccm->CCGR1, mask);
+}
+#endif
+
+#ifdef CONFIG_MXC_UART
+void enable_uart_clk(unsigned char enable)
+{
+	u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
+
+	if (enable)
+		setbits_le32(&imx_ccm->CCGR5, mask);
+	else
+		clrbits_le32(&imx_ccm->CCGR5, mask);
+}
+#endif
+
+#ifdef CONFIG_SPI
+/* spi_num can be from 0 - 4 */
+int enable_cspi_clock(unsigned char enable, unsigned spi_num)
+{
+	u32 mask;
+
+	if (spi_num > 4)
+		return -EINVAL;
+
+	mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2);
+	if (enable)
+		setbits_le32(&imx_ccm->CCGR1, mask);
+	else
+		clrbits_le32(&imx_ccm->CCGR1, mask);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MMC
+int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
+{
+	u32 mask;
+
+	if (bus_num > 3)
+		return -EINVAL;
+
+	mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
+	if (enable)
+		setbits_le32(&imx_ccm->CCGR6, mask);
+	else
+		clrbits_le32(&imx_ccm->CCGR6, mask);
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_SYS_I2C_MXC
 /* i2c_num can be from 0 - 2 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
@@ -509,6 +599,7 @@ int enable_pcie_clock(void)
 	struct anatop_regs *anatop_regs =
 		(struct anatop_regs *)ANATOP_BASE_ADDR;
 	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 lvds1_clk_sel;
 
 	/*
 	 * Here be dragons!
@@ -518,17 +609,25 @@ int enable_pcie_clock(void)
 	 * marked as ANATOP_MISC1 is actually documented in the PMU section
 	 * of the datasheet as PMU_MISC1.
 	 *
-	 * Switch LVDS clock source to SATA (0xb), disable clock INPUT and
-	 * enable clock OUTPUT. This is important for PCI express link that
-	 * is clocked from the i.MX6.
+	 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
+	 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
+	 * for PCI express link that is clocked from the i.MX6.
 	 */
 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN		(1 << 12)
 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN		(1 << 10)
 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK	0x0000001F
+#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF	0xa
+#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF	0xb
+
+	if (is_cpu_type(MXC_CPU_MX6SX))
+		lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
+	else
+		lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
+
 	clrsetbits_le32(&anatop_regs->ana_misc1,
 			ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
 			ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
-			ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);
+			ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
 
 	/* PCIe reference clock sourced from AXI. */
 	clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 1ab69f63c8..7a9b03a68f 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -184,18 +184,18 @@ void mx6sdl_dram_iocfg(unsigned width,
  */
 #define MR(val, ba, cmd, cs1) \
 	((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
-void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
-		  const struct mx6_mmdc_calibration *c,
-		  const struct mx6_ddr3_cfg *m)
+void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
+		  const struct mx6_mmdc_calibration *calib,
+		  const struct mx6_ddr3_cfg *ddr3_cfg)
 {
 	volatile struct mmdc_p_regs *mmdc0;
 	volatile struct mmdc_p_regs *mmdc1;
-	u32 reg;
+	u32 val;
 	u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
 	u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
 	u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
 	u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
-	u16 CS0_END;
+	u16 cs0_end;
 	u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
 	u8 coladdr;
 	int clkper; /* clock period in picoseconds */
@@ -215,13 +215,12 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
 		clock = 400;
 		tcwl = 3;
 	}
-	clkper = (1000*1000)/clock; /* ps */
+	clkper = (1000 * 1000) / clock; /* pico seconds */
 	todtlon = tcwl;
 	taxpd = tcwl;
 	tanpd = tcwl;
-	tcwl = tcwl;
 
-	switch (m->density) {
+	switch (ddr3_cfg->density) {
 	case 1: /* 1Gb per chip */
 		trfc = DIV_ROUND_UP(110000, clkper) - 1;
 		txs = DIV_ROUND_UP(120000, clkper) - 1;
@@ -240,80 +239,82 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
 		break;
 	default:
 		/* invalid density */
-		printf("invalid chip density\n");
+		puts("invalid chip density\n");
 		hang();
 		break;
 	}
 	txpr = txs;
 
-	switch (m->mem_speed) {
+	switch (ddr3_cfg->mem_speed) {
 	case 800:
-		txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
-		tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
-		if (m->pagesz == 1) {
+		txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
+		tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
+		if (ddr3_cfg->pagesz == 1) {
 			tfaw = DIV_ROUND_UP(40000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+			trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
 		} else {
 			tfaw = DIV_ROUND_UP(50000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+			trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
 		}
 		break;
 	case 1066:
-		txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
-		tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
-		if (m->pagesz == 1) {
+		txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
+		tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
+		if (ddr3_cfg->pagesz == 1) {
 			tfaw = DIV_ROUND_UP(37500, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+			trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
 		} else {
 			tfaw = DIV_ROUND_UP(50000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+			trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
 		}
 		break;
 	case 1333:
-		txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
-		tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
-		if (m->pagesz == 1) {
+		txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1;
+		tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
+		if (ddr3_cfg->pagesz == 1) {
 			tfaw = DIV_ROUND_UP(30000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
+			trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1;
 		} else {
 			tfaw = DIV_ROUND_UP(45000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+			trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
 		}
 		break;
 	case 1600:
-		txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
-		tcke = DIV_ROUND_UP(MAX(3*clkper, 5000), clkper) - 1;
-		if (m->pagesz == 1) {
+		txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1;
+		tcke = DIV_ROUND_UP(max(3 * clkper, 5000), clkper) - 1;
+		if (ddr3_cfg->pagesz == 1) {
 			tfaw = DIV_ROUND_UP(30000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
+			trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1;
 		} else {
 			tfaw = DIV_ROUND_UP(40000, clkper) - 1;
-			trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+			trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
 		}
 		break;
 	default:
-		printf("invalid memory speed\n");
+		puts("invalid memory speed\n");
 		hang();
 		break;
 	}
-	txpdll = DIV_ROUND_UP(MAX(10*clkper, 24000), clkper) - 1;
-	tcl = DIV_ROUND_UP(m->trcd, clkper/10) - 3;
-	tcksre = DIV_ROUND_UP(MAX(5*clkper, 10000), clkper);
-	tcksrx = tcksre;
+	txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
+	tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
 	taonpd = DIV_ROUND_UP(2000, clkper) - 1;
+	tcksrx = tcksre;
 	taofpd = taonpd;
-	trp = DIV_ROUND_UP(m->trcd, clkper/10) - 1;
+	twr  = DIV_ROUND_UP(15000, clkper) - 1;
+	tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
+	trc  = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
+	tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
+	tcl  = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
+	trp  = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
+	twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
 	trcd = trp;
-	trc = DIV_ROUND_UP(m->trcmin, clkper/10) - 1;
-	tras = DIV_ROUND_UP(m->trasmin, clkper/10) - 1;
-	twr = DIV_ROUND_UP(15000, clkper) - 1;
-	tmrd = DIV_ROUND_UP(MAX(12*clkper, 15000), clkper) - 1;
-	twtr = ROUND(MAX(4*clkper, 7500)/clkper, 1) - 1;
 	trtp = twtr;
-	CS0_END = ((4*i->cs_density) <= 120) ? (4*i->cs_density)+7 : 127;
-	debug("density:%d Gb (%d Gb per chip)\n", i->cs_density, m->density);
+	cs0_end = 4 * sysinfo->cs_density - 1;
+
+	debug("density:%d Gb (%d Gb per chip)\n",
+	      sysinfo->cs_density, ddr3_cfg->density);
 	debug("clock: %dMHz (%d ps)\n", clock, clkper);
-	debug("memspd:%d\n", m->mem_speed);
+	debug("memspd:%d\n", ddr3_cfg->mem_speed);
 	debug("tcke=%d\n", tcke);
 	debug("tcksrx=%d\n", tcksrx);
 	debug("tcksre=%d\n", tcksre);
@@ -340,11 +341,11 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
 	debug("twtr=%d\n", twtr);
 	debug("trrd=%d\n", trrd);
 	debug("txpr=%d\n", txpr);
-	debug("CS0_END=%d\n", CS0_END);
-	debug("ncs=%d\n", i->ncs);
-	debug("Rtt_wr=%d\n", i->rtt_wr);
-	debug("Rtt_nom=%d\n", i->rtt_nom);
-	debug("SRT=%d\n", m->SRT);
+	debug("cs0_end=%d\n", cs0_end);
+	debug("ncs=%d\n", sysinfo->ncs);
+	debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
+	debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
+	debug("SRT=%d\n", ddr3_cfg->SRT);
 	debug("tcl=%d\n", tcl);
 	debug("twr=%d\n", twr);
 
@@ -354,142 +355,136 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
 	 *  see:
 	 *   appnote, ddr3 spreadsheet
 	 */
-	mmdc0->mpwldectrl0 = c->p0_mpwldectrl0;
-	mmdc0->mpwldectrl1 = c->p0_mpwldectrl1;
-	mmdc0->mpdgctrl0 = c->p0_mpdgctrl0;
-	mmdc0->mpdgctrl1 = c->p0_mpdgctrl1;
-	mmdc0->mprddlctl = c->p0_mprddlctl;
-	mmdc0->mpwrdlctl = c->p0_mpwrdlctl;
-	if (i->dsize > 1) {
-		mmdc1->mpwldectrl0 = c->p1_mpwldectrl0;
-		mmdc1->mpwldectrl1 = c->p1_mpwldectrl1;
-		mmdc1->mpdgctrl0 = c->p1_mpdgctrl0;
-		mmdc1->mpdgctrl1 = c->p1_mpdgctrl1;
-		mmdc1->mprddlctl = c->p1_mprddlctl;
-		mmdc1->mpwrdlctl = c->p1_mpwrdlctl;
+	mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
+	mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
+	mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
+	mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
+	mmdc0->mprddlctl = calib->p0_mprddlctl;
+	mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
+	if (sysinfo->dsize > 1) {
+		mmdc1->mpwldectrl0 = calib->p1_mpwldectrl0;
+		mmdc1->mpwldectrl1 = calib->p1_mpwldectrl1;
+		mmdc1->mpdgctrl0 = calib->p1_mpdgctrl0;
+		mmdc1->mpdgctrl1 = calib->p1_mpdgctrl1;
+		mmdc1->mprddlctl = calib->p1_mprddlctl;
+		mmdc1->mpwrdlctl = calib->p1_mpwrdlctl;
 	}
 
 	/* Read data DQ Byte0-3 delay */
-	mmdc0->mprddqby0dl = (u32)0x33333333;
-	mmdc0->mprddqby1dl = (u32)0x33333333;
-	if (i->dsize > 0) {
-		mmdc0->mprddqby2dl = (u32)0x33333333;
-		mmdc0->mprddqby3dl = (u32)0x33333333;
+	mmdc0->mprddqby0dl = 0x33333333;
+	mmdc0->mprddqby1dl = 0x33333333;
+	if (sysinfo->dsize > 0) {
+		mmdc0->mprddqby2dl = 0x33333333;
+		mmdc0->mprddqby3dl = 0x33333333;
 	}
-	if (i->dsize > 1) {
-		mmdc1->mprddqby0dl = (u32)0x33333333;
-		mmdc1->mprddqby1dl = (u32)0x33333333;
-		mmdc1->mprddqby2dl = (u32)0x33333333;
-		mmdc1->mprddqby3dl = (u32)0x33333333;
+
+	if (sysinfo->dsize > 1) {
+		mmdc1->mprddqby0dl = 0x33333333;
+		mmdc1->mprddqby1dl = 0x33333333;
+		mmdc1->mprddqby2dl = 0x33333333;
+		mmdc1->mprddqby3dl = 0x33333333;
 	}
 
 	/* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
-	reg = (i->rtt_nom == 2) ? 0x00011117 : 0x00022227;
-	mmdc0->mpodtctrl = reg;
-	if (i->dsize > 1)
-		mmdc1->mpodtctrl = reg;
+	val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
+	mmdc0->mpodtctrl = val;
+	if (sysinfo->dsize > 1)
+		mmdc1->mpodtctrl = val;
 
 	/* complete calibration */
-	reg = (1 << 11); /* Force measurement on delay-lines */
-	mmdc0->mpmur0 = reg;
-	if (i->dsize > 1)
-		mmdc1->mpmur0 = reg;
+	val = (1 << 11); /* Force measurement on delay-lines */
+	mmdc0->mpmur0 = val;
+	if (sysinfo->dsize > 1)
+		mmdc1->mpmur0 = val;
 
 	/* Step 1: configuration request */
 	mmdc0->mdscr = (u32)(1 << 15); /* config request */
 
 	/* Step 2: Timing configuration */
-	reg = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) |
-	      (tfaw << 4) | tcl;
-	mmdc0->mdcfg0 = reg;
-	reg = (trcd << 29) | (trp << 26) | (trc << 21) | (tras << 16) |
-	      (1 << 15) |		/* trpa */
-	      (twr << 9) | (tmrd << 5) | tcwl;
-	mmdc0->mdcfg1 = reg;
-	reg = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
-	mmdc0->mdcfg2 = reg;
-	reg = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | (taxpd << 16) |
-	      (todtlon << 12) | (todt_idle_off << 4);
-	mmdc0->mdotc = reg;
-	mmdc0->mdasp = CS0_END; /* CS addressing */
+	mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
+			(txpdll << 9) | (tfaw << 4) | tcl;
+	mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
+			(tras << 16) | (1 << 15) /* trpa */ |
+			(twr << 9) | (tmrd << 5) | tcwl;
+	mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
+	mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
+		       (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
+	mmdc0->mdasp = cs0_end; /* CS addressing */
 
 	/* Step 3: Configure DDR type */
-	reg = (i->cs1_mirror << 19) | (i->walat << 16) | (i->bi_on << 12) |
-	      (i->mif3_mode << 9) | (i->ralat << 6);
-	mmdc0->mdmisc = reg;
+	mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
+			(sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
+			(sysinfo->ralat << 6);
 
 	/* Step 4: Configure delay while leaving reset */
-	reg = (txpr << 16) | (i->sde_to_rst << 8) | (i->rst_to_cke << 0);
-	mmdc0->mdor = reg;
+	mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
+		      (sysinfo->rst_to_cke << 0);
 
 	/* Step 5: Configure DDR physical parameters (density and burst len) */
-	coladdr = m->coladdr;
-	if (m->coladdr == 8)		/* 8-bit COL is 0x3 */
+	coladdr = ddr3_cfg->coladdr;
+	if (ddr3_cfg->coladdr == 8)		/* 8-bit COL is 0x3 */
 		coladdr += 4;
-	else if (m->coladdr == 12)	/* 12-bit COL is 0x4 */
+	else if (ddr3_cfg->coladdr == 12)	/* 12-bit COL is 0x4 */
 		coladdr += 1;
-	reg = (m->rowaddr - 11) << 24 |		/* ROW */
-	      (coladdr - 9) << 20 |		/* COL */
-	      (1 << 19) |			/* Burst Length = 8 for DDR3 */
-	      (i->dsize << 16);			/* DDR data bus size */
-	mmdc0->mdctl = reg;
+	mmdc0->mdctl =  (ddr3_cfg->rowaddr - 11) << 24 |	/* ROW */
+			(coladdr - 9) << 20 |			/* COL */
+			(1 << 19) |		/* Burst Length = 8 for DDR3 */
+			(sysinfo->dsize << 16);		/* DDR data bus size */
 
 	/* Step 6: Perform ZQ calibration */
-	reg = (u32)0xa1390001; /* one-time HW ZQ calib */
-	mmdc0->mpzqhwctrl = reg;
-	if (i->dsize > 1)
-		mmdc1->mpzqhwctrl = reg;
+	val = 0xa1390001; /* one-time HW ZQ calib */
+	mmdc0->mpzqhwctrl = val;
+	if (sysinfo->dsize > 1)
+		mmdc1->mpzqhwctrl = val;
 
 	/* Step 7: Enable MMDC with desired chip select */
-	reg = mmdc0->mdctl |
-	      (1 << 31) |			/* SDE_0 for CS0 */
-	      ((i->ncs == 2) ? 1 : 0) << 30;	/* SDE_1 for CS1 */
-	mmdc0->mdctl = reg;
+	mmdc0->mdctl |= (1 << 31) |			     /* SDE_0 for CS0 */
+			((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
 
 	/* Step 8: Write Mode Registers to Init DDR3 devices */
-	for (cs = 0; cs < i->ncs; cs++) {
+	for (cs = 0; cs < sysinfo->ncs; cs++) {
 		/* MR2 */
-		reg = (i->rtt_wr & 3) << 9 | (m->SRT & 1) << 7 |
+		val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
 		      ((tcwl - 3) & 3) << 3;
-		mmdc0->mdscr = (u32)MR(reg, 2, 3, cs);
+		mmdc0->mdscr = MR(val, 2, 3, cs);
 		/* MR3 */
-		mmdc0->mdscr = (u32)MR(0, 3, 3, cs);
+		mmdc0->mdscr = MR(0, 3, 3, cs);
 		/* MR1 */
-		reg = ((i->rtt_nom & 1) ? 1 : 0) << 2 |
-		      ((i->rtt_nom & 2) ? 1 : 0) << 6;
-		mmdc0->mdscr = (u32)MR(reg, 1, 3, cs);
-		reg = ((tcl - 1) << 4) |	/* CAS */
+		val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
+		      ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
+		mmdc0->mdscr = MR(val, 1, 3, cs);
+		/* MR0 */
+		val = ((tcl - 1) << 4) |	/* CAS */
 		      (1 << 8)   |		/* DLL Reset */
 		      ((twr - 3) << 9);		/* Write Recovery */
-		/* MR0 */
-		mmdc0->mdscr = (u32)MR(reg, 0, 3, cs);
+		mmdc0->mdscr = MR(val, 0, 3, cs);
 		/* ZQ calibration */
-		reg = (1 << 10);
-		mmdc0->mdscr = (u32)MR(reg, 0, 4, cs);
+		val = (1 << 10);
+		mmdc0->mdscr = MR(val, 0, 4, cs);
 	}
 
 	/* Step 10: Power down control and self-refresh */
-	reg = (tcke & 0x7) << 16 |
-	      5            << 12 |  /* PWDT_1: 256 cycles */
-	      5            <<  8 |  /* PWDT_0: 256 cycles */
-	      1            <<  6 |  /* BOTH_CS_PD */
-	      (tcksrx & 0x7) << 3 |
-	      (tcksre & 0x7);
-	mmdc0->mdpdc = reg;
-	mmdc0->mapsr = (u32)0x00011006; /* ADOPT power down enabled */
+	mmdc0->mdpdc = (tcke & 0x7) << 16 |
+			5            << 12 |  /* PWDT_1: 256 cycles */
+			5            <<  8 |  /* PWDT_0: 256 cycles */
+			1            <<  7 |  /* SLOW_PD */
+			1            <<  6 |  /* BOTH_CS_PD */
+			(tcksrx & 0x7) << 3 |
+			(tcksre & 0x7);
+	mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
 
 	/* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
-	mmdc0->mpzqhwctrl = (u32)0xa1390003;
-	if (i->dsize > 1)
-		mmdc1->mpzqhwctrl = (u32)0xa1390003;
+	val = 0xa1390003;
+	mmdc0->mpzqhwctrl = val;
+	if (sysinfo->dsize > 1)
+		mmdc1->mpzqhwctrl = val;
 
 	/* Step 12: Configure and activate periodic refresh */
-	reg = (1 << 14) |	/* REF_SEL: Periodic refresh cycles of 32kHz */
-	      (7 << 11);	/* REFR: Refresh Rate - 8 refreshes */
-	mmdc0->mdref = reg;
+	mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
+		       (7 << 11);  /* REFR: Refresh Rate - 8 refreshes */
 
 	/* Step 13: Deassert config request - init complete */
-	mmdc0->mdscr = (u32)0x00000000;
+	mmdc0->mdscr = 0x00000000;
 
 	/* wait for auto-ZQ calibration to complete */
 	mdelay(1);
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index ac84a1fbfb..ba21cfe580 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -324,10 +324,10 @@ const struct boot_mode soc_boot_modes[] = {
 	/* reserved value should start rom usb */
 	{"usb",		MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
 	{"sata",	MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
-	{"escpi1:0",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
-	{"escpi1:1",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
-	{"escpi1:2",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
-	{"escpi1:3",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
+	{"ecspi1:0",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
+	{"ecspi1:1",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
+	{"ecspi1:2",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
+	{"ecspi1:3",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
 	/* 4 bit bus width */
 	{"esdhc1",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 	{"esdhc2",	MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
@@ -430,6 +430,9 @@ void v7_outer_cache_enable(void)
 	}
 #endif
 
+	/* Must disable the L2 before changing the latency parameters */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
 	writel(0x132, &pl310->pl310_tag_latency_ctrl);
 	writel(0x132, &pl310->pl310_data_latency_ctrl);
 
diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig
new file mode 100644
index 0000000000..34f5496c8c
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/Kconfig
@@ -0,0 +1,32 @@
+menu "Panasonic UniPhier platform"
+	depends on ARCH_UNIPHIER
+
+config SYS_CPU
+	string
+	default "armv7"
+
+config SYS_SOC
+	string
+	default "uniphier"
+
+config SYS_CONFIG_NAME
+	string
+	default "ph1_pro4" if MACH_PH1_PRO4
+	default "ph1_ld4" if MACH_PH1_LD4
+	default "ph1_sld8" if MACH_PH1_SLD8
+
+choice
+	prompt "UniPhier SoC select"
+
+config MACH_PH1_PRO4
+	bool "PH1-Pro4"
+
+config MACH_PH1_LD4
+	bool "PH1-LD4"
+
+config MACH_PH1_SLD8
+	bool "PH1-sLD8"
+
+endchoice
+
+endmenu
diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile
new file mode 100644
index 0000000000..7cedddaadc
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/Makefile
@@ -0,0 +1,23 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_SPL_BUILD) += lowlevel_init.o init_page_table.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
+
+obj-y += timer.o
+obj-y += reset.o
+obj-y += cache_uniphier.o
+obj-y += dram_init.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
+obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
+obj-$(CONFIG_UNIPHIER_SMP) += smp.o
+obj-$(if $(CONFIG_SPL_BUILD),,y) += cmd_pinmon.o
+
+obj-y += board_common.o
+obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
+obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o
+
+obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
+obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/
+obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/
diff --git a/arch/arm/cpu/armv7/uniphier/board_common.c b/arch/arm/cpu/armv7/uniphier/board_common.c
new file mode 100644
index 0000000000..3fb26c6d84
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/board_common.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/led.h>
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	led_write(U, B, O, O);
+
+	return 0;
+}
+
+#if CONFIG_NR_DRAM_BANKS >= 2
+void dram_init_banksize(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE;
+	gd->bd->bi_dram[0].size  = CONFIG_SDRAM0_SIZE;
+	gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE;
+	gd->bd->bi_dram[1].size  = CONFIG_SDRAM1_SIZE;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/uniphier/board_late_init.c b/arch/arm/cpu/armv7/uniphier/board_late_init.c
new file mode 100644
index 0000000000..37300206f6
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/board_late_init.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <../drivers/mtd/nand/denali.h>
+
+static void nand_denali_wp_disable(void)
+{
+#ifdef CONFIG_NAND_DENALI
+	/*
+	 * Since the boot rom enables the write protection for NAND boot mode,
+	 * it must be disabled somewhere for "nand write", "nand erase", etc.
+	 * The workaround is here to not disturb the Denali NAND controller
+	 * driver just for a really SoC-specific thing.
+	 */
+	void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
+
+	writel(WRITE_PROTECT__FLAG, denali_reg + WRITE_PROTECT);
+#endif
+}
+
+static void nand_denali_fixup(void)
+{
+#if defined(CONFIG_NAND_DENALI) && \
+	(defined(CONFIG_MACH_PH1_SLD8) || defined(CONFIG_MACH_PH1_PRO4))
+	/*
+	 * The Denali NAND controller on some of UniPhier SoCs does not
+	 * automatically query the device parameters.  For those SoCs,
+	 * some registers must be set after the device is probed.
+	 */
+	void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
+	struct mtd_info *mtd;
+	struct nand_chip *chip;
+
+	if (nand_curr_device < 0 ||
+	    nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE) {
+		/* NAND was not detected. Just return. */
+		return;
+	}
+
+	mtd = &nand_info[nand_curr_device];
+	chip = mtd->priv;
+
+	writel(mtd->erasesize / mtd->writesize, denali_reg + PAGES_PER_BLOCK);
+	writel(0, denali_reg + DEVICE_WIDTH);
+	writel(mtd->writesize, denali_reg + DEVICE_MAIN_AREA_SIZE);
+	writel(mtd->oobsize, denali_reg + DEVICE_SPARE_AREA_SIZE);
+	writel(1, denali_reg + DEVICES_CONNECTED);
+
+	/*
+	 * chip->scan_bbt in nand_scan_tail() has been skipped.
+	 * It should be done in here.
+	 */
+	chip->scan_bbt(mtd);
+#endif
+}
+
+int board_late_init(void)
+{
+	puts("MODE:  ");
+
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+		printf("eMMC Boot\n");
+		setenv("bootmode", "emmcboot");
+		nand_denali_fixup();
+		break;
+	case BOOT_DEVICE_NAND:
+		printf("NAND Boot\n");
+		setenv("bootmode", "nandboot");
+		nand_denali_wp_disable();
+		break;
+	case BOOT_DEVICE_NOR:
+		printf("NOR Boot\n");
+		setenv("bootmode", "norboot");
+		nand_denali_fixup();
+		break;
+	default:
+		printf("Unsupported Boot Mode\n");
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/uniphier/cache_uniphier.c b/arch/arm/cpu/armv7/uniphier/cache_uniphier.c
new file mode 100644
index 0000000000..e47f977fe5
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/cache_uniphier.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/armv7.h>
+#include <asm/arch/ssc-regs.h>
+
+#ifdef CONFIG_UNIPHIER_L2CACHE_ON
+static void uniphier_cache_maint_all(u32 operation)
+{
+	/* try until the command is successfully set */
+	do {
+		writel(SSCOQM_S_ALL | SSCOQM_CE | operation, SSCOQM);
+	} while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
+
+	/* wait until the operation is completed */
+	while (readl(SSCOLPQS) != SSCOLPQS_EF)
+		;
+
+	/* clear the complete notification flag */
+	writel(SSCOLPQS_EF, SSCOLPQS);
+
+	writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
+	readl(SSCOPE); /* need a read back to confirm */
+}
+
+void v7_outer_cache_flush_all(void)
+{
+	uniphier_cache_maint_all(SSCOQM_CM_WB_INV);
+}
+
+void v7_outer_cache_inval_all(void)
+{
+	uniphier_cache_maint_all(SSCOQM_CM_INV);
+}
+
+static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation)
+{
+	/* try until the command is successfully set */
+	do {
+		writel(SSCOQM_S_ADDRESS | SSCOQM_CE | operation, SSCOQM);
+		writel(start, SSCOQAD);
+		writel(size, SSCOQSZ);
+
+	} while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
+
+	/* wait until the operation is completed */
+	while (readl(SSCOLPQS) != SSCOLPQS_EF)
+		;
+
+	/* clear the complete notification flag */
+	writel(SSCOLPQS_EF, SSCOLPQS);
+}
+
+static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation)
+{
+	u32 size;
+
+	/*
+	 * If start address is not aligned to cache-line,
+	 * do cache operation for the first cache-line
+	 */
+	start = start & ~(SSC_LINE_SIZE - 1);
+
+	if (start == 0 && end >= (u32)(-SSC_LINE_SIZE)) {
+		/* this means cache operation for all range */
+		uniphier_cache_maint_all(operation);
+		return;
+	}
+
+	/*
+	 * If end address is not aligned to cache-line,
+	 * do cache operation for the last cache-line
+	 */
+	size = (end - start + SSC_LINE_SIZE - 1) & ~(SSC_LINE_SIZE - 1);
+
+	while (size) {
+		u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ?
+						SSC_RANGE_OP_MAX_SIZE : size;
+		__uniphier_cache_maint_range(start, chunk_size, operation);
+
+		start += chunk_size;
+		size -= chunk_size;
+	}
+
+	writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
+	readl(SSCOPE); /* need a read back to confirm */
+}
+
+void v7_outer_cache_flush_range(u32 start, u32 end)
+{
+	uniphier_cache_maint_range(start, end, SSCOQM_CM_WB_INV);
+}
+
+void v7_outer_cache_inval_range(u32 start, u32 end)
+{
+	uniphier_cache_maint_range(start, end, SSCOQM_CM_INV);
+}
+
+void v7_outer_cache_enable(void)
+{
+	u32 tmp;
+	tmp = readl(SSCC);
+	tmp |= SSCC_ON;
+	writel(tmp, SSCC);
+}
+#endif
+
+void v7_outer_cache_disable(void)
+{
+	u32 tmp;
+	tmp = readl(SSCC);
+	tmp &= ~SSCC_ON;
+	writel(tmp, SSCC);
+}
+
+void wakeup_secondary(void);
+
+void enable_caches(void)
+{
+	uint32_t reg;
+
+#ifdef CONFIG_UNIPHIER_SMP
+	/*
+	 * The secondary CPU must move to DDR,
+	 * before L2 disable.
+	 * On SPL, the Page Table is located on the L2.
+	 */
+	wakeup_secondary();
+#endif
+	/*
+	 * UniPhier SoCs must use L2 cache for init stack pointer.
+	 * We disable L2 and L1 in this order.
+	 * If CONFIG_SYS_DCACHE_OFF is not defined,
+	 * caches are enabled again with a new page table.
+	 */
+
+	/* L2 disable */
+	v7_outer_cache_disable();
+
+	/* L1 disable */
+	reg = get_cr();
+	reg &= ~(CR_C | CR_M);
+	set_cr(reg);
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+	dcache_enable();
+#endif
+}
diff --git a/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c b/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c
new file mode 100644
index 0000000000..eef9f39840
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/boot-device.h>
+
+static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct boot_device_info *table;
+	u32 mode_sel, n = 0;
+
+	mode_sel = get_boot_mode_sel();
+
+	puts("Boot Mode Pin:\n");
+
+	for (table = boot_device_table; strlen(table->info); table++) {
+		printf(" %c %02x %s\n", n == mode_sel ? '*' : ' ', n,
+		       table->info);
+		n++;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	pinmon,	1,	1,	do_pinmon,
+	"pin monitor",
+	""
+);
diff --git a/arch/arm/cpu/armv7/uniphier/cpu_info.c b/arch/arm/cpu/armv7/uniphier/cpu_info.c
new file mode 100644
index 0000000000..86d079ad56
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/cpu_info.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2013-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sg-regs.h>
+
+int print_cpuinfo(void)
+{
+	u32 revision, type, model, rev, required_model = 1, required_rev = 1;
+
+	revision = readl(SG_REVISION);
+	type = (revision & SG_REVISION_TYPE_MASK) >> SG_REVISION_TYPE_SHIFT;
+	model = (revision & SG_REVISION_MODEL_MASK) >> SG_REVISION_MODEL_SHIFT;
+	rev = (revision & SG_REVISION_REV_MASK) >> SG_REVISION_REV_SHIFT;
+
+	puts("CPU:   ");
+
+	switch (type) {
+	case 0x25:
+		puts("PH1-sLD3 (MN2WS0220)");
+		required_model = 2;
+		break;
+	case 0x26:
+		puts("PH1-LD4 (MN2WS0250)");
+		required_rev = 2;
+		break;
+	case 0x28:
+		puts("PH1-Pro4 (MN2WS0230)");
+		break;
+	case 0x29:
+		puts("PH1-sLD8 (MN2WS0270)");
+		break;
+	default:
+		printf("Unknown Processor ID (0x%x)\n", revision);
+		return -1;
+	}
+
+	if (model > 1)
+		printf(" model %d", model);
+
+	printf(" (rev. %d)\n", rev);
+
+	if (model < required_model) {
+		printf("Sorry, this model is not supported.\n");
+		printf("Required model is %d.", required_model);
+		return -1;
+	} else if (rev < required_rev) {
+		printf("Sorry, this revision is not supported.\n");
+		printf("Required revision is %d.", required_rev);
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/uniphier/dram_init.c b/arch/arm/cpu/armv7/uniphier/dram_init.c
new file mode 100644
index 0000000000..5465a0e6bf
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/dram_init.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/led.h>
+
+int umc_init(void);
+void enable_dpll_ssc(void);
+
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+	led_write(B, 4, , );
+
+	{
+		int res;
+
+		res = umc_init();
+		if (res < 0)
+			return res;
+	}
+	led_write(B, 5, , );
+
+	enable_dpll_ssc();
+#endif
+
+	led_write(B, 6, , );
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/uniphier/init_page_table.c b/arch/arm/cpu/armv7/uniphier/init_page_table.c
new file mode 100644
index 0000000000..d2738350a3
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/init_page_table.c
@@ -0,0 +1,1068 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+/* encoding without TEX remap */
+#define NO_MAP	0x00000000 /* No Map */
+#define DEVICE	0x00002002 /* Non-shareable Device */
+#define NORMAL	0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
+
+#define SSC	NORMAL	/* System Cache: Normal */
+#define EXT	DEVICE	/* External Bus: Device */
+#define REG	DEVICE	/* IO Register: Device */
+#define DDR	DEVICE	/* DDR SDRAM: Device */
+
+#ifdef CONFIG_SPL_BUILD
+#define IS_SPL_TEXT_AREA(x)	((x) == ((CONFIG_SPL_TEXT_BASE) >> 20))
+#else
+#define IS_SPL_TEXT_AREA(x)	((x) == ((CONFIG_SYS_TEXT_BASE) >> 20))
+#endif
+
+#define IS_INIT_STACK_AREA(x)	((x) == ((CONFIG_SYS_INIT_SP_ADDR) >> 20))
+
+#define IS_SSC(x)		((IS_SPL_TEXT_AREA(x)) || \
+					(IS_INIT_STACK_AREA(x)))
+#define IS_EXT(x)		((x) < 0x100)
+#define IS_REG(x)		(0x500 <= (x) && (x) < 0x700)
+#define IS_DDR(x)		(0x800 <= (x) && (x) < 0xf00)
+
+#define MMU_FLAGS(x)		(IS_SSC(x)) ? SSC : \
+					(IS_EXT(x)) ? EXT : \
+						(IS_REG(x)) ? REG : \
+							(IS_DDR(x)) ? DDR : \
+								NO_MAP
+
+#define TBL_ENTRY(x)		(((x) << 20) | (MMU_FLAGS(x)))
+
+const u32 __aligned(PGTABLE_SIZE) init_page_table[PGTABLE_SIZE / sizeof(u32)]
+									= {
+	TBL_ENTRY(0x000), TBL_ENTRY(0x001), TBL_ENTRY(0x002), TBL_ENTRY(0x003),
+	TBL_ENTRY(0x004), TBL_ENTRY(0x005), TBL_ENTRY(0x006), TBL_ENTRY(0x007),
+	TBL_ENTRY(0x008), TBL_ENTRY(0x009), TBL_ENTRY(0x00a), TBL_ENTRY(0x00b),
+	TBL_ENTRY(0x00c), TBL_ENTRY(0x00d), TBL_ENTRY(0x00e), TBL_ENTRY(0x00f),
+	TBL_ENTRY(0x010), TBL_ENTRY(0x011), TBL_ENTRY(0x012), TBL_ENTRY(0x013),
+	TBL_ENTRY(0x014), TBL_ENTRY(0x015), TBL_ENTRY(0x016), TBL_ENTRY(0x017),
+	TBL_ENTRY(0x018), TBL_ENTRY(0x019), TBL_ENTRY(0x01a), TBL_ENTRY(0x01b),
+	TBL_ENTRY(0x01c), TBL_ENTRY(0x01d), TBL_ENTRY(0x01e), TBL_ENTRY(0x01f),
+	TBL_ENTRY(0x020), TBL_ENTRY(0x021), TBL_ENTRY(0x022), TBL_ENTRY(0x023),
+	TBL_ENTRY(0x024), TBL_ENTRY(0x025), TBL_ENTRY(0x026), TBL_ENTRY(0x027),
+	TBL_ENTRY(0x028), TBL_ENTRY(0x029), TBL_ENTRY(0x02a), TBL_ENTRY(0x02b),
+	TBL_ENTRY(0x02c), TBL_ENTRY(0x02d), TBL_ENTRY(0x02e), TBL_ENTRY(0x02f),
+	TBL_ENTRY(0x030), TBL_ENTRY(0x031), TBL_ENTRY(0x032), TBL_ENTRY(0x033),
+	TBL_ENTRY(0x034), TBL_ENTRY(0x035), TBL_ENTRY(0x036), TBL_ENTRY(0x037),
+	TBL_ENTRY(0x038), TBL_ENTRY(0x039), TBL_ENTRY(0x03a), TBL_ENTRY(0x03b),
+	TBL_ENTRY(0x03c), TBL_ENTRY(0x03d), TBL_ENTRY(0x03e), TBL_ENTRY(0x03f),
+	TBL_ENTRY(0x040), TBL_ENTRY(0x041), TBL_ENTRY(0x042), TBL_ENTRY(0x043),
+	TBL_ENTRY(0x044), TBL_ENTRY(0x045), TBL_ENTRY(0x046), TBL_ENTRY(0x047),
+	TBL_ENTRY(0x048), TBL_ENTRY(0x049), TBL_ENTRY(0x04a), TBL_ENTRY(0x04b),
+	TBL_ENTRY(0x04c), TBL_ENTRY(0x04d), TBL_ENTRY(0x04e), TBL_ENTRY(0x04f),
+	TBL_ENTRY(0x050), TBL_ENTRY(0x051), TBL_ENTRY(0x052), TBL_ENTRY(0x053),
+	TBL_ENTRY(0x054), TBL_ENTRY(0x055), TBL_ENTRY(0x056), TBL_ENTRY(0x057),
+	TBL_ENTRY(0x058), TBL_ENTRY(0x059), TBL_ENTRY(0x05a), TBL_ENTRY(0x05b),
+	TBL_ENTRY(0x05c), TBL_ENTRY(0x05d), TBL_ENTRY(0x05e), TBL_ENTRY(0x05f),
+	TBL_ENTRY(0x060), TBL_ENTRY(0x061), TBL_ENTRY(0x062), TBL_ENTRY(0x063),
+	TBL_ENTRY(0x064), TBL_ENTRY(0x065), TBL_ENTRY(0x066), TBL_ENTRY(0x067),
+	TBL_ENTRY(0x068), TBL_ENTRY(0x069), TBL_ENTRY(0x06a), TBL_ENTRY(0x06b),
+	TBL_ENTRY(0x06c), TBL_ENTRY(0x06d), TBL_ENTRY(0x06e), TBL_ENTRY(0x06f),
+	TBL_ENTRY(0x070), TBL_ENTRY(0x071), TBL_ENTRY(0x072), TBL_ENTRY(0x073),
+	TBL_ENTRY(0x074), TBL_ENTRY(0x075), TBL_ENTRY(0x076), TBL_ENTRY(0x077),
+	TBL_ENTRY(0x078), TBL_ENTRY(0x079), TBL_ENTRY(0x07a), TBL_ENTRY(0x07b),
+	TBL_ENTRY(0x07c), TBL_ENTRY(0x07d), TBL_ENTRY(0x07e), TBL_ENTRY(0x07f),
+	TBL_ENTRY(0x080), TBL_ENTRY(0x081), TBL_ENTRY(0x082), TBL_ENTRY(0x083),
+	TBL_ENTRY(0x084), TBL_ENTRY(0x085), TBL_ENTRY(0x086), TBL_ENTRY(0x087),
+	TBL_ENTRY(0x088), TBL_ENTRY(0x089), TBL_ENTRY(0x08a), TBL_ENTRY(0x08b),
+	TBL_ENTRY(0x08c), TBL_ENTRY(0x08d), TBL_ENTRY(0x08e), TBL_ENTRY(0x08f),
+	TBL_ENTRY(0x090), TBL_ENTRY(0x091), TBL_ENTRY(0x092), TBL_ENTRY(0x093),
+	TBL_ENTRY(0x094), TBL_ENTRY(0x095), TBL_ENTRY(0x096), TBL_ENTRY(0x097),
+	TBL_ENTRY(0x098), TBL_ENTRY(0x099), TBL_ENTRY(0x09a), TBL_ENTRY(0x09b),
+	TBL_ENTRY(0x09c), TBL_ENTRY(0x09d), TBL_ENTRY(0x09e), TBL_ENTRY(0x09f),
+	TBL_ENTRY(0x0a0), TBL_ENTRY(0x0a1), TBL_ENTRY(0x0a2), TBL_ENTRY(0x0a3),
+	TBL_ENTRY(0x0a4), TBL_ENTRY(0x0a5), TBL_ENTRY(0x0a6), TBL_ENTRY(0x0a7),
+	TBL_ENTRY(0x0a8), TBL_ENTRY(0x0a9), TBL_ENTRY(0x0aa), TBL_ENTRY(0x0ab),
+	TBL_ENTRY(0x0ac), TBL_ENTRY(0x0ad), TBL_ENTRY(0x0ae), TBL_ENTRY(0x0af),
+	TBL_ENTRY(0x0b0), TBL_ENTRY(0x0b1), TBL_ENTRY(0x0b2), TBL_ENTRY(0x0b3),
+	TBL_ENTRY(0x0b4), TBL_ENTRY(0x0b5), TBL_ENTRY(0x0b6), TBL_ENTRY(0x0b7),
+	TBL_ENTRY(0x0b8), TBL_ENTRY(0x0b9), TBL_ENTRY(0x0ba), TBL_ENTRY(0x0bb),
+	TBL_ENTRY(0x0bc), TBL_ENTRY(0x0bd), TBL_ENTRY(0x0be), TBL_ENTRY(0x0bf),
+	TBL_ENTRY(0x0c0), TBL_ENTRY(0x0c1), TBL_ENTRY(0x0c2), TBL_ENTRY(0x0c3),
+	TBL_ENTRY(0x0c4), TBL_ENTRY(0x0c5), TBL_ENTRY(0x0c6), TBL_ENTRY(0x0c7),
+	TBL_ENTRY(0x0c8), TBL_ENTRY(0x0c9), TBL_ENTRY(0x0ca), TBL_ENTRY(0x0cb),
+	TBL_ENTRY(0x0cc), TBL_ENTRY(0x0cd), TBL_ENTRY(0x0ce), TBL_ENTRY(0x0cf),
+	TBL_ENTRY(0x0d0), TBL_ENTRY(0x0d1), TBL_ENTRY(0x0d2), TBL_ENTRY(0x0d3),
+	TBL_ENTRY(0x0d4), TBL_ENTRY(0x0d5), TBL_ENTRY(0x0d6), TBL_ENTRY(0x0d7),
+	TBL_ENTRY(0x0d8), TBL_ENTRY(0x0d9), TBL_ENTRY(0x0da), TBL_ENTRY(0x0db),
+	TBL_ENTRY(0x0dc), TBL_ENTRY(0x0dd), TBL_ENTRY(0x0de), TBL_ENTRY(0x0df),
+	TBL_ENTRY(0x0e0), TBL_ENTRY(0x0e1), TBL_ENTRY(0x0e2), TBL_ENTRY(0x0e3),
+	TBL_ENTRY(0x0e4), TBL_ENTRY(0x0e5), TBL_ENTRY(0x0e6), TBL_ENTRY(0x0e7),
+	TBL_ENTRY(0x0e8), TBL_ENTRY(0x0e9), TBL_ENTRY(0x0ea), TBL_ENTRY(0x0eb),
+	TBL_ENTRY(0x0ec), TBL_ENTRY(0x0ed), TBL_ENTRY(0x0ee), TBL_ENTRY(0x0ef),
+	TBL_ENTRY(0x0f0), TBL_ENTRY(0x0f1), TBL_ENTRY(0x0f2), TBL_ENTRY(0x0f3),
+	TBL_ENTRY(0x0f4), TBL_ENTRY(0x0f5), TBL_ENTRY(0x0f6), TBL_ENTRY(0x0f7),
+	TBL_ENTRY(0x0f8), TBL_ENTRY(0x0f9), TBL_ENTRY(0x0fa), TBL_ENTRY(0x0fb),
+	TBL_ENTRY(0x0fc), TBL_ENTRY(0x0fd), TBL_ENTRY(0x0fe), TBL_ENTRY(0x0ff),
+	TBL_ENTRY(0x100), TBL_ENTRY(0x101), TBL_ENTRY(0x102), TBL_ENTRY(0x103),
+	TBL_ENTRY(0x104), TBL_ENTRY(0x105), TBL_ENTRY(0x106), TBL_ENTRY(0x107),
+	TBL_ENTRY(0x108), TBL_ENTRY(0x109), TBL_ENTRY(0x10a), TBL_ENTRY(0x10b),
+	TBL_ENTRY(0x10c), TBL_ENTRY(0x10d), TBL_ENTRY(0x10e), TBL_ENTRY(0x10f),
+	TBL_ENTRY(0x110), TBL_ENTRY(0x111), TBL_ENTRY(0x112), TBL_ENTRY(0x113),
+	TBL_ENTRY(0x114), TBL_ENTRY(0x115), TBL_ENTRY(0x116), TBL_ENTRY(0x117),
+	TBL_ENTRY(0x118), TBL_ENTRY(0x119), TBL_ENTRY(0x11a), TBL_ENTRY(0x11b),
+	TBL_ENTRY(0x11c), TBL_ENTRY(0x11d), TBL_ENTRY(0x11e), TBL_ENTRY(0x11f),
+	TBL_ENTRY(0x120), TBL_ENTRY(0x121), TBL_ENTRY(0x122), TBL_ENTRY(0x123),
+	TBL_ENTRY(0x124), TBL_ENTRY(0x125), TBL_ENTRY(0x126), TBL_ENTRY(0x127),
+	TBL_ENTRY(0x128), TBL_ENTRY(0x129), TBL_ENTRY(0x12a), TBL_ENTRY(0x12b),
+	TBL_ENTRY(0x12c), TBL_ENTRY(0x12d), TBL_ENTRY(0x12e), TBL_ENTRY(0x12f),
+	TBL_ENTRY(0x130), TBL_ENTRY(0x131), TBL_ENTRY(0x132), TBL_ENTRY(0x133),
+	TBL_ENTRY(0x134), TBL_ENTRY(0x135), TBL_ENTRY(0x136), TBL_ENTRY(0x137),
+	TBL_ENTRY(0x138), TBL_ENTRY(0x139), TBL_ENTRY(0x13a), TBL_ENTRY(0x13b),
+	TBL_ENTRY(0x13c), TBL_ENTRY(0x13d), TBL_ENTRY(0x13e), TBL_ENTRY(0x13f),
+	TBL_ENTRY(0x140), TBL_ENTRY(0x141), TBL_ENTRY(0x142), TBL_ENTRY(0x143),
+	TBL_ENTRY(0x144), TBL_ENTRY(0x145), TBL_ENTRY(0x146), TBL_ENTRY(0x147),
+	TBL_ENTRY(0x148), TBL_ENTRY(0x149), TBL_ENTRY(0x14a), TBL_ENTRY(0x14b),
+	TBL_ENTRY(0x14c), TBL_ENTRY(0x14d), TBL_ENTRY(0x14e), TBL_ENTRY(0x14f),
+	TBL_ENTRY(0x150), TBL_ENTRY(0x151), TBL_ENTRY(0x152), TBL_ENTRY(0x153),
+	TBL_ENTRY(0x154), TBL_ENTRY(0x155), TBL_ENTRY(0x156), TBL_ENTRY(0x157),
+	TBL_ENTRY(0x158), TBL_ENTRY(0x159), TBL_ENTRY(0x15a), TBL_ENTRY(0x15b),
+	TBL_ENTRY(0x15c), TBL_ENTRY(0x15d), TBL_ENTRY(0x15e), TBL_ENTRY(0x15f),
+	TBL_ENTRY(0x160), TBL_ENTRY(0x161), TBL_ENTRY(0x162), TBL_ENTRY(0x163),
+	TBL_ENTRY(0x164), TBL_ENTRY(0x165), TBL_ENTRY(0x166), TBL_ENTRY(0x167),
+	TBL_ENTRY(0x168), TBL_ENTRY(0x169), TBL_ENTRY(0x16a), TBL_ENTRY(0x16b),
+	TBL_ENTRY(0x16c), TBL_ENTRY(0x16d), TBL_ENTRY(0x16e), TBL_ENTRY(0x16f),
+	TBL_ENTRY(0x170), TBL_ENTRY(0x171), TBL_ENTRY(0x172), TBL_ENTRY(0x173),
+	TBL_ENTRY(0x174), TBL_ENTRY(0x175), TBL_ENTRY(0x176), TBL_ENTRY(0x177),
+	TBL_ENTRY(0x178), TBL_ENTRY(0x179), TBL_ENTRY(0x17a), TBL_ENTRY(0x17b),
+	TBL_ENTRY(0x17c), TBL_ENTRY(0x17d), TBL_ENTRY(0x17e), TBL_ENTRY(0x17f),
+	TBL_ENTRY(0x180), TBL_ENTRY(0x181), TBL_ENTRY(0x182), TBL_ENTRY(0x183),
+	TBL_ENTRY(0x184), TBL_ENTRY(0x185), TBL_ENTRY(0x186), TBL_ENTRY(0x187),
+	TBL_ENTRY(0x188), TBL_ENTRY(0x189), TBL_ENTRY(0x18a), TBL_ENTRY(0x18b),
+	TBL_ENTRY(0x18c), TBL_ENTRY(0x18d), TBL_ENTRY(0x18e), TBL_ENTRY(0x18f),
+	TBL_ENTRY(0x190), TBL_ENTRY(0x191), TBL_ENTRY(0x192), TBL_ENTRY(0x193),
+	TBL_ENTRY(0x194), TBL_ENTRY(0x195), TBL_ENTRY(0x196), TBL_ENTRY(0x197),
+	TBL_ENTRY(0x198), TBL_ENTRY(0x199), TBL_ENTRY(0x19a), TBL_ENTRY(0x19b),
+	TBL_ENTRY(0x19c), TBL_ENTRY(0x19d), TBL_ENTRY(0x19e), TBL_ENTRY(0x19f),
+	TBL_ENTRY(0x1a0), TBL_ENTRY(0x1a1), TBL_ENTRY(0x1a2), TBL_ENTRY(0x1a3),
+	TBL_ENTRY(0x1a4), TBL_ENTRY(0x1a5), TBL_ENTRY(0x1a6), TBL_ENTRY(0x1a7),
+	TBL_ENTRY(0x1a8), TBL_ENTRY(0x1a9), TBL_ENTRY(0x1aa), TBL_ENTRY(0x1ab),
+	TBL_ENTRY(0x1ac), TBL_ENTRY(0x1ad), TBL_ENTRY(0x1ae), TBL_ENTRY(0x1af),
+	TBL_ENTRY(0x1b0), TBL_ENTRY(0x1b1), TBL_ENTRY(0x1b2), TBL_ENTRY(0x1b3),
+	TBL_ENTRY(0x1b4), TBL_ENTRY(0x1b5), TBL_ENTRY(0x1b6), TBL_ENTRY(0x1b7),
+	TBL_ENTRY(0x1b8), TBL_ENTRY(0x1b9), TBL_ENTRY(0x1ba), TBL_ENTRY(0x1bb),
+	TBL_ENTRY(0x1bc), TBL_ENTRY(0x1bd), TBL_ENTRY(0x1be), TBL_ENTRY(0x1bf),
+	TBL_ENTRY(0x1c0), TBL_ENTRY(0x1c1), TBL_ENTRY(0x1c2), TBL_ENTRY(0x1c3),
+	TBL_ENTRY(0x1c4), TBL_ENTRY(0x1c5), TBL_ENTRY(0x1c6), TBL_ENTRY(0x1c7),
+	TBL_ENTRY(0x1c8), TBL_ENTRY(0x1c9), TBL_ENTRY(0x1ca), TBL_ENTRY(0x1cb),
+	TBL_ENTRY(0x1cc), TBL_ENTRY(0x1cd), TBL_ENTRY(0x1ce), TBL_ENTRY(0x1cf),
+	TBL_ENTRY(0x1d0), TBL_ENTRY(0x1d1), TBL_ENTRY(0x1d2), TBL_ENTRY(0x1d3),
+	TBL_ENTRY(0x1d4), TBL_ENTRY(0x1d5), TBL_ENTRY(0x1d6), TBL_ENTRY(0x1d7),
+	TBL_ENTRY(0x1d8), TBL_ENTRY(0x1d9), TBL_ENTRY(0x1da), TBL_ENTRY(0x1db),
+	TBL_ENTRY(0x1dc), TBL_ENTRY(0x1dd), TBL_ENTRY(0x1de), TBL_ENTRY(0x1df),
+	TBL_ENTRY(0x1e0), TBL_ENTRY(0x1e1), TBL_ENTRY(0x1e2), TBL_ENTRY(0x1e3),
+	TBL_ENTRY(0x1e4), TBL_ENTRY(0x1e5), TBL_ENTRY(0x1e6), TBL_ENTRY(0x1e7),
+	TBL_ENTRY(0x1e8), TBL_ENTRY(0x1e9), TBL_ENTRY(0x1ea), TBL_ENTRY(0x1eb),
+	TBL_ENTRY(0x1ec), TBL_ENTRY(0x1ed), TBL_ENTRY(0x1ee), TBL_ENTRY(0x1ef),
+	TBL_ENTRY(0x1f0), TBL_ENTRY(0x1f1), TBL_ENTRY(0x1f2), TBL_ENTRY(0x1f3),
+	TBL_ENTRY(0x1f4), TBL_ENTRY(0x1f5), TBL_ENTRY(0x1f6), TBL_ENTRY(0x1f7),
+	TBL_ENTRY(0x1f8), TBL_ENTRY(0x1f9), TBL_ENTRY(0x1fa), TBL_ENTRY(0x1fb),
+	TBL_ENTRY(0x1fc), TBL_ENTRY(0x1fd), TBL_ENTRY(0x1fe), TBL_ENTRY(0x1ff),
+	TBL_ENTRY(0x200), TBL_ENTRY(0x201), TBL_ENTRY(0x202), TBL_ENTRY(0x203),
+	TBL_ENTRY(0x204), TBL_ENTRY(0x205), TBL_ENTRY(0x206), TBL_ENTRY(0x207),
+	TBL_ENTRY(0x208), TBL_ENTRY(0x209), TBL_ENTRY(0x20a), TBL_ENTRY(0x20b),
+	TBL_ENTRY(0x20c), TBL_ENTRY(0x20d), TBL_ENTRY(0x20e), TBL_ENTRY(0x20f),
+	TBL_ENTRY(0x210), TBL_ENTRY(0x211), TBL_ENTRY(0x212), TBL_ENTRY(0x213),
+	TBL_ENTRY(0x214), TBL_ENTRY(0x215), TBL_ENTRY(0x216), TBL_ENTRY(0x217),
+	TBL_ENTRY(0x218), TBL_ENTRY(0x219), TBL_ENTRY(0x21a), TBL_ENTRY(0x21b),
+	TBL_ENTRY(0x21c), TBL_ENTRY(0x21d), TBL_ENTRY(0x21e), TBL_ENTRY(0x21f),
+	TBL_ENTRY(0x220), TBL_ENTRY(0x221), TBL_ENTRY(0x222), TBL_ENTRY(0x223),
+	TBL_ENTRY(0x224), TBL_ENTRY(0x225), TBL_ENTRY(0x226), TBL_ENTRY(0x227),
+	TBL_ENTRY(0x228), TBL_ENTRY(0x229), TBL_ENTRY(0x22a), TBL_ENTRY(0x22b),
+	TBL_ENTRY(0x22c), TBL_ENTRY(0x22d), TBL_ENTRY(0x22e), TBL_ENTRY(0x22f),
+	TBL_ENTRY(0x230), TBL_ENTRY(0x231), TBL_ENTRY(0x232), TBL_ENTRY(0x233),
+	TBL_ENTRY(0x234), TBL_ENTRY(0x235), TBL_ENTRY(0x236), TBL_ENTRY(0x237),
+	TBL_ENTRY(0x238), TBL_ENTRY(0x239), TBL_ENTRY(0x23a), TBL_ENTRY(0x23b),
+	TBL_ENTRY(0x23c), TBL_ENTRY(0x23d), TBL_ENTRY(0x23e), TBL_ENTRY(0x23f),
+	TBL_ENTRY(0x240), TBL_ENTRY(0x241), TBL_ENTRY(0x242), TBL_ENTRY(0x243),
+	TBL_ENTRY(0x244), TBL_ENTRY(0x245), TBL_ENTRY(0x246), TBL_ENTRY(0x247),
+	TBL_ENTRY(0x248), TBL_ENTRY(0x249), TBL_ENTRY(0x24a), TBL_ENTRY(0x24b),
+	TBL_ENTRY(0x24c), TBL_ENTRY(0x24d), TBL_ENTRY(0x24e), TBL_ENTRY(0x24f),
+	TBL_ENTRY(0x250), TBL_ENTRY(0x251), TBL_ENTRY(0x252), TBL_ENTRY(0x253),
+	TBL_ENTRY(0x254), TBL_ENTRY(0x255), TBL_ENTRY(0x256), TBL_ENTRY(0x257),
+	TBL_ENTRY(0x258), TBL_ENTRY(0x259), TBL_ENTRY(0x25a), TBL_ENTRY(0x25b),
+	TBL_ENTRY(0x25c), TBL_ENTRY(0x25d), TBL_ENTRY(0x25e), TBL_ENTRY(0x25f),
+	TBL_ENTRY(0x260), TBL_ENTRY(0x261), TBL_ENTRY(0x262), TBL_ENTRY(0x263),
+	TBL_ENTRY(0x264), TBL_ENTRY(0x265), TBL_ENTRY(0x266), TBL_ENTRY(0x267),
+	TBL_ENTRY(0x268), TBL_ENTRY(0x269), TBL_ENTRY(0x26a), TBL_ENTRY(0x26b),
+	TBL_ENTRY(0x26c), TBL_ENTRY(0x26d), TBL_ENTRY(0x26e), TBL_ENTRY(0x26f),
+	TBL_ENTRY(0x270), TBL_ENTRY(0x271), TBL_ENTRY(0x272), TBL_ENTRY(0x273),
+	TBL_ENTRY(0x274), TBL_ENTRY(0x275), TBL_ENTRY(0x276), TBL_ENTRY(0x277),
+	TBL_ENTRY(0x278), TBL_ENTRY(0x279), TBL_ENTRY(0x27a), TBL_ENTRY(0x27b),
+	TBL_ENTRY(0x27c), TBL_ENTRY(0x27d), TBL_ENTRY(0x27e), TBL_ENTRY(0x27f),
+	TBL_ENTRY(0x280), TBL_ENTRY(0x281), TBL_ENTRY(0x282), TBL_ENTRY(0x283),
+	TBL_ENTRY(0x284), TBL_ENTRY(0x285), TBL_ENTRY(0x286), TBL_ENTRY(0x287),
+	TBL_ENTRY(0x288), TBL_ENTRY(0x289), TBL_ENTRY(0x28a), TBL_ENTRY(0x28b),
+	TBL_ENTRY(0x28c), TBL_ENTRY(0x28d), TBL_ENTRY(0x28e), TBL_ENTRY(0x28f),
+	TBL_ENTRY(0x290), TBL_ENTRY(0x291), TBL_ENTRY(0x292), TBL_ENTRY(0x293),
+	TBL_ENTRY(0x294), TBL_ENTRY(0x295), TBL_ENTRY(0x296), TBL_ENTRY(0x297),
+	TBL_ENTRY(0x298), TBL_ENTRY(0x299), TBL_ENTRY(0x29a), TBL_ENTRY(0x29b),
+	TBL_ENTRY(0x29c), TBL_ENTRY(0x29d), TBL_ENTRY(0x29e), TBL_ENTRY(0x29f),
+	TBL_ENTRY(0x2a0), TBL_ENTRY(0x2a1), TBL_ENTRY(0x2a2), TBL_ENTRY(0x2a3),
+	TBL_ENTRY(0x2a4), TBL_ENTRY(0x2a5), TBL_ENTRY(0x2a6), TBL_ENTRY(0x2a7),
+	TBL_ENTRY(0x2a8), TBL_ENTRY(0x2a9), TBL_ENTRY(0x2aa), TBL_ENTRY(0x2ab),
+	TBL_ENTRY(0x2ac), TBL_ENTRY(0x2ad), TBL_ENTRY(0x2ae), TBL_ENTRY(0x2af),
+	TBL_ENTRY(0x2b0), TBL_ENTRY(0x2b1), TBL_ENTRY(0x2b2), TBL_ENTRY(0x2b3),
+	TBL_ENTRY(0x2b4), TBL_ENTRY(0x2b5), TBL_ENTRY(0x2b6), TBL_ENTRY(0x2b7),
+	TBL_ENTRY(0x2b8), TBL_ENTRY(0x2b9), TBL_ENTRY(0x2ba), TBL_ENTRY(0x2bb),
+	TBL_ENTRY(0x2bc), TBL_ENTRY(0x2bd), TBL_ENTRY(0x2be), TBL_ENTRY(0x2bf),
+	TBL_ENTRY(0x2c0), TBL_ENTRY(0x2c1), TBL_ENTRY(0x2c2), TBL_ENTRY(0x2c3),
+	TBL_ENTRY(0x2c4), TBL_ENTRY(0x2c5), TBL_ENTRY(0x2c6), TBL_ENTRY(0x2c7),
+	TBL_ENTRY(0x2c8), TBL_ENTRY(0x2c9), TBL_ENTRY(0x2ca), TBL_ENTRY(0x2cb),
+	TBL_ENTRY(0x2cc), TBL_ENTRY(0x2cd), TBL_ENTRY(0x2ce), TBL_ENTRY(0x2cf),
+	TBL_ENTRY(0x2d0), TBL_ENTRY(0x2d1), TBL_ENTRY(0x2d2), TBL_ENTRY(0x2d3),
+	TBL_ENTRY(0x2d4), TBL_ENTRY(0x2d5), TBL_ENTRY(0x2d6), TBL_ENTRY(0x2d7),
+	TBL_ENTRY(0x2d8), TBL_ENTRY(0x2d9), TBL_ENTRY(0x2da), TBL_ENTRY(0x2db),
+	TBL_ENTRY(0x2dc), TBL_ENTRY(0x2dd), TBL_ENTRY(0x2de), TBL_ENTRY(0x2df),
+	TBL_ENTRY(0x2e0), TBL_ENTRY(0x2e1), TBL_ENTRY(0x2e2), TBL_ENTRY(0x2e3),
+	TBL_ENTRY(0x2e4), TBL_ENTRY(0x2e5), TBL_ENTRY(0x2e6), TBL_ENTRY(0x2e7),
+	TBL_ENTRY(0x2e8), TBL_ENTRY(0x2e9), TBL_ENTRY(0x2ea), TBL_ENTRY(0x2eb),
+	TBL_ENTRY(0x2ec), TBL_ENTRY(0x2ed), TBL_ENTRY(0x2ee), TBL_ENTRY(0x2ef),
+	TBL_ENTRY(0x2f0), TBL_ENTRY(0x2f1), TBL_ENTRY(0x2f2), TBL_ENTRY(0x2f3),
+	TBL_ENTRY(0x2f4), TBL_ENTRY(0x2f5), TBL_ENTRY(0x2f6), TBL_ENTRY(0x2f7),
+	TBL_ENTRY(0x2f8), TBL_ENTRY(0x2f9), TBL_ENTRY(0x2fa), TBL_ENTRY(0x2fb),
+	TBL_ENTRY(0x2fc), TBL_ENTRY(0x2fd), TBL_ENTRY(0x2fe), TBL_ENTRY(0x2ff),
+	TBL_ENTRY(0x300), TBL_ENTRY(0x301), TBL_ENTRY(0x302), TBL_ENTRY(0x303),
+	TBL_ENTRY(0x304), TBL_ENTRY(0x305), TBL_ENTRY(0x306), TBL_ENTRY(0x307),
+	TBL_ENTRY(0x308), TBL_ENTRY(0x309), TBL_ENTRY(0x30a), TBL_ENTRY(0x30b),
+	TBL_ENTRY(0x30c), TBL_ENTRY(0x30d), TBL_ENTRY(0x30e), TBL_ENTRY(0x30f),
+	TBL_ENTRY(0x310), TBL_ENTRY(0x311), TBL_ENTRY(0x312), TBL_ENTRY(0x313),
+	TBL_ENTRY(0x314), TBL_ENTRY(0x315), TBL_ENTRY(0x316), TBL_ENTRY(0x317),
+	TBL_ENTRY(0x318), TBL_ENTRY(0x319), TBL_ENTRY(0x31a), TBL_ENTRY(0x31b),
+	TBL_ENTRY(0x31c), TBL_ENTRY(0x31d), TBL_ENTRY(0x31e), TBL_ENTRY(0x31f),
+	TBL_ENTRY(0x320), TBL_ENTRY(0x321), TBL_ENTRY(0x322), TBL_ENTRY(0x323),
+	TBL_ENTRY(0x324), TBL_ENTRY(0x325), TBL_ENTRY(0x326), TBL_ENTRY(0x327),
+	TBL_ENTRY(0x328), TBL_ENTRY(0x329), TBL_ENTRY(0x32a), TBL_ENTRY(0x32b),
+	TBL_ENTRY(0x32c), TBL_ENTRY(0x32d), TBL_ENTRY(0x32e), TBL_ENTRY(0x32f),
+	TBL_ENTRY(0x330), TBL_ENTRY(0x331), TBL_ENTRY(0x332), TBL_ENTRY(0x333),
+	TBL_ENTRY(0x334), TBL_ENTRY(0x335), TBL_ENTRY(0x336), TBL_ENTRY(0x337),
+	TBL_ENTRY(0x338), TBL_ENTRY(0x339), TBL_ENTRY(0x33a), TBL_ENTRY(0x33b),
+	TBL_ENTRY(0x33c), TBL_ENTRY(0x33d), TBL_ENTRY(0x33e), TBL_ENTRY(0x33f),
+	TBL_ENTRY(0x340), TBL_ENTRY(0x341), TBL_ENTRY(0x342), TBL_ENTRY(0x343),
+	TBL_ENTRY(0x344), TBL_ENTRY(0x345), TBL_ENTRY(0x346), TBL_ENTRY(0x347),
+	TBL_ENTRY(0x348), TBL_ENTRY(0x349), TBL_ENTRY(0x34a), TBL_ENTRY(0x34b),
+	TBL_ENTRY(0x34c), TBL_ENTRY(0x34d), TBL_ENTRY(0x34e), TBL_ENTRY(0x34f),
+	TBL_ENTRY(0x350), TBL_ENTRY(0x351), TBL_ENTRY(0x352), TBL_ENTRY(0x353),
+	TBL_ENTRY(0x354), TBL_ENTRY(0x355), TBL_ENTRY(0x356), TBL_ENTRY(0x357),
+	TBL_ENTRY(0x358), TBL_ENTRY(0x359), TBL_ENTRY(0x35a), TBL_ENTRY(0x35b),
+	TBL_ENTRY(0x35c), TBL_ENTRY(0x35d), TBL_ENTRY(0x35e), TBL_ENTRY(0x35f),
+	TBL_ENTRY(0x360), TBL_ENTRY(0x361), TBL_ENTRY(0x362), TBL_ENTRY(0x363),
+	TBL_ENTRY(0x364), TBL_ENTRY(0x365), TBL_ENTRY(0x366), TBL_ENTRY(0x367),
+	TBL_ENTRY(0x368), TBL_ENTRY(0x369), TBL_ENTRY(0x36a), TBL_ENTRY(0x36b),
+	TBL_ENTRY(0x36c), TBL_ENTRY(0x36d), TBL_ENTRY(0x36e), TBL_ENTRY(0x36f),
+	TBL_ENTRY(0x370), TBL_ENTRY(0x371), TBL_ENTRY(0x372), TBL_ENTRY(0x373),
+	TBL_ENTRY(0x374), TBL_ENTRY(0x375), TBL_ENTRY(0x376), TBL_ENTRY(0x377),
+	TBL_ENTRY(0x378), TBL_ENTRY(0x379), TBL_ENTRY(0x37a), TBL_ENTRY(0x37b),
+	TBL_ENTRY(0x37c), TBL_ENTRY(0x37d), TBL_ENTRY(0x37e), TBL_ENTRY(0x37f),
+	TBL_ENTRY(0x380), TBL_ENTRY(0x381), TBL_ENTRY(0x382), TBL_ENTRY(0x383),
+	TBL_ENTRY(0x384), TBL_ENTRY(0x385), TBL_ENTRY(0x386), TBL_ENTRY(0x387),
+	TBL_ENTRY(0x388), TBL_ENTRY(0x389), TBL_ENTRY(0x38a), TBL_ENTRY(0x38b),
+	TBL_ENTRY(0x38c), TBL_ENTRY(0x38d), TBL_ENTRY(0x38e), TBL_ENTRY(0x38f),
+	TBL_ENTRY(0x390), TBL_ENTRY(0x391), TBL_ENTRY(0x392), TBL_ENTRY(0x393),
+	TBL_ENTRY(0x394), TBL_ENTRY(0x395), TBL_ENTRY(0x396), TBL_ENTRY(0x397),
+	TBL_ENTRY(0x398), TBL_ENTRY(0x399), TBL_ENTRY(0x39a), TBL_ENTRY(0x39b),
+	TBL_ENTRY(0x39c), TBL_ENTRY(0x39d), TBL_ENTRY(0x39e), TBL_ENTRY(0x39f),
+	TBL_ENTRY(0x3a0), TBL_ENTRY(0x3a1), TBL_ENTRY(0x3a2), TBL_ENTRY(0x3a3),
+	TBL_ENTRY(0x3a4), TBL_ENTRY(0x3a5), TBL_ENTRY(0x3a6), TBL_ENTRY(0x3a7),
+	TBL_ENTRY(0x3a8), TBL_ENTRY(0x3a9), TBL_ENTRY(0x3aa), TBL_ENTRY(0x3ab),
+	TBL_ENTRY(0x3ac), TBL_ENTRY(0x3ad), TBL_ENTRY(0x3ae), TBL_ENTRY(0x3af),
+	TBL_ENTRY(0x3b0), TBL_ENTRY(0x3b1), TBL_ENTRY(0x3b2), TBL_ENTRY(0x3b3),
+	TBL_ENTRY(0x3b4), TBL_ENTRY(0x3b5), TBL_ENTRY(0x3b6), TBL_ENTRY(0x3b7),
+	TBL_ENTRY(0x3b8), TBL_ENTRY(0x3b9), TBL_ENTRY(0x3ba), TBL_ENTRY(0x3bb),
+	TBL_ENTRY(0x3bc), TBL_ENTRY(0x3bd), TBL_ENTRY(0x3be), TBL_ENTRY(0x3bf),
+	TBL_ENTRY(0x3c0), TBL_ENTRY(0x3c1), TBL_ENTRY(0x3c2), TBL_ENTRY(0x3c3),
+	TBL_ENTRY(0x3c4), TBL_ENTRY(0x3c5), TBL_ENTRY(0x3c6), TBL_ENTRY(0x3c7),
+	TBL_ENTRY(0x3c8), TBL_ENTRY(0x3c9), TBL_ENTRY(0x3ca), TBL_ENTRY(0x3cb),
+	TBL_ENTRY(0x3cc), TBL_ENTRY(0x3cd), TBL_ENTRY(0x3ce), TBL_ENTRY(0x3cf),
+	TBL_ENTRY(0x3d0), TBL_ENTRY(0x3d1), TBL_ENTRY(0x3d2), TBL_ENTRY(0x3d3),
+	TBL_ENTRY(0x3d4), TBL_ENTRY(0x3d5), TBL_ENTRY(0x3d6), TBL_ENTRY(0x3d7),
+	TBL_ENTRY(0x3d8), TBL_ENTRY(0x3d9), TBL_ENTRY(0x3da), TBL_ENTRY(0x3db),
+	TBL_ENTRY(0x3dc), TBL_ENTRY(0x3dd), TBL_ENTRY(0x3de), TBL_ENTRY(0x3df),
+	TBL_ENTRY(0x3e0), TBL_ENTRY(0x3e1), TBL_ENTRY(0x3e2), TBL_ENTRY(0x3e3),
+	TBL_ENTRY(0x3e4), TBL_ENTRY(0x3e5), TBL_ENTRY(0x3e6), TBL_ENTRY(0x3e7),
+	TBL_ENTRY(0x3e8), TBL_ENTRY(0x3e9), TBL_ENTRY(0x3ea), TBL_ENTRY(0x3eb),
+	TBL_ENTRY(0x3ec), TBL_ENTRY(0x3ed), TBL_ENTRY(0x3ee), TBL_ENTRY(0x3ef),
+	TBL_ENTRY(0x3f0), TBL_ENTRY(0x3f1), TBL_ENTRY(0x3f2), TBL_ENTRY(0x3f3),
+	TBL_ENTRY(0x3f4), TBL_ENTRY(0x3f5), TBL_ENTRY(0x3f6), TBL_ENTRY(0x3f7),
+	TBL_ENTRY(0x3f8), TBL_ENTRY(0x3f9), TBL_ENTRY(0x3fa), TBL_ENTRY(0x3fb),
+	TBL_ENTRY(0x3fc), TBL_ENTRY(0x3fd), TBL_ENTRY(0x3fe), TBL_ENTRY(0x3ff),
+	TBL_ENTRY(0x400), TBL_ENTRY(0x401), TBL_ENTRY(0x402), TBL_ENTRY(0x403),
+	TBL_ENTRY(0x404), TBL_ENTRY(0x405), TBL_ENTRY(0x406), TBL_ENTRY(0x407),
+	TBL_ENTRY(0x408), TBL_ENTRY(0x409), TBL_ENTRY(0x40a), TBL_ENTRY(0x40b),
+	TBL_ENTRY(0x40c), TBL_ENTRY(0x40d), TBL_ENTRY(0x40e), TBL_ENTRY(0x40f),
+	TBL_ENTRY(0x410), TBL_ENTRY(0x411), TBL_ENTRY(0x412), TBL_ENTRY(0x413),
+	TBL_ENTRY(0x414), TBL_ENTRY(0x415), TBL_ENTRY(0x416), TBL_ENTRY(0x417),
+	TBL_ENTRY(0x418), TBL_ENTRY(0x419), TBL_ENTRY(0x41a), TBL_ENTRY(0x41b),
+	TBL_ENTRY(0x41c), TBL_ENTRY(0x41d), TBL_ENTRY(0x41e), TBL_ENTRY(0x41f),
+	TBL_ENTRY(0x420), TBL_ENTRY(0x421), TBL_ENTRY(0x422), TBL_ENTRY(0x423),
+	TBL_ENTRY(0x424), TBL_ENTRY(0x425), TBL_ENTRY(0x426), TBL_ENTRY(0x427),
+	TBL_ENTRY(0x428), TBL_ENTRY(0x429), TBL_ENTRY(0x42a), TBL_ENTRY(0x42b),
+	TBL_ENTRY(0x42c), TBL_ENTRY(0x42d), TBL_ENTRY(0x42e), TBL_ENTRY(0x42f),
+	TBL_ENTRY(0x430), TBL_ENTRY(0x431), TBL_ENTRY(0x432), TBL_ENTRY(0x433),
+	TBL_ENTRY(0x434), TBL_ENTRY(0x435), TBL_ENTRY(0x436), TBL_ENTRY(0x437),
+	TBL_ENTRY(0x438), TBL_ENTRY(0x439), TBL_ENTRY(0x43a), TBL_ENTRY(0x43b),
+	TBL_ENTRY(0x43c), TBL_ENTRY(0x43d), TBL_ENTRY(0x43e), TBL_ENTRY(0x43f),
+	TBL_ENTRY(0x440), TBL_ENTRY(0x441), TBL_ENTRY(0x442), TBL_ENTRY(0x443),
+	TBL_ENTRY(0x444), TBL_ENTRY(0x445), TBL_ENTRY(0x446), TBL_ENTRY(0x447),
+	TBL_ENTRY(0x448), TBL_ENTRY(0x449), TBL_ENTRY(0x44a), TBL_ENTRY(0x44b),
+	TBL_ENTRY(0x44c), TBL_ENTRY(0x44d), TBL_ENTRY(0x44e), TBL_ENTRY(0x44f),
+	TBL_ENTRY(0x450), TBL_ENTRY(0x451), TBL_ENTRY(0x452), TBL_ENTRY(0x453),
+	TBL_ENTRY(0x454), TBL_ENTRY(0x455), TBL_ENTRY(0x456), TBL_ENTRY(0x457),
+	TBL_ENTRY(0x458), TBL_ENTRY(0x459), TBL_ENTRY(0x45a), TBL_ENTRY(0x45b),
+	TBL_ENTRY(0x45c), TBL_ENTRY(0x45d), TBL_ENTRY(0x45e), TBL_ENTRY(0x45f),
+	TBL_ENTRY(0x460), TBL_ENTRY(0x461), TBL_ENTRY(0x462), TBL_ENTRY(0x463),
+	TBL_ENTRY(0x464), TBL_ENTRY(0x465), TBL_ENTRY(0x466), TBL_ENTRY(0x467),
+	TBL_ENTRY(0x468), TBL_ENTRY(0x469), TBL_ENTRY(0x46a), TBL_ENTRY(0x46b),
+	TBL_ENTRY(0x46c), TBL_ENTRY(0x46d), TBL_ENTRY(0x46e), TBL_ENTRY(0x46f),
+	TBL_ENTRY(0x470), TBL_ENTRY(0x471), TBL_ENTRY(0x472), TBL_ENTRY(0x473),
+	TBL_ENTRY(0x474), TBL_ENTRY(0x475), TBL_ENTRY(0x476), TBL_ENTRY(0x477),
+	TBL_ENTRY(0x478), TBL_ENTRY(0x479), TBL_ENTRY(0x47a), TBL_ENTRY(0x47b),
+	TBL_ENTRY(0x47c), TBL_ENTRY(0x47d), TBL_ENTRY(0x47e), TBL_ENTRY(0x47f),
+	TBL_ENTRY(0x480), TBL_ENTRY(0x481), TBL_ENTRY(0x482), TBL_ENTRY(0x483),
+	TBL_ENTRY(0x484), TBL_ENTRY(0x485), TBL_ENTRY(0x486), TBL_ENTRY(0x487),
+	TBL_ENTRY(0x488), TBL_ENTRY(0x489), TBL_ENTRY(0x48a), TBL_ENTRY(0x48b),
+	TBL_ENTRY(0x48c), TBL_ENTRY(0x48d), TBL_ENTRY(0x48e), TBL_ENTRY(0x48f),
+	TBL_ENTRY(0x490), TBL_ENTRY(0x491), TBL_ENTRY(0x492), TBL_ENTRY(0x493),
+	TBL_ENTRY(0x494), TBL_ENTRY(0x495), TBL_ENTRY(0x496), TBL_ENTRY(0x497),
+	TBL_ENTRY(0x498), TBL_ENTRY(0x499), TBL_ENTRY(0x49a), TBL_ENTRY(0x49b),
+	TBL_ENTRY(0x49c), TBL_ENTRY(0x49d), TBL_ENTRY(0x49e), TBL_ENTRY(0x49f),
+	TBL_ENTRY(0x4a0), TBL_ENTRY(0x4a1), TBL_ENTRY(0x4a2), TBL_ENTRY(0x4a3),
+	TBL_ENTRY(0x4a4), TBL_ENTRY(0x4a5), TBL_ENTRY(0x4a6), TBL_ENTRY(0x4a7),
+	TBL_ENTRY(0x4a8), TBL_ENTRY(0x4a9), TBL_ENTRY(0x4aa), TBL_ENTRY(0x4ab),
+	TBL_ENTRY(0x4ac), TBL_ENTRY(0x4ad), TBL_ENTRY(0x4ae), TBL_ENTRY(0x4af),
+	TBL_ENTRY(0x4b0), TBL_ENTRY(0x4b1), TBL_ENTRY(0x4b2), TBL_ENTRY(0x4b3),
+	TBL_ENTRY(0x4b4), TBL_ENTRY(0x4b5), TBL_ENTRY(0x4b6), TBL_ENTRY(0x4b7),
+	TBL_ENTRY(0x4b8), TBL_ENTRY(0x4b9), TBL_ENTRY(0x4ba), TBL_ENTRY(0x4bb),
+	TBL_ENTRY(0x4bc), TBL_ENTRY(0x4bd), TBL_ENTRY(0x4be), TBL_ENTRY(0x4bf),
+	TBL_ENTRY(0x4c0), TBL_ENTRY(0x4c1), TBL_ENTRY(0x4c2), TBL_ENTRY(0x4c3),
+	TBL_ENTRY(0x4c4), TBL_ENTRY(0x4c5), TBL_ENTRY(0x4c6), TBL_ENTRY(0x4c7),
+	TBL_ENTRY(0x4c8), TBL_ENTRY(0x4c9), TBL_ENTRY(0x4ca), TBL_ENTRY(0x4cb),
+	TBL_ENTRY(0x4cc), TBL_ENTRY(0x4cd), TBL_ENTRY(0x4ce), TBL_ENTRY(0x4cf),
+	TBL_ENTRY(0x4d0), TBL_ENTRY(0x4d1), TBL_ENTRY(0x4d2), TBL_ENTRY(0x4d3),
+	TBL_ENTRY(0x4d4), TBL_ENTRY(0x4d5), TBL_ENTRY(0x4d6), TBL_ENTRY(0x4d7),
+	TBL_ENTRY(0x4d8), TBL_ENTRY(0x4d9), TBL_ENTRY(0x4da), TBL_ENTRY(0x4db),
+	TBL_ENTRY(0x4dc), TBL_ENTRY(0x4dd), TBL_ENTRY(0x4de), TBL_ENTRY(0x4df),
+	TBL_ENTRY(0x4e0), TBL_ENTRY(0x4e1), TBL_ENTRY(0x4e2), TBL_ENTRY(0x4e3),
+	TBL_ENTRY(0x4e4), TBL_ENTRY(0x4e5), TBL_ENTRY(0x4e6), TBL_ENTRY(0x4e7),
+	TBL_ENTRY(0x4e8), TBL_ENTRY(0x4e9), TBL_ENTRY(0x4ea), TBL_ENTRY(0x4eb),
+	TBL_ENTRY(0x4ec), TBL_ENTRY(0x4ed), TBL_ENTRY(0x4ee), TBL_ENTRY(0x4ef),
+	TBL_ENTRY(0x4f0), TBL_ENTRY(0x4f1), TBL_ENTRY(0x4f2), TBL_ENTRY(0x4f3),
+	TBL_ENTRY(0x4f4), TBL_ENTRY(0x4f5), TBL_ENTRY(0x4f6), TBL_ENTRY(0x4f7),
+	TBL_ENTRY(0x4f8), TBL_ENTRY(0x4f9), TBL_ENTRY(0x4fa), TBL_ENTRY(0x4fb),
+	TBL_ENTRY(0x4fc), TBL_ENTRY(0x4fd), TBL_ENTRY(0x4fe), TBL_ENTRY(0x4ff),
+	TBL_ENTRY(0x500), TBL_ENTRY(0x501), TBL_ENTRY(0x502), TBL_ENTRY(0x503),
+	TBL_ENTRY(0x504), TBL_ENTRY(0x505), TBL_ENTRY(0x506), TBL_ENTRY(0x507),
+	TBL_ENTRY(0x508), TBL_ENTRY(0x509), TBL_ENTRY(0x50a), TBL_ENTRY(0x50b),
+	TBL_ENTRY(0x50c), TBL_ENTRY(0x50d), TBL_ENTRY(0x50e), TBL_ENTRY(0x50f),
+	TBL_ENTRY(0x510), TBL_ENTRY(0x511), TBL_ENTRY(0x512), TBL_ENTRY(0x513),
+	TBL_ENTRY(0x514), TBL_ENTRY(0x515), TBL_ENTRY(0x516), TBL_ENTRY(0x517),
+	TBL_ENTRY(0x518), TBL_ENTRY(0x519), TBL_ENTRY(0x51a), TBL_ENTRY(0x51b),
+	TBL_ENTRY(0x51c), TBL_ENTRY(0x51d), TBL_ENTRY(0x51e), TBL_ENTRY(0x51f),
+	TBL_ENTRY(0x520), TBL_ENTRY(0x521), TBL_ENTRY(0x522), TBL_ENTRY(0x523),
+	TBL_ENTRY(0x524), TBL_ENTRY(0x525), TBL_ENTRY(0x526), TBL_ENTRY(0x527),
+	TBL_ENTRY(0x528), TBL_ENTRY(0x529), TBL_ENTRY(0x52a), TBL_ENTRY(0x52b),
+	TBL_ENTRY(0x52c), TBL_ENTRY(0x52d), TBL_ENTRY(0x52e), TBL_ENTRY(0x52f),
+	TBL_ENTRY(0x530), TBL_ENTRY(0x531), TBL_ENTRY(0x532), TBL_ENTRY(0x533),
+	TBL_ENTRY(0x534), TBL_ENTRY(0x535), TBL_ENTRY(0x536), TBL_ENTRY(0x537),
+	TBL_ENTRY(0x538), TBL_ENTRY(0x539), TBL_ENTRY(0x53a), TBL_ENTRY(0x53b),
+	TBL_ENTRY(0x53c), TBL_ENTRY(0x53d), TBL_ENTRY(0x53e), TBL_ENTRY(0x53f),
+	TBL_ENTRY(0x540), TBL_ENTRY(0x541), TBL_ENTRY(0x542), TBL_ENTRY(0x543),
+	TBL_ENTRY(0x544), TBL_ENTRY(0x545), TBL_ENTRY(0x546), TBL_ENTRY(0x547),
+	TBL_ENTRY(0x548), TBL_ENTRY(0x549), TBL_ENTRY(0x54a), TBL_ENTRY(0x54b),
+	TBL_ENTRY(0x54c), TBL_ENTRY(0x54d), TBL_ENTRY(0x54e), TBL_ENTRY(0x54f),
+	TBL_ENTRY(0x550), TBL_ENTRY(0x551), TBL_ENTRY(0x552), TBL_ENTRY(0x553),
+	TBL_ENTRY(0x554), TBL_ENTRY(0x555), TBL_ENTRY(0x556), TBL_ENTRY(0x557),
+	TBL_ENTRY(0x558), TBL_ENTRY(0x559), TBL_ENTRY(0x55a), TBL_ENTRY(0x55b),
+	TBL_ENTRY(0x55c), TBL_ENTRY(0x55d), TBL_ENTRY(0x55e), TBL_ENTRY(0x55f),
+	TBL_ENTRY(0x560), TBL_ENTRY(0x561), TBL_ENTRY(0x562), TBL_ENTRY(0x563),
+	TBL_ENTRY(0x564), TBL_ENTRY(0x565), TBL_ENTRY(0x566), TBL_ENTRY(0x567),
+	TBL_ENTRY(0x568), TBL_ENTRY(0x569), TBL_ENTRY(0x56a), TBL_ENTRY(0x56b),
+	TBL_ENTRY(0x56c), TBL_ENTRY(0x56d), TBL_ENTRY(0x56e), TBL_ENTRY(0x56f),
+	TBL_ENTRY(0x570), TBL_ENTRY(0x571), TBL_ENTRY(0x572), TBL_ENTRY(0x573),
+	TBL_ENTRY(0x574), TBL_ENTRY(0x575), TBL_ENTRY(0x576), TBL_ENTRY(0x577),
+	TBL_ENTRY(0x578), TBL_ENTRY(0x579), TBL_ENTRY(0x57a), TBL_ENTRY(0x57b),
+	TBL_ENTRY(0x57c), TBL_ENTRY(0x57d), TBL_ENTRY(0x57e), TBL_ENTRY(0x57f),
+	TBL_ENTRY(0x580), TBL_ENTRY(0x581), TBL_ENTRY(0x582), TBL_ENTRY(0x583),
+	TBL_ENTRY(0x584), TBL_ENTRY(0x585), TBL_ENTRY(0x586), TBL_ENTRY(0x587),
+	TBL_ENTRY(0x588), TBL_ENTRY(0x589), TBL_ENTRY(0x58a), TBL_ENTRY(0x58b),
+	TBL_ENTRY(0x58c), TBL_ENTRY(0x58d), TBL_ENTRY(0x58e), TBL_ENTRY(0x58f),
+	TBL_ENTRY(0x590), TBL_ENTRY(0x591), TBL_ENTRY(0x592), TBL_ENTRY(0x593),
+	TBL_ENTRY(0x594), TBL_ENTRY(0x595), TBL_ENTRY(0x596), TBL_ENTRY(0x597),
+	TBL_ENTRY(0x598), TBL_ENTRY(0x599), TBL_ENTRY(0x59a), TBL_ENTRY(0x59b),
+	TBL_ENTRY(0x59c), TBL_ENTRY(0x59d), TBL_ENTRY(0x59e), TBL_ENTRY(0x59f),
+	TBL_ENTRY(0x5a0), TBL_ENTRY(0x5a1), TBL_ENTRY(0x5a2), TBL_ENTRY(0x5a3),
+	TBL_ENTRY(0x5a4), TBL_ENTRY(0x5a5), TBL_ENTRY(0x5a6), TBL_ENTRY(0x5a7),
+	TBL_ENTRY(0x5a8), TBL_ENTRY(0x5a9), TBL_ENTRY(0x5aa), TBL_ENTRY(0x5ab),
+	TBL_ENTRY(0x5ac), TBL_ENTRY(0x5ad), TBL_ENTRY(0x5ae), TBL_ENTRY(0x5af),
+	TBL_ENTRY(0x5b0), TBL_ENTRY(0x5b1), TBL_ENTRY(0x5b2), TBL_ENTRY(0x5b3),
+	TBL_ENTRY(0x5b4), TBL_ENTRY(0x5b5), TBL_ENTRY(0x5b6), TBL_ENTRY(0x5b7),
+	TBL_ENTRY(0x5b8), TBL_ENTRY(0x5b9), TBL_ENTRY(0x5ba), TBL_ENTRY(0x5bb),
+	TBL_ENTRY(0x5bc), TBL_ENTRY(0x5bd), TBL_ENTRY(0x5be), TBL_ENTRY(0x5bf),
+	TBL_ENTRY(0x5c0), TBL_ENTRY(0x5c1), TBL_ENTRY(0x5c2), TBL_ENTRY(0x5c3),
+	TBL_ENTRY(0x5c4), TBL_ENTRY(0x5c5), TBL_ENTRY(0x5c6), TBL_ENTRY(0x5c7),
+	TBL_ENTRY(0x5c8), TBL_ENTRY(0x5c9), TBL_ENTRY(0x5ca), TBL_ENTRY(0x5cb),
+	TBL_ENTRY(0x5cc), TBL_ENTRY(0x5cd), TBL_ENTRY(0x5ce), TBL_ENTRY(0x5cf),
+	TBL_ENTRY(0x5d0), TBL_ENTRY(0x5d1), TBL_ENTRY(0x5d2), TBL_ENTRY(0x5d3),
+	TBL_ENTRY(0x5d4), TBL_ENTRY(0x5d5), TBL_ENTRY(0x5d6), TBL_ENTRY(0x5d7),
+	TBL_ENTRY(0x5d8), TBL_ENTRY(0x5d9), TBL_ENTRY(0x5da), TBL_ENTRY(0x5db),
+	TBL_ENTRY(0x5dc), TBL_ENTRY(0x5dd), TBL_ENTRY(0x5de), TBL_ENTRY(0x5df),
+	TBL_ENTRY(0x5e0), TBL_ENTRY(0x5e1), TBL_ENTRY(0x5e2), TBL_ENTRY(0x5e3),
+	TBL_ENTRY(0x5e4), TBL_ENTRY(0x5e5), TBL_ENTRY(0x5e6), TBL_ENTRY(0x5e7),
+	TBL_ENTRY(0x5e8), TBL_ENTRY(0x5e9), TBL_ENTRY(0x5ea), TBL_ENTRY(0x5eb),
+	TBL_ENTRY(0x5ec), TBL_ENTRY(0x5ed), TBL_ENTRY(0x5ee), TBL_ENTRY(0x5ef),
+	TBL_ENTRY(0x5f0), TBL_ENTRY(0x5f1), TBL_ENTRY(0x5f2), TBL_ENTRY(0x5f3),
+	TBL_ENTRY(0x5f4), TBL_ENTRY(0x5f5), TBL_ENTRY(0x5f6), TBL_ENTRY(0x5f7),
+	TBL_ENTRY(0x5f8), TBL_ENTRY(0x5f9), TBL_ENTRY(0x5fa), TBL_ENTRY(0x5fb),
+	TBL_ENTRY(0x5fc), TBL_ENTRY(0x5fd), TBL_ENTRY(0x5fe), TBL_ENTRY(0x5ff),
+	TBL_ENTRY(0x600), TBL_ENTRY(0x601), TBL_ENTRY(0x602), TBL_ENTRY(0x603),
+	TBL_ENTRY(0x604), TBL_ENTRY(0x605), TBL_ENTRY(0x606), TBL_ENTRY(0x607),
+	TBL_ENTRY(0x608), TBL_ENTRY(0x609), TBL_ENTRY(0x60a), TBL_ENTRY(0x60b),
+	TBL_ENTRY(0x60c), TBL_ENTRY(0x60d), TBL_ENTRY(0x60e), TBL_ENTRY(0x60f),
+	TBL_ENTRY(0x610), TBL_ENTRY(0x611), TBL_ENTRY(0x612), TBL_ENTRY(0x613),
+	TBL_ENTRY(0x614), TBL_ENTRY(0x615), TBL_ENTRY(0x616), TBL_ENTRY(0x617),
+	TBL_ENTRY(0x618), TBL_ENTRY(0x619), TBL_ENTRY(0x61a), TBL_ENTRY(0x61b),
+	TBL_ENTRY(0x61c), TBL_ENTRY(0x61d), TBL_ENTRY(0x61e), TBL_ENTRY(0x61f),
+	TBL_ENTRY(0x620), TBL_ENTRY(0x621), TBL_ENTRY(0x622), TBL_ENTRY(0x623),
+	TBL_ENTRY(0x624), TBL_ENTRY(0x625), TBL_ENTRY(0x626), TBL_ENTRY(0x627),
+	TBL_ENTRY(0x628), TBL_ENTRY(0x629), TBL_ENTRY(0x62a), TBL_ENTRY(0x62b),
+	TBL_ENTRY(0x62c), TBL_ENTRY(0x62d), TBL_ENTRY(0x62e), TBL_ENTRY(0x62f),
+	TBL_ENTRY(0x630), TBL_ENTRY(0x631), TBL_ENTRY(0x632), TBL_ENTRY(0x633),
+	TBL_ENTRY(0x634), TBL_ENTRY(0x635), TBL_ENTRY(0x636), TBL_ENTRY(0x637),
+	TBL_ENTRY(0x638), TBL_ENTRY(0x639), TBL_ENTRY(0x63a), TBL_ENTRY(0x63b),
+	TBL_ENTRY(0x63c), TBL_ENTRY(0x63d), TBL_ENTRY(0x63e), TBL_ENTRY(0x63f),
+	TBL_ENTRY(0x640), TBL_ENTRY(0x641), TBL_ENTRY(0x642), TBL_ENTRY(0x643),
+	TBL_ENTRY(0x644), TBL_ENTRY(0x645), TBL_ENTRY(0x646), TBL_ENTRY(0x647),
+	TBL_ENTRY(0x648), TBL_ENTRY(0x649), TBL_ENTRY(0x64a), TBL_ENTRY(0x64b),
+	TBL_ENTRY(0x64c), TBL_ENTRY(0x64d), TBL_ENTRY(0x64e), TBL_ENTRY(0x64f),
+	TBL_ENTRY(0x650), TBL_ENTRY(0x651), TBL_ENTRY(0x652), TBL_ENTRY(0x653),
+	TBL_ENTRY(0x654), TBL_ENTRY(0x655), TBL_ENTRY(0x656), TBL_ENTRY(0x657),
+	TBL_ENTRY(0x658), TBL_ENTRY(0x659), TBL_ENTRY(0x65a), TBL_ENTRY(0x65b),
+	TBL_ENTRY(0x65c), TBL_ENTRY(0x65d), TBL_ENTRY(0x65e), TBL_ENTRY(0x65f),
+	TBL_ENTRY(0x660), TBL_ENTRY(0x661), TBL_ENTRY(0x662), TBL_ENTRY(0x663),
+	TBL_ENTRY(0x664), TBL_ENTRY(0x665), TBL_ENTRY(0x666), TBL_ENTRY(0x667),
+	TBL_ENTRY(0x668), TBL_ENTRY(0x669), TBL_ENTRY(0x66a), TBL_ENTRY(0x66b),
+	TBL_ENTRY(0x66c), TBL_ENTRY(0x66d), TBL_ENTRY(0x66e), TBL_ENTRY(0x66f),
+	TBL_ENTRY(0x670), TBL_ENTRY(0x671), TBL_ENTRY(0x672), TBL_ENTRY(0x673),
+	TBL_ENTRY(0x674), TBL_ENTRY(0x675), TBL_ENTRY(0x676), TBL_ENTRY(0x677),
+	TBL_ENTRY(0x678), TBL_ENTRY(0x679), TBL_ENTRY(0x67a), TBL_ENTRY(0x67b),
+	TBL_ENTRY(0x67c), TBL_ENTRY(0x67d), TBL_ENTRY(0x67e), TBL_ENTRY(0x67f),
+	TBL_ENTRY(0x680), TBL_ENTRY(0x681), TBL_ENTRY(0x682), TBL_ENTRY(0x683),
+	TBL_ENTRY(0x684), TBL_ENTRY(0x685), TBL_ENTRY(0x686), TBL_ENTRY(0x687),
+	TBL_ENTRY(0x688), TBL_ENTRY(0x689), TBL_ENTRY(0x68a), TBL_ENTRY(0x68b),
+	TBL_ENTRY(0x68c), TBL_ENTRY(0x68d), TBL_ENTRY(0x68e), TBL_ENTRY(0x68f),
+	TBL_ENTRY(0x690), TBL_ENTRY(0x691), TBL_ENTRY(0x692), TBL_ENTRY(0x693),
+	TBL_ENTRY(0x694), TBL_ENTRY(0x695), TBL_ENTRY(0x696), TBL_ENTRY(0x697),
+	TBL_ENTRY(0x698), TBL_ENTRY(0x699), TBL_ENTRY(0x69a), TBL_ENTRY(0x69b),
+	TBL_ENTRY(0x69c), TBL_ENTRY(0x69d), TBL_ENTRY(0x69e), TBL_ENTRY(0x69f),
+	TBL_ENTRY(0x6a0), TBL_ENTRY(0x6a1), TBL_ENTRY(0x6a2), TBL_ENTRY(0x6a3),
+	TBL_ENTRY(0x6a4), TBL_ENTRY(0x6a5), TBL_ENTRY(0x6a6), TBL_ENTRY(0x6a7),
+	TBL_ENTRY(0x6a8), TBL_ENTRY(0x6a9), TBL_ENTRY(0x6aa), TBL_ENTRY(0x6ab),
+	TBL_ENTRY(0x6ac), TBL_ENTRY(0x6ad), TBL_ENTRY(0x6ae), TBL_ENTRY(0x6af),
+	TBL_ENTRY(0x6b0), TBL_ENTRY(0x6b1), TBL_ENTRY(0x6b2), TBL_ENTRY(0x6b3),
+	TBL_ENTRY(0x6b4), TBL_ENTRY(0x6b5), TBL_ENTRY(0x6b6), TBL_ENTRY(0x6b7),
+	TBL_ENTRY(0x6b8), TBL_ENTRY(0x6b9), TBL_ENTRY(0x6ba), TBL_ENTRY(0x6bb),
+	TBL_ENTRY(0x6bc), TBL_ENTRY(0x6bd), TBL_ENTRY(0x6be), TBL_ENTRY(0x6bf),
+	TBL_ENTRY(0x6c0), TBL_ENTRY(0x6c1), TBL_ENTRY(0x6c2), TBL_ENTRY(0x6c3),
+	TBL_ENTRY(0x6c4), TBL_ENTRY(0x6c5), TBL_ENTRY(0x6c6), TBL_ENTRY(0x6c7),
+	TBL_ENTRY(0x6c8), TBL_ENTRY(0x6c9), TBL_ENTRY(0x6ca), TBL_ENTRY(0x6cb),
+	TBL_ENTRY(0x6cc), TBL_ENTRY(0x6cd), TBL_ENTRY(0x6ce), TBL_ENTRY(0x6cf),
+	TBL_ENTRY(0x6d0), TBL_ENTRY(0x6d1), TBL_ENTRY(0x6d2), TBL_ENTRY(0x6d3),
+	TBL_ENTRY(0x6d4), TBL_ENTRY(0x6d5), TBL_ENTRY(0x6d6), TBL_ENTRY(0x6d7),
+	TBL_ENTRY(0x6d8), TBL_ENTRY(0x6d9), TBL_ENTRY(0x6da), TBL_ENTRY(0x6db),
+	TBL_ENTRY(0x6dc), TBL_ENTRY(0x6dd), TBL_ENTRY(0x6de), TBL_ENTRY(0x6df),
+	TBL_ENTRY(0x6e0), TBL_ENTRY(0x6e1), TBL_ENTRY(0x6e2), TBL_ENTRY(0x6e3),
+	TBL_ENTRY(0x6e4), TBL_ENTRY(0x6e5), TBL_ENTRY(0x6e6), TBL_ENTRY(0x6e7),
+	TBL_ENTRY(0x6e8), TBL_ENTRY(0x6e9), TBL_ENTRY(0x6ea), TBL_ENTRY(0x6eb),
+	TBL_ENTRY(0x6ec), TBL_ENTRY(0x6ed), TBL_ENTRY(0x6ee), TBL_ENTRY(0x6ef),
+	TBL_ENTRY(0x6f0), TBL_ENTRY(0x6f1), TBL_ENTRY(0x6f2), TBL_ENTRY(0x6f3),
+	TBL_ENTRY(0x6f4), TBL_ENTRY(0x6f5), TBL_ENTRY(0x6f6), TBL_ENTRY(0x6f7),
+	TBL_ENTRY(0x6f8), TBL_ENTRY(0x6f9), TBL_ENTRY(0x6fa), TBL_ENTRY(0x6fb),
+	TBL_ENTRY(0x6fc), TBL_ENTRY(0x6fd), TBL_ENTRY(0x6fe), TBL_ENTRY(0x6ff),
+	TBL_ENTRY(0x700), TBL_ENTRY(0x701), TBL_ENTRY(0x702), TBL_ENTRY(0x703),
+	TBL_ENTRY(0x704), TBL_ENTRY(0x705), TBL_ENTRY(0x706), TBL_ENTRY(0x707),
+	TBL_ENTRY(0x708), TBL_ENTRY(0x709), TBL_ENTRY(0x70a), TBL_ENTRY(0x70b),
+	TBL_ENTRY(0x70c), TBL_ENTRY(0x70d), TBL_ENTRY(0x70e), TBL_ENTRY(0x70f),
+	TBL_ENTRY(0x710), TBL_ENTRY(0x711), TBL_ENTRY(0x712), TBL_ENTRY(0x713),
+	TBL_ENTRY(0x714), TBL_ENTRY(0x715), TBL_ENTRY(0x716), TBL_ENTRY(0x717),
+	TBL_ENTRY(0x718), TBL_ENTRY(0x719), TBL_ENTRY(0x71a), TBL_ENTRY(0x71b),
+	TBL_ENTRY(0x71c), TBL_ENTRY(0x71d), TBL_ENTRY(0x71e), TBL_ENTRY(0x71f),
+	TBL_ENTRY(0x720), TBL_ENTRY(0x721), TBL_ENTRY(0x722), TBL_ENTRY(0x723),
+	TBL_ENTRY(0x724), TBL_ENTRY(0x725), TBL_ENTRY(0x726), TBL_ENTRY(0x727),
+	TBL_ENTRY(0x728), TBL_ENTRY(0x729), TBL_ENTRY(0x72a), TBL_ENTRY(0x72b),
+	TBL_ENTRY(0x72c), TBL_ENTRY(0x72d), TBL_ENTRY(0x72e), TBL_ENTRY(0x72f),
+	TBL_ENTRY(0x730), TBL_ENTRY(0x731), TBL_ENTRY(0x732), TBL_ENTRY(0x733),
+	TBL_ENTRY(0x734), TBL_ENTRY(0x735), TBL_ENTRY(0x736), TBL_ENTRY(0x737),
+	TBL_ENTRY(0x738), TBL_ENTRY(0x739), TBL_ENTRY(0x73a), TBL_ENTRY(0x73b),
+	TBL_ENTRY(0x73c), TBL_ENTRY(0x73d), TBL_ENTRY(0x73e), TBL_ENTRY(0x73f),
+	TBL_ENTRY(0x740), TBL_ENTRY(0x741), TBL_ENTRY(0x742), TBL_ENTRY(0x743),
+	TBL_ENTRY(0x744), TBL_ENTRY(0x745), TBL_ENTRY(0x746), TBL_ENTRY(0x747),
+	TBL_ENTRY(0x748), TBL_ENTRY(0x749), TBL_ENTRY(0x74a), TBL_ENTRY(0x74b),
+	TBL_ENTRY(0x74c), TBL_ENTRY(0x74d), TBL_ENTRY(0x74e), TBL_ENTRY(0x74f),
+	TBL_ENTRY(0x750), TBL_ENTRY(0x751), TBL_ENTRY(0x752), TBL_ENTRY(0x753),
+	TBL_ENTRY(0x754), TBL_ENTRY(0x755), TBL_ENTRY(0x756), TBL_ENTRY(0x757),
+	TBL_ENTRY(0x758), TBL_ENTRY(0x759), TBL_ENTRY(0x75a), TBL_ENTRY(0x75b),
+	TBL_ENTRY(0x75c), TBL_ENTRY(0x75d), TBL_ENTRY(0x75e), TBL_ENTRY(0x75f),
+	TBL_ENTRY(0x760), TBL_ENTRY(0x761), TBL_ENTRY(0x762), TBL_ENTRY(0x763),
+	TBL_ENTRY(0x764), TBL_ENTRY(0x765), TBL_ENTRY(0x766), TBL_ENTRY(0x767),
+	TBL_ENTRY(0x768), TBL_ENTRY(0x769), TBL_ENTRY(0x76a), TBL_ENTRY(0x76b),
+	TBL_ENTRY(0x76c), TBL_ENTRY(0x76d), TBL_ENTRY(0x76e), TBL_ENTRY(0x76f),
+	TBL_ENTRY(0x770), TBL_ENTRY(0x771), TBL_ENTRY(0x772), TBL_ENTRY(0x773),
+	TBL_ENTRY(0x774), TBL_ENTRY(0x775), TBL_ENTRY(0x776), TBL_ENTRY(0x777),
+	TBL_ENTRY(0x778), TBL_ENTRY(0x779), TBL_ENTRY(0x77a), TBL_ENTRY(0x77b),
+	TBL_ENTRY(0x77c), TBL_ENTRY(0x77d), TBL_ENTRY(0x77e), TBL_ENTRY(0x77f),
+	TBL_ENTRY(0x780), TBL_ENTRY(0x781), TBL_ENTRY(0x782), TBL_ENTRY(0x783),
+	TBL_ENTRY(0x784), TBL_ENTRY(0x785), TBL_ENTRY(0x786), TBL_ENTRY(0x787),
+	TBL_ENTRY(0x788), TBL_ENTRY(0x789), TBL_ENTRY(0x78a), TBL_ENTRY(0x78b),
+	TBL_ENTRY(0x78c), TBL_ENTRY(0x78d), TBL_ENTRY(0x78e), TBL_ENTRY(0x78f),
+	TBL_ENTRY(0x790), TBL_ENTRY(0x791), TBL_ENTRY(0x792), TBL_ENTRY(0x793),
+	TBL_ENTRY(0x794), TBL_ENTRY(0x795), TBL_ENTRY(0x796), TBL_ENTRY(0x797),
+	TBL_ENTRY(0x798), TBL_ENTRY(0x799), TBL_ENTRY(0x79a), TBL_ENTRY(0x79b),
+	TBL_ENTRY(0x79c), TBL_ENTRY(0x79d), TBL_ENTRY(0x79e), TBL_ENTRY(0x79f),
+	TBL_ENTRY(0x7a0), TBL_ENTRY(0x7a1), TBL_ENTRY(0x7a2), TBL_ENTRY(0x7a3),
+	TBL_ENTRY(0x7a4), TBL_ENTRY(0x7a5), TBL_ENTRY(0x7a6), TBL_ENTRY(0x7a7),
+	TBL_ENTRY(0x7a8), TBL_ENTRY(0x7a9), TBL_ENTRY(0x7aa), TBL_ENTRY(0x7ab),
+	TBL_ENTRY(0x7ac), TBL_ENTRY(0x7ad), TBL_ENTRY(0x7ae), TBL_ENTRY(0x7af),
+	TBL_ENTRY(0x7b0), TBL_ENTRY(0x7b1), TBL_ENTRY(0x7b2), TBL_ENTRY(0x7b3),
+	TBL_ENTRY(0x7b4), TBL_ENTRY(0x7b5), TBL_ENTRY(0x7b6), TBL_ENTRY(0x7b7),
+	TBL_ENTRY(0x7b8), TBL_ENTRY(0x7b9), TBL_ENTRY(0x7ba), TBL_ENTRY(0x7bb),
+	TBL_ENTRY(0x7bc), TBL_ENTRY(0x7bd), TBL_ENTRY(0x7be), TBL_ENTRY(0x7bf),
+	TBL_ENTRY(0x7c0), TBL_ENTRY(0x7c1), TBL_ENTRY(0x7c2), TBL_ENTRY(0x7c3),
+	TBL_ENTRY(0x7c4), TBL_ENTRY(0x7c5), TBL_ENTRY(0x7c6), TBL_ENTRY(0x7c7),
+	TBL_ENTRY(0x7c8), TBL_ENTRY(0x7c9), TBL_ENTRY(0x7ca), TBL_ENTRY(0x7cb),
+	TBL_ENTRY(0x7cc), TBL_ENTRY(0x7cd), TBL_ENTRY(0x7ce), TBL_ENTRY(0x7cf),
+	TBL_ENTRY(0x7d0), TBL_ENTRY(0x7d1), TBL_ENTRY(0x7d2), TBL_ENTRY(0x7d3),
+	TBL_ENTRY(0x7d4), TBL_ENTRY(0x7d5), TBL_ENTRY(0x7d6), TBL_ENTRY(0x7d7),
+	TBL_ENTRY(0x7d8), TBL_ENTRY(0x7d9), TBL_ENTRY(0x7da), TBL_ENTRY(0x7db),
+	TBL_ENTRY(0x7dc), TBL_ENTRY(0x7dd), TBL_ENTRY(0x7de), TBL_ENTRY(0x7df),
+	TBL_ENTRY(0x7e0), TBL_ENTRY(0x7e1), TBL_ENTRY(0x7e2), TBL_ENTRY(0x7e3),
+	TBL_ENTRY(0x7e4), TBL_ENTRY(0x7e5), TBL_ENTRY(0x7e6), TBL_ENTRY(0x7e7),
+	TBL_ENTRY(0x7e8), TBL_ENTRY(0x7e9), TBL_ENTRY(0x7ea), TBL_ENTRY(0x7eb),
+	TBL_ENTRY(0x7ec), TBL_ENTRY(0x7ed), TBL_ENTRY(0x7ee), TBL_ENTRY(0x7ef),
+	TBL_ENTRY(0x7f0), TBL_ENTRY(0x7f1), TBL_ENTRY(0x7f2), TBL_ENTRY(0x7f3),
+	TBL_ENTRY(0x7f4), TBL_ENTRY(0x7f5), TBL_ENTRY(0x7f6), TBL_ENTRY(0x7f7),
+	TBL_ENTRY(0x7f8), TBL_ENTRY(0x7f9), TBL_ENTRY(0x7fa), TBL_ENTRY(0x7fb),
+	TBL_ENTRY(0x7fc), TBL_ENTRY(0x7fd), TBL_ENTRY(0x7fe), TBL_ENTRY(0x7ff),
+	TBL_ENTRY(0x800), TBL_ENTRY(0x801), TBL_ENTRY(0x802), TBL_ENTRY(0x803),
+	TBL_ENTRY(0x804), TBL_ENTRY(0x805), TBL_ENTRY(0x806), TBL_ENTRY(0x807),
+	TBL_ENTRY(0x808), TBL_ENTRY(0x809), TBL_ENTRY(0x80a), TBL_ENTRY(0x80b),
+	TBL_ENTRY(0x80c), TBL_ENTRY(0x80d), TBL_ENTRY(0x80e), TBL_ENTRY(0x80f),
+	TBL_ENTRY(0x810), TBL_ENTRY(0x811), TBL_ENTRY(0x812), TBL_ENTRY(0x813),
+	TBL_ENTRY(0x814), TBL_ENTRY(0x815), TBL_ENTRY(0x816), TBL_ENTRY(0x817),
+	TBL_ENTRY(0x818), TBL_ENTRY(0x819), TBL_ENTRY(0x81a), TBL_ENTRY(0x81b),
+	TBL_ENTRY(0x81c), TBL_ENTRY(0x81d), TBL_ENTRY(0x81e), TBL_ENTRY(0x81f),
+	TBL_ENTRY(0x820), TBL_ENTRY(0x821), TBL_ENTRY(0x822), TBL_ENTRY(0x823),
+	TBL_ENTRY(0x824), TBL_ENTRY(0x825), TBL_ENTRY(0x826), TBL_ENTRY(0x827),
+	TBL_ENTRY(0x828), TBL_ENTRY(0x829), TBL_ENTRY(0x82a), TBL_ENTRY(0x82b),
+	TBL_ENTRY(0x82c), TBL_ENTRY(0x82d), TBL_ENTRY(0x82e), TBL_ENTRY(0x82f),
+	TBL_ENTRY(0x830), TBL_ENTRY(0x831), TBL_ENTRY(0x832), TBL_ENTRY(0x833),
+	TBL_ENTRY(0x834), TBL_ENTRY(0x835), TBL_ENTRY(0x836), TBL_ENTRY(0x837),
+	TBL_ENTRY(0x838), TBL_ENTRY(0x839), TBL_ENTRY(0x83a), TBL_ENTRY(0x83b),
+	TBL_ENTRY(0x83c), TBL_ENTRY(0x83d), TBL_ENTRY(0x83e), TBL_ENTRY(0x83f),
+	TBL_ENTRY(0x840), TBL_ENTRY(0x841), TBL_ENTRY(0x842), TBL_ENTRY(0x843),
+	TBL_ENTRY(0x844), TBL_ENTRY(0x845), TBL_ENTRY(0x846), TBL_ENTRY(0x847),
+	TBL_ENTRY(0x848), TBL_ENTRY(0x849), TBL_ENTRY(0x84a), TBL_ENTRY(0x84b),
+	TBL_ENTRY(0x84c), TBL_ENTRY(0x84d), TBL_ENTRY(0x84e), TBL_ENTRY(0x84f),
+	TBL_ENTRY(0x850), TBL_ENTRY(0x851), TBL_ENTRY(0x852), TBL_ENTRY(0x853),
+	TBL_ENTRY(0x854), TBL_ENTRY(0x855), TBL_ENTRY(0x856), TBL_ENTRY(0x857),
+	TBL_ENTRY(0x858), TBL_ENTRY(0x859), TBL_ENTRY(0x85a), TBL_ENTRY(0x85b),
+	TBL_ENTRY(0x85c), TBL_ENTRY(0x85d), TBL_ENTRY(0x85e), TBL_ENTRY(0x85f),
+	TBL_ENTRY(0x860), TBL_ENTRY(0x861), TBL_ENTRY(0x862), TBL_ENTRY(0x863),
+	TBL_ENTRY(0x864), TBL_ENTRY(0x865), TBL_ENTRY(0x866), TBL_ENTRY(0x867),
+	TBL_ENTRY(0x868), TBL_ENTRY(0x869), TBL_ENTRY(0x86a), TBL_ENTRY(0x86b),
+	TBL_ENTRY(0x86c), TBL_ENTRY(0x86d), TBL_ENTRY(0x86e), TBL_ENTRY(0x86f),
+	TBL_ENTRY(0x870), TBL_ENTRY(0x871), TBL_ENTRY(0x872), TBL_ENTRY(0x873),
+	TBL_ENTRY(0x874), TBL_ENTRY(0x875), TBL_ENTRY(0x876), TBL_ENTRY(0x877),
+	TBL_ENTRY(0x878), TBL_ENTRY(0x879), TBL_ENTRY(0x87a), TBL_ENTRY(0x87b),
+	TBL_ENTRY(0x87c), TBL_ENTRY(0x87d), TBL_ENTRY(0x87e), TBL_ENTRY(0x87f),
+	TBL_ENTRY(0x880), TBL_ENTRY(0x881), TBL_ENTRY(0x882), TBL_ENTRY(0x883),
+	TBL_ENTRY(0x884), TBL_ENTRY(0x885), TBL_ENTRY(0x886), TBL_ENTRY(0x887),
+	TBL_ENTRY(0x888), TBL_ENTRY(0x889), TBL_ENTRY(0x88a), TBL_ENTRY(0x88b),
+	TBL_ENTRY(0x88c), TBL_ENTRY(0x88d), TBL_ENTRY(0x88e), TBL_ENTRY(0x88f),
+	TBL_ENTRY(0x890), TBL_ENTRY(0x891), TBL_ENTRY(0x892), TBL_ENTRY(0x893),
+	TBL_ENTRY(0x894), TBL_ENTRY(0x895), TBL_ENTRY(0x896), TBL_ENTRY(0x897),
+	TBL_ENTRY(0x898), TBL_ENTRY(0x899), TBL_ENTRY(0x89a), TBL_ENTRY(0x89b),
+	TBL_ENTRY(0x89c), TBL_ENTRY(0x89d), TBL_ENTRY(0x89e), TBL_ENTRY(0x89f),
+	TBL_ENTRY(0x8a0), TBL_ENTRY(0x8a1), TBL_ENTRY(0x8a2), TBL_ENTRY(0x8a3),
+	TBL_ENTRY(0x8a4), TBL_ENTRY(0x8a5), TBL_ENTRY(0x8a6), TBL_ENTRY(0x8a7),
+	TBL_ENTRY(0x8a8), TBL_ENTRY(0x8a9), TBL_ENTRY(0x8aa), TBL_ENTRY(0x8ab),
+	TBL_ENTRY(0x8ac), TBL_ENTRY(0x8ad), TBL_ENTRY(0x8ae), TBL_ENTRY(0x8af),
+	TBL_ENTRY(0x8b0), TBL_ENTRY(0x8b1), TBL_ENTRY(0x8b2), TBL_ENTRY(0x8b3),
+	TBL_ENTRY(0x8b4), TBL_ENTRY(0x8b5), TBL_ENTRY(0x8b6), TBL_ENTRY(0x8b7),
+	TBL_ENTRY(0x8b8), TBL_ENTRY(0x8b9), TBL_ENTRY(0x8ba), TBL_ENTRY(0x8bb),
+	TBL_ENTRY(0x8bc), TBL_ENTRY(0x8bd), TBL_ENTRY(0x8be), TBL_ENTRY(0x8bf),
+	TBL_ENTRY(0x8c0), TBL_ENTRY(0x8c1), TBL_ENTRY(0x8c2), TBL_ENTRY(0x8c3),
+	TBL_ENTRY(0x8c4), TBL_ENTRY(0x8c5), TBL_ENTRY(0x8c6), TBL_ENTRY(0x8c7),
+	TBL_ENTRY(0x8c8), TBL_ENTRY(0x8c9), TBL_ENTRY(0x8ca), TBL_ENTRY(0x8cb),
+	TBL_ENTRY(0x8cc), TBL_ENTRY(0x8cd), TBL_ENTRY(0x8ce), TBL_ENTRY(0x8cf),
+	TBL_ENTRY(0x8d0), TBL_ENTRY(0x8d1), TBL_ENTRY(0x8d2), TBL_ENTRY(0x8d3),
+	TBL_ENTRY(0x8d4), TBL_ENTRY(0x8d5), TBL_ENTRY(0x8d6), TBL_ENTRY(0x8d7),
+	TBL_ENTRY(0x8d8), TBL_ENTRY(0x8d9), TBL_ENTRY(0x8da), TBL_ENTRY(0x8db),
+	TBL_ENTRY(0x8dc), TBL_ENTRY(0x8dd), TBL_ENTRY(0x8de), TBL_ENTRY(0x8df),
+	TBL_ENTRY(0x8e0), TBL_ENTRY(0x8e1), TBL_ENTRY(0x8e2), TBL_ENTRY(0x8e3),
+	TBL_ENTRY(0x8e4), TBL_ENTRY(0x8e5), TBL_ENTRY(0x8e6), TBL_ENTRY(0x8e7),
+	TBL_ENTRY(0x8e8), TBL_ENTRY(0x8e9), TBL_ENTRY(0x8ea), TBL_ENTRY(0x8eb),
+	TBL_ENTRY(0x8ec), TBL_ENTRY(0x8ed), TBL_ENTRY(0x8ee), TBL_ENTRY(0x8ef),
+	TBL_ENTRY(0x8f0), TBL_ENTRY(0x8f1), TBL_ENTRY(0x8f2), TBL_ENTRY(0x8f3),
+	TBL_ENTRY(0x8f4), TBL_ENTRY(0x8f5), TBL_ENTRY(0x8f6), TBL_ENTRY(0x8f7),
+	TBL_ENTRY(0x8f8), TBL_ENTRY(0x8f9), TBL_ENTRY(0x8fa), TBL_ENTRY(0x8fb),
+	TBL_ENTRY(0x8fc), TBL_ENTRY(0x8fd), TBL_ENTRY(0x8fe), TBL_ENTRY(0x8ff),
+	TBL_ENTRY(0x900), TBL_ENTRY(0x901), TBL_ENTRY(0x902), TBL_ENTRY(0x903),
+	TBL_ENTRY(0x904), TBL_ENTRY(0x905), TBL_ENTRY(0x906), TBL_ENTRY(0x907),
+	TBL_ENTRY(0x908), TBL_ENTRY(0x909), TBL_ENTRY(0x90a), TBL_ENTRY(0x90b),
+	TBL_ENTRY(0x90c), TBL_ENTRY(0x90d), TBL_ENTRY(0x90e), TBL_ENTRY(0x90f),
+	TBL_ENTRY(0x910), TBL_ENTRY(0x911), TBL_ENTRY(0x912), TBL_ENTRY(0x913),
+	TBL_ENTRY(0x914), TBL_ENTRY(0x915), TBL_ENTRY(0x916), TBL_ENTRY(0x917),
+	TBL_ENTRY(0x918), TBL_ENTRY(0x919), TBL_ENTRY(0x91a), TBL_ENTRY(0x91b),
+	TBL_ENTRY(0x91c), TBL_ENTRY(0x91d), TBL_ENTRY(0x91e), TBL_ENTRY(0x91f),
+	TBL_ENTRY(0x920), TBL_ENTRY(0x921), TBL_ENTRY(0x922), TBL_ENTRY(0x923),
+	TBL_ENTRY(0x924), TBL_ENTRY(0x925), TBL_ENTRY(0x926), TBL_ENTRY(0x927),
+	TBL_ENTRY(0x928), TBL_ENTRY(0x929), TBL_ENTRY(0x92a), TBL_ENTRY(0x92b),
+	TBL_ENTRY(0x92c), TBL_ENTRY(0x92d), TBL_ENTRY(0x92e), TBL_ENTRY(0x92f),
+	TBL_ENTRY(0x930), TBL_ENTRY(0x931), TBL_ENTRY(0x932), TBL_ENTRY(0x933),
+	TBL_ENTRY(0x934), TBL_ENTRY(0x935), TBL_ENTRY(0x936), TBL_ENTRY(0x937),
+	TBL_ENTRY(0x938), TBL_ENTRY(0x939), TBL_ENTRY(0x93a), TBL_ENTRY(0x93b),
+	TBL_ENTRY(0x93c), TBL_ENTRY(0x93d), TBL_ENTRY(0x93e), TBL_ENTRY(0x93f),
+	TBL_ENTRY(0x940), TBL_ENTRY(0x941), TBL_ENTRY(0x942), TBL_ENTRY(0x943),
+	TBL_ENTRY(0x944), TBL_ENTRY(0x945), TBL_ENTRY(0x946), TBL_ENTRY(0x947),
+	TBL_ENTRY(0x948), TBL_ENTRY(0x949), TBL_ENTRY(0x94a), TBL_ENTRY(0x94b),
+	TBL_ENTRY(0x94c), TBL_ENTRY(0x94d), TBL_ENTRY(0x94e), TBL_ENTRY(0x94f),
+	TBL_ENTRY(0x950), TBL_ENTRY(0x951), TBL_ENTRY(0x952), TBL_ENTRY(0x953),
+	TBL_ENTRY(0x954), TBL_ENTRY(0x955), TBL_ENTRY(0x956), TBL_ENTRY(0x957),
+	TBL_ENTRY(0x958), TBL_ENTRY(0x959), TBL_ENTRY(0x95a), TBL_ENTRY(0x95b),
+	TBL_ENTRY(0x95c), TBL_ENTRY(0x95d), TBL_ENTRY(0x95e), TBL_ENTRY(0x95f),
+	TBL_ENTRY(0x960), TBL_ENTRY(0x961), TBL_ENTRY(0x962), TBL_ENTRY(0x963),
+	TBL_ENTRY(0x964), TBL_ENTRY(0x965), TBL_ENTRY(0x966), TBL_ENTRY(0x967),
+	TBL_ENTRY(0x968), TBL_ENTRY(0x969), TBL_ENTRY(0x96a), TBL_ENTRY(0x96b),
+	TBL_ENTRY(0x96c), TBL_ENTRY(0x96d), TBL_ENTRY(0x96e), TBL_ENTRY(0x96f),
+	TBL_ENTRY(0x970), TBL_ENTRY(0x971), TBL_ENTRY(0x972), TBL_ENTRY(0x973),
+	TBL_ENTRY(0x974), TBL_ENTRY(0x975), TBL_ENTRY(0x976), TBL_ENTRY(0x977),
+	TBL_ENTRY(0x978), TBL_ENTRY(0x979), TBL_ENTRY(0x97a), TBL_ENTRY(0x97b),
+	TBL_ENTRY(0x97c), TBL_ENTRY(0x97d), TBL_ENTRY(0x97e), TBL_ENTRY(0x97f),
+	TBL_ENTRY(0x980), TBL_ENTRY(0x981), TBL_ENTRY(0x982), TBL_ENTRY(0x983),
+	TBL_ENTRY(0x984), TBL_ENTRY(0x985), TBL_ENTRY(0x986), TBL_ENTRY(0x987),
+	TBL_ENTRY(0x988), TBL_ENTRY(0x989), TBL_ENTRY(0x98a), TBL_ENTRY(0x98b),
+	TBL_ENTRY(0x98c), TBL_ENTRY(0x98d), TBL_ENTRY(0x98e), TBL_ENTRY(0x98f),
+	TBL_ENTRY(0x990), TBL_ENTRY(0x991), TBL_ENTRY(0x992), TBL_ENTRY(0x993),
+	TBL_ENTRY(0x994), TBL_ENTRY(0x995), TBL_ENTRY(0x996), TBL_ENTRY(0x997),
+	TBL_ENTRY(0x998), TBL_ENTRY(0x999), TBL_ENTRY(0x99a), TBL_ENTRY(0x99b),
+	TBL_ENTRY(0x99c), TBL_ENTRY(0x99d), TBL_ENTRY(0x99e), TBL_ENTRY(0x99f),
+	TBL_ENTRY(0x9a0), TBL_ENTRY(0x9a1), TBL_ENTRY(0x9a2), TBL_ENTRY(0x9a3),
+	TBL_ENTRY(0x9a4), TBL_ENTRY(0x9a5), TBL_ENTRY(0x9a6), TBL_ENTRY(0x9a7),
+	TBL_ENTRY(0x9a8), TBL_ENTRY(0x9a9), TBL_ENTRY(0x9aa), TBL_ENTRY(0x9ab),
+	TBL_ENTRY(0x9ac), TBL_ENTRY(0x9ad), TBL_ENTRY(0x9ae), TBL_ENTRY(0x9af),
+	TBL_ENTRY(0x9b0), TBL_ENTRY(0x9b1), TBL_ENTRY(0x9b2), TBL_ENTRY(0x9b3),
+	TBL_ENTRY(0x9b4), TBL_ENTRY(0x9b5), TBL_ENTRY(0x9b6), TBL_ENTRY(0x9b7),
+	TBL_ENTRY(0x9b8), TBL_ENTRY(0x9b9), TBL_ENTRY(0x9ba), TBL_ENTRY(0x9bb),
+	TBL_ENTRY(0x9bc), TBL_ENTRY(0x9bd), TBL_ENTRY(0x9be), TBL_ENTRY(0x9bf),
+	TBL_ENTRY(0x9c0), TBL_ENTRY(0x9c1), TBL_ENTRY(0x9c2), TBL_ENTRY(0x9c3),
+	TBL_ENTRY(0x9c4), TBL_ENTRY(0x9c5), TBL_ENTRY(0x9c6), TBL_ENTRY(0x9c7),
+	TBL_ENTRY(0x9c8), TBL_ENTRY(0x9c9), TBL_ENTRY(0x9ca), TBL_ENTRY(0x9cb),
+	TBL_ENTRY(0x9cc), TBL_ENTRY(0x9cd), TBL_ENTRY(0x9ce), TBL_ENTRY(0x9cf),
+	TBL_ENTRY(0x9d0), TBL_ENTRY(0x9d1), TBL_ENTRY(0x9d2), TBL_ENTRY(0x9d3),
+	TBL_ENTRY(0x9d4), TBL_ENTRY(0x9d5), TBL_ENTRY(0x9d6), TBL_ENTRY(0x9d7),
+	TBL_ENTRY(0x9d8), TBL_ENTRY(0x9d9), TBL_ENTRY(0x9da), TBL_ENTRY(0x9db),
+	TBL_ENTRY(0x9dc), TBL_ENTRY(0x9dd), TBL_ENTRY(0x9de), TBL_ENTRY(0x9df),
+	TBL_ENTRY(0x9e0), TBL_ENTRY(0x9e1), TBL_ENTRY(0x9e2), TBL_ENTRY(0x9e3),
+	TBL_ENTRY(0x9e4), TBL_ENTRY(0x9e5), TBL_ENTRY(0x9e6), TBL_ENTRY(0x9e7),
+	TBL_ENTRY(0x9e8), TBL_ENTRY(0x9e9), TBL_ENTRY(0x9ea), TBL_ENTRY(0x9eb),
+	TBL_ENTRY(0x9ec), TBL_ENTRY(0x9ed), TBL_ENTRY(0x9ee), TBL_ENTRY(0x9ef),
+	TBL_ENTRY(0x9f0), TBL_ENTRY(0x9f1), TBL_ENTRY(0x9f2), TBL_ENTRY(0x9f3),
+	TBL_ENTRY(0x9f4), TBL_ENTRY(0x9f5), TBL_ENTRY(0x9f6), TBL_ENTRY(0x9f7),
+	TBL_ENTRY(0x9f8), TBL_ENTRY(0x9f9), TBL_ENTRY(0x9fa), TBL_ENTRY(0x9fb),
+	TBL_ENTRY(0x9fc), TBL_ENTRY(0x9fd), TBL_ENTRY(0x9fe), TBL_ENTRY(0x9ff),
+	TBL_ENTRY(0xa00), TBL_ENTRY(0xa01), TBL_ENTRY(0xa02), TBL_ENTRY(0xa03),
+	TBL_ENTRY(0xa04), TBL_ENTRY(0xa05), TBL_ENTRY(0xa06), TBL_ENTRY(0xa07),
+	TBL_ENTRY(0xa08), TBL_ENTRY(0xa09), TBL_ENTRY(0xa0a), TBL_ENTRY(0xa0b),
+	TBL_ENTRY(0xa0c), TBL_ENTRY(0xa0d), TBL_ENTRY(0xa0e), TBL_ENTRY(0xa0f),
+	TBL_ENTRY(0xa10), TBL_ENTRY(0xa11), TBL_ENTRY(0xa12), TBL_ENTRY(0xa13),
+	TBL_ENTRY(0xa14), TBL_ENTRY(0xa15), TBL_ENTRY(0xa16), TBL_ENTRY(0xa17),
+	TBL_ENTRY(0xa18), TBL_ENTRY(0xa19), TBL_ENTRY(0xa1a), TBL_ENTRY(0xa1b),
+	TBL_ENTRY(0xa1c), TBL_ENTRY(0xa1d), TBL_ENTRY(0xa1e), TBL_ENTRY(0xa1f),
+	TBL_ENTRY(0xa20), TBL_ENTRY(0xa21), TBL_ENTRY(0xa22), TBL_ENTRY(0xa23),
+	TBL_ENTRY(0xa24), TBL_ENTRY(0xa25), TBL_ENTRY(0xa26), TBL_ENTRY(0xa27),
+	TBL_ENTRY(0xa28), TBL_ENTRY(0xa29), TBL_ENTRY(0xa2a), TBL_ENTRY(0xa2b),
+	TBL_ENTRY(0xa2c), TBL_ENTRY(0xa2d), TBL_ENTRY(0xa2e), TBL_ENTRY(0xa2f),
+	TBL_ENTRY(0xa30), TBL_ENTRY(0xa31), TBL_ENTRY(0xa32), TBL_ENTRY(0xa33),
+	TBL_ENTRY(0xa34), TBL_ENTRY(0xa35), TBL_ENTRY(0xa36), TBL_ENTRY(0xa37),
+	TBL_ENTRY(0xa38), TBL_ENTRY(0xa39), TBL_ENTRY(0xa3a), TBL_ENTRY(0xa3b),
+	TBL_ENTRY(0xa3c), TBL_ENTRY(0xa3d), TBL_ENTRY(0xa3e), TBL_ENTRY(0xa3f),
+	TBL_ENTRY(0xa40), TBL_ENTRY(0xa41), TBL_ENTRY(0xa42), TBL_ENTRY(0xa43),
+	TBL_ENTRY(0xa44), TBL_ENTRY(0xa45), TBL_ENTRY(0xa46), TBL_ENTRY(0xa47),
+	TBL_ENTRY(0xa48), TBL_ENTRY(0xa49), TBL_ENTRY(0xa4a), TBL_ENTRY(0xa4b),
+	TBL_ENTRY(0xa4c), TBL_ENTRY(0xa4d), TBL_ENTRY(0xa4e), TBL_ENTRY(0xa4f),
+	TBL_ENTRY(0xa50), TBL_ENTRY(0xa51), TBL_ENTRY(0xa52), TBL_ENTRY(0xa53),
+	TBL_ENTRY(0xa54), TBL_ENTRY(0xa55), TBL_ENTRY(0xa56), TBL_ENTRY(0xa57),
+	TBL_ENTRY(0xa58), TBL_ENTRY(0xa59), TBL_ENTRY(0xa5a), TBL_ENTRY(0xa5b),
+	TBL_ENTRY(0xa5c), TBL_ENTRY(0xa5d), TBL_ENTRY(0xa5e), TBL_ENTRY(0xa5f),
+	TBL_ENTRY(0xa60), TBL_ENTRY(0xa61), TBL_ENTRY(0xa62), TBL_ENTRY(0xa63),
+	TBL_ENTRY(0xa64), TBL_ENTRY(0xa65), TBL_ENTRY(0xa66), TBL_ENTRY(0xa67),
+	TBL_ENTRY(0xa68), TBL_ENTRY(0xa69), TBL_ENTRY(0xa6a), TBL_ENTRY(0xa6b),
+	TBL_ENTRY(0xa6c), TBL_ENTRY(0xa6d), TBL_ENTRY(0xa6e), TBL_ENTRY(0xa6f),
+	TBL_ENTRY(0xa70), TBL_ENTRY(0xa71), TBL_ENTRY(0xa72), TBL_ENTRY(0xa73),
+	TBL_ENTRY(0xa74), TBL_ENTRY(0xa75), TBL_ENTRY(0xa76), TBL_ENTRY(0xa77),
+	TBL_ENTRY(0xa78), TBL_ENTRY(0xa79), TBL_ENTRY(0xa7a), TBL_ENTRY(0xa7b),
+	TBL_ENTRY(0xa7c), TBL_ENTRY(0xa7d), TBL_ENTRY(0xa7e), TBL_ENTRY(0xa7f),
+	TBL_ENTRY(0xa80), TBL_ENTRY(0xa81), TBL_ENTRY(0xa82), TBL_ENTRY(0xa83),
+	TBL_ENTRY(0xa84), TBL_ENTRY(0xa85), TBL_ENTRY(0xa86), TBL_ENTRY(0xa87),
+	TBL_ENTRY(0xa88), TBL_ENTRY(0xa89), TBL_ENTRY(0xa8a), TBL_ENTRY(0xa8b),
+	TBL_ENTRY(0xa8c), TBL_ENTRY(0xa8d), TBL_ENTRY(0xa8e), TBL_ENTRY(0xa8f),
+	TBL_ENTRY(0xa90), TBL_ENTRY(0xa91), TBL_ENTRY(0xa92), TBL_ENTRY(0xa93),
+	TBL_ENTRY(0xa94), TBL_ENTRY(0xa95), TBL_ENTRY(0xa96), TBL_ENTRY(0xa97),
+	TBL_ENTRY(0xa98), TBL_ENTRY(0xa99), TBL_ENTRY(0xa9a), TBL_ENTRY(0xa9b),
+	TBL_ENTRY(0xa9c), TBL_ENTRY(0xa9d), TBL_ENTRY(0xa9e), TBL_ENTRY(0xa9f),
+	TBL_ENTRY(0xaa0), TBL_ENTRY(0xaa1), TBL_ENTRY(0xaa2), TBL_ENTRY(0xaa3),
+	TBL_ENTRY(0xaa4), TBL_ENTRY(0xaa5), TBL_ENTRY(0xaa6), TBL_ENTRY(0xaa7),
+	TBL_ENTRY(0xaa8), TBL_ENTRY(0xaa9), TBL_ENTRY(0xaaa), TBL_ENTRY(0xaab),
+	TBL_ENTRY(0xaac), TBL_ENTRY(0xaad), TBL_ENTRY(0xaae), TBL_ENTRY(0xaaf),
+	TBL_ENTRY(0xab0), TBL_ENTRY(0xab1), TBL_ENTRY(0xab2), TBL_ENTRY(0xab3),
+	TBL_ENTRY(0xab4), TBL_ENTRY(0xab5), TBL_ENTRY(0xab6), TBL_ENTRY(0xab7),
+	TBL_ENTRY(0xab8), TBL_ENTRY(0xab9), TBL_ENTRY(0xaba), TBL_ENTRY(0xabb),
+	TBL_ENTRY(0xabc), TBL_ENTRY(0xabd), TBL_ENTRY(0xabe), TBL_ENTRY(0xabf),
+	TBL_ENTRY(0xac0), TBL_ENTRY(0xac1), TBL_ENTRY(0xac2), TBL_ENTRY(0xac3),
+	TBL_ENTRY(0xac4), TBL_ENTRY(0xac5), TBL_ENTRY(0xac6), TBL_ENTRY(0xac7),
+	TBL_ENTRY(0xac8), TBL_ENTRY(0xac9), TBL_ENTRY(0xaca), TBL_ENTRY(0xacb),
+	TBL_ENTRY(0xacc), TBL_ENTRY(0xacd), TBL_ENTRY(0xace), TBL_ENTRY(0xacf),
+	TBL_ENTRY(0xad0), TBL_ENTRY(0xad1), TBL_ENTRY(0xad2), TBL_ENTRY(0xad3),
+	TBL_ENTRY(0xad4), TBL_ENTRY(0xad5), TBL_ENTRY(0xad6), TBL_ENTRY(0xad7),
+	TBL_ENTRY(0xad8), TBL_ENTRY(0xad9), TBL_ENTRY(0xada), TBL_ENTRY(0xadb),
+	TBL_ENTRY(0xadc), TBL_ENTRY(0xadd), TBL_ENTRY(0xade), TBL_ENTRY(0xadf),
+	TBL_ENTRY(0xae0), TBL_ENTRY(0xae1), TBL_ENTRY(0xae2), TBL_ENTRY(0xae3),
+	TBL_ENTRY(0xae4), TBL_ENTRY(0xae5), TBL_ENTRY(0xae6), TBL_ENTRY(0xae7),
+	TBL_ENTRY(0xae8), TBL_ENTRY(0xae9), TBL_ENTRY(0xaea), TBL_ENTRY(0xaeb),
+	TBL_ENTRY(0xaec), TBL_ENTRY(0xaed), TBL_ENTRY(0xaee), TBL_ENTRY(0xaef),
+	TBL_ENTRY(0xaf0), TBL_ENTRY(0xaf1), TBL_ENTRY(0xaf2), TBL_ENTRY(0xaf3),
+	TBL_ENTRY(0xaf4), TBL_ENTRY(0xaf5), TBL_ENTRY(0xaf6), TBL_ENTRY(0xaf7),
+	TBL_ENTRY(0xaf8), TBL_ENTRY(0xaf9), TBL_ENTRY(0xafa), TBL_ENTRY(0xafb),
+	TBL_ENTRY(0xafc), TBL_ENTRY(0xafd), TBL_ENTRY(0xafe), TBL_ENTRY(0xaff),
+	TBL_ENTRY(0xb00), TBL_ENTRY(0xb01), TBL_ENTRY(0xb02), TBL_ENTRY(0xb03),
+	TBL_ENTRY(0xb04), TBL_ENTRY(0xb05), TBL_ENTRY(0xb06), TBL_ENTRY(0xb07),
+	TBL_ENTRY(0xb08), TBL_ENTRY(0xb09), TBL_ENTRY(0xb0a), TBL_ENTRY(0xb0b),
+	TBL_ENTRY(0xb0c), TBL_ENTRY(0xb0d), TBL_ENTRY(0xb0e), TBL_ENTRY(0xb0f),
+	TBL_ENTRY(0xb10), TBL_ENTRY(0xb11), TBL_ENTRY(0xb12), TBL_ENTRY(0xb13),
+	TBL_ENTRY(0xb14), TBL_ENTRY(0xb15), TBL_ENTRY(0xb16), TBL_ENTRY(0xb17),
+	TBL_ENTRY(0xb18), TBL_ENTRY(0xb19), TBL_ENTRY(0xb1a), TBL_ENTRY(0xb1b),
+	TBL_ENTRY(0xb1c), TBL_ENTRY(0xb1d), TBL_ENTRY(0xb1e), TBL_ENTRY(0xb1f),
+	TBL_ENTRY(0xb20), TBL_ENTRY(0xb21), TBL_ENTRY(0xb22), TBL_ENTRY(0xb23),
+	TBL_ENTRY(0xb24), TBL_ENTRY(0xb25), TBL_ENTRY(0xb26), TBL_ENTRY(0xb27),
+	TBL_ENTRY(0xb28), TBL_ENTRY(0xb29), TBL_ENTRY(0xb2a), TBL_ENTRY(0xb2b),
+	TBL_ENTRY(0xb2c), TBL_ENTRY(0xb2d), TBL_ENTRY(0xb2e), TBL_ENTRY(0xb2f),
+	TBL_ENTRY(0xb30), TBL_ENTRY(0xb31), TBL_ENTRY(0xb32), TBL_ENTRY(0xb33),
+	TBL_ENTRY(0xb34), TBL_ENTRY(0xb35), TBL_ENTRY(0xb36), TBL_ENTRY(0xb37),
+	TBL_ENTRY(0xb38), TBL_ENTRY(0xb39), TBL_ENTRY(0xb3a), TBL_ENTRY(0xb3b),
+	TBL_ENTRY(0xb3c), TBL_ENTRY(0xb3d), TBL_ENTRY(0xb3e), TBL_ENTRY(0xb3f),
+	TBL_ENTRY(0xb40), TBL_ENTRY(0xb41), TBL_ENTRY(0xb42), TBL_ENTRY(0xb43),
+	TBL_ENTRY(0xb44), TBL_ENTRY(0xb45), TBL_ENTRY(0xb46), TBL_ENTRY(0xb47),
+	TBL_ENTRY(0xb48), TBL_ENTRY(0xb49), TBL_ENTRY(0xb4a), TBL_ENTRY(0xb4b),
+	TBL_ENTRY(0xb4c), TBL_ENTRY(0xb4d), TBL_ENTRY(0xb4e), TBL_ENTRY(0xb4f),
+	TBL_ENTRY(0xb50), TBL_ENTRY(0xb51), TBL_ENTRY(0xb52), TBL_ENTRY(0xb53),
+	TBL_ENTRY(0xb54), TBL_ENTRY(0xb55), TBL_ENTRY(0xb56), TBL_ENTRY(0xb57),
+	TBL_ENTRY(0xb58), TBL_ENTRY(0xb59), TBL_ENTRY(0xb5a), TBL_ENTRY(0xb5b),
+	TBL_ENTRY(0xb5c), TBL_ENTRY(0xb5d), TBL_ENTRY(0xb5e), TBL_ENTRY(0xb5f),
+	TBL_ENTRY(0xb60), TBL_ENTRY(0xb61), TBL_ENTRY(0xb62), TBL_ENTRY(0xb63),
+	TBL_ENTRY(0xb64), TBL_ENTRY(0xb65), TBL_ENTRY(0xb66), TBL_ENTRY(0xb67),
+	TBL_ENTRY(0xb68), TBL_ENTRY(0xb69), TBL_ENTRY(0xb6a), TBL_ENTRY(0xb6b),
+	TBL_ENTRY(0xb6c), TBL_ENTRY(0xb6d), TBL_ENTRY(0xb6e), TBL_ENTRY(0xb6f),
+	TBL_ENTRY(0xb70), TBL_ENTRY(0xb71), TBL_ENTRY(0xb72), TBL_ENTRY(0xb73),
+	TBL_ENTRY(0xb74), TBL_ENTRY(0xb75), TBL_ENTRY(0xb76), TBL_ENTRY(0xb77),
+	TBL_ENTRY(0xb78), TBL_ENTRY(0xb79), TBL_ENTRY(0xb7a), TBL_ENTRY(0xb7b),
+	TBL_ENTRY(0xb7c), TBL_ENTRY(0xb7d), TBL_ENTRY(0xb7e), TBL_ENTRY(0xb7f),
+	TBL_ENTRY(0xb80), TBL_ENTRY(0xb81), TBL_ENTRY(0xb82), TBL_ENTRY(0xb83),
+	TBL_ENTRY(0xb84), TBL_ENTRY(0xb85), TBL_ENTRY(0xb86), TBL_ENTRY(0xb87),
+	TBL_ENTRY(0xb88), TBL_ENTRY(0xb89), TBL_ENTRY(0xb8a), TBL_ENTRY(0xb8b),
+	TBL_ENTRY(0xb8c), TBL_ENTRY(0xb8d), TBL_ENTRY(0xb8e), TBL_ENTRY(0xb8f),
+	TBL_ENTRY(0xb90), TBL_ENTRY(0xb91), TBL_ENTRY(0xb92), TBL_ENTRY(0xb93),
+	TBL_ENTRY(0xb94), TBL_ENTRY(0xb95), TBL_ENTRY(0xb96), TBL_ENTRY(0xb97),
+	TBL_ENTRY(0xb98), TBL_ENTRY(0xb99), TBL_ENTRY(0xb9a), TBL_ENTRY(0xb9b),
+	TBL_ENTRY(0xb9c), TBL_ENTRY(0xb9d), TBL_ENTRY(0xb9e), TBL_ENTRY(0xb9f),
+	TBL_ENTRY(0xba0), TBL_ENTRY(0xba1), TBL_ENTRY(0xba2), TBL_ENTRY(0xba3),
+	TBL_ENTRY(0xba4), TBL_ENTRY(0xba5), TBL_ENTRY(0xba6), TBL_ENTRY(0xba7),
+	TBL_ENTRY(0xba8), TBL_ENTRY(0xba9), TBL_ENTRY(0xbaa), TBL_ENTRY(0xbab),
+	TBL_ENTRY(0xbac), TBL_ENTRY(0xbad), TBL_ENTRY(0xbae), TBL_ENTRY(0xbaf),
+	TBL_ENTRY(0xbb0), TBL_ENTRY(0xbb1), TBL_ENTRY(0xbb2), TBL_ENTRY(0xbb3),
+	TBL_ENTRY(0xbb4), TBL_ENTRY(0xbb5), TBL_ENTRY(0xbb6), TBL_ENTRY(0xbb7),
+	TBL_ENTRY(0xbb8), TBL_ENTRY(0xbb9), TBL_ENTRY(0xbba), TBL_ENTRY(0xbbb),
+	TBL_ENTRY(0xbbc), TBL_ENTRY(0xbbd), TBL_ENTRY(0xbbe), TBL_ENTRY(0xbbf),
+	TBL_ENTRY(0xbc0), TBL_ENTRY(0xbc1), TBL_ENTRY(0xbc2), TBL_ENTRY(0xbc3),
+	TBL_ENTRY(0xbc4), TBL_ENTRY(0xbc5), TBL_ENTRY(0xbc6), TBL_ENTRY(0xbc7),
+	TBL_ENTRY(0xbc8), TBL_ENTRY(0xbc9), TBL_ENTRY(0xbca), TBL_ENTRY(0xbcb),
+	TBL_ENTRY(0xbcc), TBL_ENTRY(0xbcd), TBL_ENTRY(0xbce), TBL_ENTRY(0xbcf),
+	TBL_ENTRY(0xbd0), TBL_ENTRY(0xbd1), TBL_ENTRY(0xbd2), TBL_ENTRY(0xbd3),
+	TBL_ENTRY(0xbd4), TBL_ENTRY(0xbd5), TBL_ENTRY(0xbd6), TBL_ENTRY(0xbd7),
+	TBL_ENTRY(0xbd8), TBL_ENTRY(0xbd9), TBL_ENTRY(0xbda), TBL_ENTRY(0xbdb),
+	TBL_ENTRY(0xbdc), TBL_ENTRY(0xbdd), TBL_ENTRY(0xbde), TBL_ENTRY(0xbdf),
+	TBL_ENTRY(0xbe0), TBL_ENTRY(0xbe1), TBL_ENTRY(0xbe2), TBL_ENTRY(0xbe3),
+	TBL_ENTRY(0xbe4), TBL_ENTRY(0xbe5), TBL_ENTRY(0xbe6), TBL_ENTRY(0xbe7),
+	TBL_ENTRY(0xbe8), TBL_ENTRY(0xbe9), TBL_ENTRY(0xbea), TBL_ENTRY(0xbeb),
+	TBL_ENTRY(0xbec), TBL_ENTRY(0xbed), TBL_ENTRY(0xbee), TBL_ENTRY(0xbef),
+	TBL_ENTRY(0xbf0), TBL_ENTRY(0xbf1), TBL_ENTRY(0xbf2), TBL_ENTRY(0xbf3),
+	TBL_ENTRY(0xbf4), TBL_ENTRY(0xbf5), TBL_ENTRY(0xbf6), TBL_ENTRY(0xbf7),
+	TBL_ENTRY(0xbf8), TBL_ENTRY(0xbf9), TBL_ENTRY(0xbfa), TBL_ENTRY(0xbfb),
+	TBL_ENTRY(0xbfc), TBL_ENTRY(0xbfd), TBL_ENTRY(0xbfe), TBL_ENTRY(0xbff),
+	TBL_ENTRY(0xc00), TBL_ENTRY(0xc01), TBL_ENTRY(0xc02), TBL_ENTRY(0xc03),
+	TBL_ENTRY(0xc04), TBL_ENTRY(0xc05), TBL_ENTRY(0xc06), TBL_ENTRY(0xc07),
+	TBL_ENTRY(0xc08), TBL_ENTRY(0xc09), TBL_ENTRY(0xc0a), TBL_ENTRY(0xc0b),
+	TBL_ENTRY(0xc0c), TBL_ENTRY(0xc0d), TBL_ENTRY(0xc0e), TBL_ENTRY(0xc0f),
+	TBL_ENTRY(0xc10), TBL_ENTRY(0xc11), TBL_ENTRY(0xc12), TBL_ENTRY(0xc13),
+	TBL_ENTRY(0xc14), TBL_ENTRY(0xc15), TBL_ENTRY(0xc16), TBL_ENTRY(0xc17),
+	TBL_ENTRY(0xc18), TBL_ENTRY(0xc19), TBL_ENTRY(0xc1a), TBL_ENTRY(0xc1b),
+	TBL_ENTRY(0xc1c), TBL_ENTRY(0xc1d), TBL_ENTRY(0xc1e), TBL_ENTRY(0xc1f),
+	TBL_ENTRY(0xc20), TBL_ENTRY(0xc21), TBL_ENTRY(0xc22), TBL_ENTRY(0xc23),
+	TBL_ENTRY(0xc24), TBL_ENTRY(0xc25), TBL_ENTRY(0xc26), TBL_ENTRY(0xc27),
+	TBL_ENTRY(0xc28), TBL_ENTRY(0xc29), TBL_ENTRY(0xc2a), TBL_ENTRY(0xc2b),
+	TBL_ENTRY(0xc2c), TBL_ENTRY(0xc2d), TBL_ENTRY(0xc2e), TBL_ENTRY(0xc2f),
+	TBL_ENTRY(0xc30), TBL_ENTRY(0xc31), TBL_ENTRY(0xc32), TBL_ENTRY(0xc33),
+	TBL_ENTRY(0xc34), TBL_ENTRY(0xc35), TBL_ENTRY(0xc36), TBL_ENTRY(0xc37),
+	TBL_ENTRY(0xc38), TBL_ENTRY(0xc39), TBL_ENTRY(0xc3a), TBL_ENTRY(0xc3b),
+	TBL_ENTRY(0xc3c), TBL_ENTRY(0xc3d), TBL_ENTRY(0xc3e), TBL_ENTRY(0xc3f),
+	TBL_ENTRY(0xc40), TBL_ENTRY(0xc41), TBL_ENTRY(0xc42), TBL_ENTRY(0xc43),
+	TBL_ENTRY(0xc44), TBL_ENTRY(0xc45), TBL_ENTRY(0xc46), TBL_ENTRY(0xc47),
+	TBL_ENTRY(0xc48), TBL_ENTRY(0xc49), TBL_ENTRY(0xc4a), TBL_ENTRY(0xc4b),
+	TBL_ENTRY(0xc4c), TBL_ENTRY(0xc4d), TBL_ENTRY(0xc4e), TBL_ENTRY(0xc4f),
+	TBL_ENTRY(0xc50), TBL_ENTRY(0xc51), TBL_ENTRY(0xc52), TBL_ENTRY(0xc53),
+	TBL_ENTRY(0xc54), TBL_ENTRY(0xc55), TBL_ENTRY(0xc56), TBL_ENTRY(0xc57),
+	TBL_ENTRY(0xc58), TBL_ENTRY(0xc59), TBL_ENTRY(0xc5a), TBL_ENTRY(0xc5b),
+	TBL_ENTRY(0xc5c), TBL_ENTRY(0xc5d), TBL_ENTRY(0xc5e), TBL_ENTRY(0xc5f),
+	TBL_ENTRY(0xc60), TBL_ENTRY(0xc61), TBL_ENTRY(0xc62), TBL_ENTRY(0xc63),
+	TBL_ENTRY(0xc64), TBL_ENTRY(0xc65), TBL_ENTRY(0xc66), TBL_ENTRY(0xc67),
+	TBL_ENTRY(0xc68), TBL_ENTRY(0xc69), TBL_ENTRY(0xc6a), TBL_ENTRY(0xc6b),
+	TBL_ENTRY(0xc6c), TBL_ENTRY(0xc6d), TBL_ENTRY(0xc6e), TBL_ENTRY(0xc6f),
+	TBL_ENTRY(0xc70), TBL_ENTRY(0xc71), TBL_ENTRY(0xc72), TBL_ENTRY(0xc73),
+	TBL_ENTRY(0xc74), TBL_ENTRY(0xc75), TBL_ENTRY(0xc76), TBL_ENTRY(0xc77),
+	TBL_ENTRY(0xc78), TBL_ENTRY(0xc79), TBL_ENTRY(0xc7a), TBL_ENTRY(0xc7b),
+	TBL_ENTRY(0xc7c), TBL_ENTRY(0xc7d), TBL_ENTRY(0xc7e), TBL_ENTRY(0xc7f),
+	TBL_ENTRY(0xc80), TBL_ENTRY(0xc81), TBL_ENTRY(0xc82), TBL_ENTRY(0xc83),
+	TBL_ENTRY(0xc84), TBL_ENTRY(0xc85), TBL_ENTRY(0xc86), TBL_ENTRY(0xc87),
+	TBL_ENTRY(0xc88), TBL_ENTRY(0xc89), TBL_ENTRY(0xc8a), TBL_ENTRY(0xc8b),
+	TBL_ENTRY(0xc8c), TBL_ENTRY(0xc8d), TBL_ENTRY(0xc8e), TBL_ENTRY(0xc8f),
+	TBL_ENTRY(0xc90), TBL_ENTRY(0xc91), TBL_ENTRY(0xc92), TBL_ENTRY(0xc93),
+	TBL_ENTRY(0xc94), TBL_ENTRY(0xc95), TBL_ENTRY(0xc96), TBL_ENTRY(0xc97),
+	TBL_ENTRY(0xc98), TBL_ENTRY(0xc99), TBL_ENTRY(0xc9a), TBL_ENTRY(0xc9b),
+	TBL_ENTRY(0xc9c), TBL_ENTRY(0xc9d), TBL_ENTRY(0xc9e), TBL_ENTRY(0xc9f),
+	TBL_ENTRY(0xca0), TBL_ENTRY(0xca1), TBL_ENTRY(0xca2), TBL_ENTRY(0xca3),
+	TBL_ENTRY(0xca4), TBL_ENTRY(0xca5), TBL_ENTRY(0xca6), TBL_ENTRY(0xca7),
+	TBL_ENTRY(0xca8), TBL_ENTRY(0xca9), TBL_ENTRY(0xcaa), TBL_ENTRY(0xcab),
+	TBL_ENTRY(0xcac), TBL_ENTRY(0xcad), TBL_ENTRY(0xcae), TBL_ENTRY(0xcaf),
+	TBL_ENTRY(0xcb0), TBL_ENTRY(0xcb1), TBL_ENTRY(0xcb2), TBL_ENTRY(0xcb3),
+	TBL_ENTRY(0xcb4), TBL_ENTRY(0xcb5), TBL_ENTRY(0xcb6), TBL_ENTRY(0xcb7),
+	TBL_ENTRY(0xcb8), TBL_ENTRY(0xcb9), TBL_ENTRY(0xcba), TBL_ENTRY(0xcbb),
+	TBL_ENTRY(0xcbc), TBL_ENTRY(0xcbd), TBL_ENTRY(0xcbe), TBL_ENTRY(0xcbf),
+	TBL_ENTRY(0xcc0), TBL_ENTRY(0xcc1), TBL_ENTRY(0xcc2), TBL_ENTRY(0xcc3),
+	TBL_ENTRY(0xcc4), TBL_ENTRY(0xcc5), TBL_ENTRY(0xcc6), TBL_ENTRY(0xcc7),
+	TBL_ENTRY(0xcc8), TBL_ENTRY(0xcc9), TBL_ENTRY(0xcca), TBL_ENTRY(0xccb),
+	TBL_ENTRY(0xccc), TBL_ENTRY(0xccd), TBL_ENTRY(0xcce), TBL_ENTRY(0xccf),
+	TBL_ENTRY(0xcd0), TBL_ENTRY(0xcd1), TBL_ENTRY(0xcd2), TBL_ENTRY(0xcd3),
+	TBL_ENTRY(0xcd4), TBL_ENTRY(0xcd5), TBL_ENTRY(0xcd6), TBL_ENTRY(0xcd7),
+	TBL_ENTRY(0xcd8), TBL_ENTRY(0xcd9), TBL_ENTRY(0xcda), TBL_ENTRY(0xcdb),
+	TBL_ENTRY(0xcdc), TBL_ENTRY(0xcdd), TBL_ENTRY(0xcde), TBL_ENTRY(0xcdf),
+	TBL_ENTRY(0xce0), TBL_ENTRY(0xce1), TBL_ENTRY(0xce2), TBL_ENTRY(0xce3),
+	TBL_ENTRY(0xce4), TBL_ENTRY(0xce5), TBL_ENTRY(0xce6), TBL_ENTRY(0xce7),
+	TBL_ENTRY(0xce8), TBL_ENTRY(0xce9), TBL_ENTRY(0xcea), TBL_ENTRY(0xceb),
+	TBL_ENTRY(0xcec), TBL_ENTRY(0xced), TBL_ENTRY(0xcee), TBL_ENTRY(0xcef),
+	TBL_ENTRY(0xcf0), TBL_ENTRY(0xcf1), TBL_ENTRY(0xcf2), TBL_ENTRY(0xcf3),
+	TBL_ENTRY(0xcf4), TBL_ENTRY(0xcf5), TBL_ENTRY(0xcf6), TBL_ENTRY(0xcf7),
+	TBL_ENTRY(0xcf8), TBL_ENTRY(0xcf9), TBL_ENTRY(0xcfa), TBL_ENTRY(0xcfb),
+	TBL_ENTRY(0xcfc), TBL_ENTRY(0xcfd), TBL_ENTRY(0xcfe), TBL_ENTRY(0xcff),
+	TBL_ENTRY(0xd00), TBL_ENTRY(0xd01), TBL_ENTRY(0xd02), TBL_ENTRY(0xd03),
+	TBL_ENTRY(0xd04), TBL_ENTRY(0xd05), TBL_ENTRY(0xd06), TBL_ENTRY(0xd07),
+	TBL_ENTRY(0xd08), TBL_ENTRY(0xd09), TBL_ENTRY(0xd0a), TBL_ENTRY(0xd0b),
+	TBL_ENTRY(0xd0c), TBL_ENTRY(0xd0d), TBL_ENTRY(0xd0e), TBL_ENTRY(0xd0f),
+	TBL_ENTRY(0xd10), TBL_ENTRY(0xd11), TBL_ENTRY(0xd12), TBL_ENTRY(0xd13),
+	TBL_ENTRY(0xd14), TBL_ENTRY(0xd15), TBL_ENTRY(0xd16), TBL_ENTRY(0xd17),
+	TBL_ENTRY(0xd18), TBL_ENTRY(0xd19), TBL_ENTRY(0xd1a), TBL_ENTRY(0xd1b),
+	TBL_ENTRY(0xd1c), TBL_ENTRY(0xd1d), TBL_ENTRY(0xd1e), TBL_ENTRY(0xd1f),
+	TBL_ENTRY(0xd20), TBL_ENTRY(0xd21), TBL_ENTRY(0xd22), TBL_ENTRY(0xd23),
+	TBL_ENTRY(0xd24), TBL_ENTRY(0xd25), TBL_ENTRY(0xd26), TBL_ENTRY(0xd27),
+	TBL_ENTRY(0xd28), TBL_ENTRY(0xd29), TBL_ENTRY(0xd2a), TBL_ENTRY(0xd2b),
+	TBL_ENTRY(0xd2c), TBL_ENTRY(0xd2d), TBL_ENTRY(0xd2e), TBL_ENTRY(0xd2f),
+	TBL_ENTRY(0xd30), TBL_ENTRY(0xd31), TBL_ENTRY(0xd32), TBL_ENTRY(0xd33),
+	TBL_ENTRY(0xd34), TBL_ENTRY(0xd35), TBL_ENTRY(0xd36), TBL_ENTRY(0xd37),
+	TBL_ENTRY(0xd38), TBL_ENTRY(0xd39), TBL_ENTRY(0xd3a), TBL_ENTRY(0xd3b),
+	TBL_ENTRY(0xd3c), TBL_ENTRY(0xd3d), TBL_ENTRY(0xd3e), TBL_ENTRY(0xd3f),
+	TBL_ENTRY(0xd40), TBL_ENTRY(0xd41), TBL_ENTRY(0xd42), TBL_ENTRY(0xd43),
+	TBL_ENTRY(0xd44), TBL_ENTRY(0xd45), TBL_ENTRY(0xd46), TBL_ENTRY(0xd47),
+	TBL_ENTRY(0xd48), TBL_ENTRY(0xd49), TBL_ENTRY(0xd4a), TBL_ENTRY(0xd4b),
+	TBL_ENTRY(0xd4c), TBL_ENTRY(0xd4d), TBL_ENTRY(0xd4e), TBL_ENTRY(0xd4f),
+	TBL_ENTRY(0xd50), TBL_ENTRY(0xd51), TBL_ENTRY(0xd52), TBL_ENTRY(0xd53),
+	TBL_ENTRY(0xd54), TBL_ENTRY(0xd55), TBL_ENTRY(0xd56), TBL_ENTRY(0xd57),
+	TBL_ENTRY(0xd58), TBL_ENTRY(0xd59), TBL_ENTRY(0xd5a), TBL_ENTRY(0xd5b),
+	TBL_ENTRY(0xd5c), TBL_ENTRY(0xd5d), TBL_ENTRY(0xd5e), TBL_ENTRY(0xd5f),
+	TBL_ENTRY(0xd60), TBL_ENTRY(0xd61), TBL_ENTRY(0xd62), TBL_ENTRY(0xd63),
+	TBL_ENTRY(0xd64), TBL_ENTRY(0xd65), TBL_ENTRY(0xd66), TBL_ENTRY(0xd67),
+	TBL_ENTRY(0xd68), TBL_ENTRY(0xd69), TBL_ENTRY(0xd6a), TBL_ENTRY(0xd6b),
+	TBL_ENTRY(0xd6c), TBL_ENTRY(0xd6d), TBL_ENTRY(0xd6e), TBL_ENTRY(0xd6f),
+	TBL_ENTRY(0xd70), TBL_ENTRY(0xd71), TBL_ENTRY(0xd72), TBL_ENTRY(0xd73),
+	TBL_ENTRY(0xd74), TBL_ENTRY(0xd75), TBL_ENTRY(0xd76), TBL_ENTRY(0xd77),
+	TBL_ENTRY(0xd78), TBL_ENTRY(0xd79), TBL_ENTRY(0xd7a), TBL_ENTRY(0xd7b),
+	TBL_ENTRY(0xd7c), TBL_ENTRY(0xd7d), TBL_ENTRY(0xd7e), TBL_ENTRY(0xd7f),
+	TBL_ENTRY(0xd80), TBL_ENTRY(0xd81), TBL_ENTRY(0xd82), TBL_ENTRY(0xd83),
+	TBL_ENTRY(0xd84), TBL_ENTRY(0xd85), TBL_ENTRY(0xd86), TBL_ENTRY(0xd87),
+	TBL_ENTRY(0xd88), TBL_ENTRY(0xd89), TBL_ENTRY(0xd8a), TBL_ENTRY(0xd8b),
+	TBL_ENTRY(0xd8c), TBL_ENTRY(0xd8d), TBL_ENTRY(0xd8e), TBL_ENTRY(0xd8f),
+	TBL_ENTRY(0xd90), TBL_ENTRY(0xd91), TBL_ENTRY(0xd92), TBL_ENTRY(0xd93),
+	TBL_ENTRY(0xd94), TBL_ENTRY(0xd95), TBL_ENTRY(0xd96), TBL_ENTRY(0xd97),
+	TBL_ENTRY(0xd98), TBL_ENTRY(0xd99), TBL_ENTRY(0xd9a), TBL_ENTRY(0xd9b),
+	TBL_ENTRY(0xd9c), TBL_ENTRY(0xd9d), TBL_ENTRY(0xd9e), TBL_ENTRY(0xd9f),
+	TBL_ENTRY(0xda0), TBL_ENTRY(0xda1), TBL_ENTRY(0xda2), TBL_ENTRY(0xda3),
+	TBL_ENTRY(0xda4), TBL_ENTRY(0xda5), TBL_ENTRY(0xda6), TBL_ENTRY(0xda7),
+	TBL_ENTRY(0xda8), TBL_ENTRY(0xda9), TBL_ENTRY(0xdaa), TBL_ENTRY(0xdab),
+	TBL_ENTRY(0xdac), TBL_ENTRY(0xdad), TBL_ENTRY(0xdae), TBL_ENTRY(0xdaf),
+	TBL_ENTRY(0xdb0), TBL_ENTRY(0xdb1), TBL_ENTRY(0xdb2), TBL_ENTRY(0xdb3),
+	TBL_ENTRY(0xdb4), TBL_ENTRY(0xdb5), TBL_ENTRY(0xdb6), TBL_ENTRY(0xdb7),
+	TBL_ENTRY(0xdb8), TBL_ENTRY(0xdb9), TBL_ENTRY(0xdba), TBL_ENTRY(0xdbb),
+	TBL_ENTRY(0xdbc), TBL_ENTRY(0xdbd), TBL_ENTRY(0xdbe), TBL_ENTRY(0xdbf),
+	TBL_ENTRY(0xdc0), TBL_ENTRY(0xdc1), TBL_ENTRY(0xdc2), TBL_ENTRY(0xdc3),
+	TBL_ENTRY(0xdc4), TBL_ENTRY(0xdc5), TBL_ENTRY(0xdc6), TBL_ENTRY(0xdc7),
+	TBL_ENTRY(0xdc8), TBL_ENTRY(0xdc9), TBL_ENTRY(0xdca), TBL_ENTRY(0xdcb),
+	TBL_ENTRY(0xdcc), TBL_ENTRY(0xdcd), TBL_ENTRY(0xdce), TBL_ENTRY(0xdcf),
+	TBL_ENTRY(0xdd0), TBL_ENTRY(0xdd1), TBL_ENTRY(0xdd2), TBL_ENTRY(0xdd3),
+	TBL_ENTRY(0xdd4), TBL_ENTRY(0xdd5), TBL_ENTRY(0xdd6), TBL_ENTRY(0xdd7),
+	TBL_ENTRY(0xdd8), TBL_ENTRY(0xdd9), TBL_ENTRY(0xdda), TBL_ENTRY(0xddb),
+	TBL_ENTRY(0xddc), TBL_ENTRY(0xddd), TBL_ENTRY(0xdde), TBL_ENTRY(0xddf),
+	TBL_ENTRY(0xde0), TBL_ENTRY(0xde1), TBL_ENTRY(0xde2), TBL_ENTRY(0xde3),
+	TBL_ENTRY(0xde4), TBL_ENTRY(0xde5), TBL_ENTRY(0xde6), TBL_ENTRY(0xde7),
+	TBL_ENTRY(0xde8), TBL_ENTRY(0xde9), TBL_ENTRY(0xdea), TBL_ENTRY(0xdeb),
+	TBL_ENTRY(0xdec), TBL_ENTRY(0xded), TBL_ENTRY(0xdee), TBL_ENTRY(0xdef),
+	TBL_ENTRY(0xdf0), TBL_ENTRY(0xdf1), TBL_ENTRY(0xdf2), TBL_ENTRY(0xdf3),
+	TBL_ENTRY(0xdf4), TBL_ENTRY(0xdf5), TBL_ENTRY(0xdf6), TBL_ENTRY(0xdf7),
+	TBL_ENTRY(0xdf8), TBL_ENTRY(0xdf9), TBL_ENTRY(0xdfa), TBL_ENTRY(0xdfb),
+	TBL_ENTRY(0xdfc), TBL_ENTRY(0xdfd), TBL_ENTRY(0xdfe), TBL_ENTRY(0xdff),
+	TBL_ENTRY(0xe00), TBL_ENTRY(0xe01), TBL_ENTRY(0xe02), TBL_ENTRY(0xe03),
+	TBL_ENTRY(0xe04), TBL_ENTRY(0xe05), TBL_ENTRY(0xe06), TBL_ENTRY(0xe07),
+	TBL_ENTRY(0xe08), TBL_ENTRY(0xe09), TBL_ENTRY(0xe0a), TBL_ENTRY(0xe0b),
+	TBL_ENTRY(0xe0c), TBL_ENTRY(0xe0d), TBL_ENTRY(0xe0e), TBL_ENTRY(0xe0f),
+	TBL_ENTRY(0xe10), TBL_ENTRY(0xe11), TBL_ENTRY(0xe12), TBL_ENTRY(0xe13),
+	TBL_ENTRY(0xe14), TBL_ENTRY(0xe15), TBL_ENTRY(0xe16), TBL_ENTRY(0xe17),
+	TBL_ENTRY(0xe18), TBL_ENTRY(0xe19), TBL_ENTRY(0xe1a), TBL_ENTRY(0xe1b),
+	TBL_ENTRY(0xe1c), TBL_ENTRY(0xe1d), TBL_ENTRY(0xe1e), TBL_ENTRY(0xe1f),
+	TBL_ENTRY(0xe20), TBL_ENTRY(0xe21), TBL_ENTRY(0xe22), TBL_ENTRY(0xe23),
+	TBL_ENTRY(0xe24), TBL_ENTRY(0xe25), TBL_ENTRY(0xe26), TBL_ENTRY(0xe27),
+	TBL_ENTRY(0xe28), TBL_ENTRY(0xe29), TBL_ENTRY(0xe2a), TBL_ENTRY(0xe2b),
+	TBL_ENTRY(0xe2c), TBL_ENTRY(0xe2d), TBL_ENTRY(0xe2e), TBL_ENTRY(0xe2f),
+	TBL_ENTRY(0xe30), TBL_ENTRY(0xe31), TBL_ENTRY(0xe32), TBL_ENTRY(0xe33),
+	TBL_ENTRY(0xe34), TBL_ENTRY(0xe35), TBL_ENTRY(0xe36), TBL_ENTRY(0xe37),
+	TBL_ENTRY(0xe38), TBL_ENTRY(0xe39), TBL_ENTRY(0xe3a), TBL_ENTRY(0xe3b),
+	TBL_ENTRY(0xe3c), TBL_ENTRY(0xe3d), TBL_ENTRY(0xe3e), TBL_ENTRY(0xe3f),
+	TBL_ENTRY(0xe40), TBL_ENTRY(0xe41), TBL_ENTRY(0xe42), TBL_ENTRY(0xe43),
+	TBL_ENTRY(0xe44), TBL_ENTRY(0xe45), TBL_ENTRY(0xe46), TBL_ENTRY(0xe47),
+	TBL_ENTRY(0xe48), TBL_ENTRY(0xe49), TBL_ENTRY(0xe4a), TBL_ENTRY(0xe4b),
+	TBL_ENTRY(0xe4c), TBL_ENTRY(0xe4d), TBL_ENTRY(0xe4e), TBL_ENTRY(0xe4f),
+	TBL_ENTRY(0xe50), TBL_ENTRY(0xe51), TBL_ENTRY(0xe52), TBL_ENTRY(0xe53),
+	TBL_ENTRY(0xe54), TBL_ENTRY(0xe55), TBL_ENTRY(0xe56), TBL_ENTRY(0xe57),
+	TBL_ENTRY(0xe58), TBL_ENTRY(0xe59), TBL_ENTRY(0xe5a), TBL_ENTRY(0xe5b),
+	TBL_ENTRY(0xe5c), TBL_ENTRY(0xe5d), TBL_ENTRY(0xe5e), TBL_ENTRY(0xe5f),
+	TBL_ENTRY(0xe60), TBL_ENTRY(0xe61), TBL_ENTRY(0xe62), TBL_ENTRY(0xe63),
+	TBL_ENTRY(0xe64), TBL_ENTRY(0xe65), TBL_ENTRY(0xe66), TBL_ENTRY(0xe67),
+	TBL_ENTRY(0xe68), TBL_ENTRY(0xe69), TBL_ENTRY(0xe6a), TBL_ENTRY(0xe6b),
+	TBL_ENTRY(0xe6c), TBL_ENTRY(0xe6d), TBL_ENTRY(0xe6e), TBL_ENTRY(0xe6f),
+	TBL_ENTRY(0xe70), TBL_ENTRY(0xe71), TBL_ENTRY(0xe72), TBL_ENTRY(0xe73),
+	TBL_ENTRY(0xe74), TBL_ENTRY(0xe75), TBL_ENTRY(0xe76), TBL_ENTRY(0xe77),
+	TBL_ENTRY(0xe78), TBL_ENTRY(0xe79), TBL_ENTRY(0xe7a), TBL_ENTRY(0xe7b),
+	TBL_ENTRY(0xe7c), TBL_ENTRY(0xe7d), TBL_ENTRY(0xe7e), TBL_ENTRY(0xe7f),
+	TBL_ENTRY(0xe80), TBL_ENTRY(0xe81), TBL_ENTRY(0xe82), TBL_ENTRY(0xe83),
+	TBL_ENTRY(0xe84), TBL_ENTRY(0xe85), TBL_ENTRY(0xe86), TBL_ENTRY(0xe87),
+	TBL_ENTRY(0xe88), TBL_ENTRY(0xe89), TBL_ENTRY(0xe8a), TBL_ENTRY(0xe8b),
+	TBL_ENTRY(0xe8c), TBL_ENTRY(0xe8d), TBL_ENTRY(0xe8e), TBL_ENTRY(0xe8f),
+	TBL_ENTRY(0xe90), TBL_ENTRY(0xe91), TBL_ENTRY(0xe92), TBL_ENTRY(0xe93),
+	TBL_ENTRY(0xe94), TBL_ENTRY(0xe95), TBL_ENTRY(0xe96), TBL_ENTRY(0xe97),
+	TBL_ENTRY(0xe98), TBL_ENTRY(0xe99), TBL_ENTRY(0xe9a), TBL_ENTRY(0xe9b),
+	TBL_ENTRY(0xe9c), TBL_ENTRY(0xe9d), TBL_ENTRY(0xe9e), TBL_ENTRY(0xe9f),
+	TBL_ENTRY(0xea0), TBL_ENTRY(0xea1), TBL_ENTRY(0xea2), TBL_ENTRY(0xea3),
+	TBL_ENTRY(0xea4), TBL_ENTRY(0xea5), TBL_ENTRY(0xea6), TBL_ENTRY(0xea7),
+	TBL_ENTRY(0xea8), TBL_ENTRY(0xea9), TBL_ENTRY(0xeaa), TBL_ENTRY(0xeab),
+	TBL_ENTRY(0xeac), TBL_ENTRY(0xead), TBL_ENTRY(0xeae), TBL_ENTRY(0xeaf),
+	TBL_ENTRY(0xeb0), TBL_ENTRY(0xeb1), TBL_ENTRY(0xeb2), TBL_ENTRY(0xeb3),
+	TBL_ENTRY(0xeb4), TBL_ENTRY(0xeb5), TBL_ENTRY(0xeb6), TBL_ENTRY(0xeb7),
+	TBL_ENTRY(0xeb8), TBL_ENTRY(0xeb9), TBL_ENTRY(0xeba), TBL_ENTRY(0xebb),
+	TBL_ENTRY(0xebc), TBL_ENTRY(0xebd), TBL_ENTRY(0xebe), TBL_ENTRY(0xebf),
+	TBL_ENTRY(0xec0), TBL_ENTRY(0xec1), TBL_ENTRY(0xec2), TBL_ENTRY(0xec3),
+	TBL_ENTRY(0xec4), TBL_ENTRY(0xec5), TBL_ENTRY(0xec6), TBL_ENTRY(0xec7),
+	TBL_ENTRY(0xec8), TBL_ENTRY(0xec9), TBL_ENTRY(0xeca), TBL_ENTRY(0xecb),
+	TBL_ENTRY(0xecc), TBL_ENTRY(0xecd), TBL_ENTRY(0xece), TBL_ENTRY(0xecf),
+	TBL_ENTRY(0xed0), TBL_ENTRY(0xed1), TBL_ENTRY(0xed2), TBL_ENTRY(0xed3),
+	TBL_ENTRY(0xed4), TBL_ENTRY(0xed5), TBL_ENTRY(0xed6), TBL_ENTRY(0xed7),
+	TBL_ENTRY(0xed8), TBL_ENTRY(0xed9), TBL_ENTRY(0xeda), TBL_ENTRY(0xedb),
+	TBL_ENTRY(0xedc), TBL_ENTRY(0xedd), TBL_ENTRY(0xede), TBL_ENTRY(0xedf),
+	TBL_ENTRY(0xee0), TBL_ENTRY(0xee1), TBL_ENTRY(0xee2), TBL_ENTRY(0xee3),
+	TBL_ENTRY(0xee4), TBL_ENTRY(0xee5), TBL_ENTRY(0xee6), TBL_ENTRY(0xee7),
+	TBL_ENTRY(0xee8), TBL_ENTRY(0xee9), TBL_ENTRY(0xeea), TBL_ENTRY(0xeeb),
+	TBL_ENTRY(0xeec), TBL_ENTRY(0xeed), TBL_ENTRY(0xeee), TBL_ENTRY(0xeef),
+	TBL_ENTRY(0xef0), TBL_ENTRY(0xef1), TBL_ENTRY(0xef2), TBL_ENTRY(0xef3),
+	TBL_ENTRY(0xef4), TBL_ENTRY(0xef5), TBL_ENTRY(0xef6), TBL_ENTRY(0xef7),
+	TBL_ENTRY(0xef8), TBL_ENTRY(0xef9), TBL_ENTRY(0xefa), TBL_ENTRY(0xefb),
+	TBL_ENTRY(0xefc), TBL_ENTRY(0xefd), TBL_ENTRY(0xefe), TBL_ENTRY(0xeff),
+	TBL_ENTRY(0xf00), TBL_ENTRY(0xf01), TBL_ENTRY(0xf02), TBL_ENTRY(0xf03),
+	TBL_ENTRY(0xf04), TBL_ENTRY(0xf05), TBL_ENTRY(0xf06), TBL_ENTRY(0xf07),
+	TBL_ENTRY(0xf08), TBL_ENTRY(0xf09), TBL_ENTRY(0xf0a), TBL_ENTRY(0xf0b),
+	TBL_ENTRY(0xf0c), TBL_ENTRY(0xf0d), TBL_ENTRY(0xf0e), TBL_ENTRY(0xf0f),
+	TBL_ENTRY(0xf10), TBL_ENTRY(0xf11), TBL_ENTRY(0xf12), TBL_ENTRY(0xf13),
+	TBL_ENTRY(0xf14), TBL_ENTRY(0xf15), TBL_ENTRY(0xf16), TBL_ENTRY(0xf17),
+	TBL_ENTRY(0xf18), TBL_ENTRY(0xf19), TBL_ENTRY(0xf1a), TBL_ENTRY(0xf1b),
+	TBL_ENTRY(0xf1c), TBL_ENTRY(0xf1d), TBL_ENTRY(0xf1e), TBL_ENTRY(0xf1f),
+	TBL_ENTRY(0xf20), TBL_ENTRY(0xf21), TBL_ENTRY(0xf22), TBL_ENTRY(0xf23),
+	TBL_ENTRY(0xf24), TBL_ENTRY(0xf25), TBL_ENTRY(0xf26), TBL_ENTRY(0xf27),
+	TBL_ENTRY(0xf28), TBL_ENTRY(0xf29), TBL_ENTRY(0xf2a), TBL_ENTRY(0xf2b),
+	TBL_ENTRY(0xf2c), TBL_ENTRY(0xf2d), TBL_ENTRY(0xf2e), TBL_ENTRY(0xf2f),
+	TBL_ENTRY(0xf30), TBL_ENTRY(0xf31), TBL_ENTRY(0xf32), TBL_ENTRY(0xf33),
+	TBL_ENTRY(0xf34), TBL_ENTRY(0xf35), TBL_ENTRY(0xf36), TBL_ENTRY(0xf37),
+	TBL_ENTRY(0xf38), TBL_ENTRY(0xf39), TBL_ENTRY(0xf3a), TBL_ENTRY(0xf3b),
+	TBL_ENTRY(0xf3c), TBL_ENTRY(0xf3d), TBL_ENTRY(0xf3e), TBL_ENTRY(0xf3f),
+	TBL_ENTRY(0xf40), TBL_ENTRY(0xf41), TBL_ENTRY(0xf42), TBL_ENTRY(0xf43),
+	TBL_ENTRY(0xf44), TBL_ENTRY(0xf45), TBL_ENTRY(0xf46), TBL_ENTRY(0xf47),
+	TBL_ENTRY(0xf48), TBL_ENTRY(0xf49), TBL_ENTRY(0xf4a), TBL_ENTRY(0xf4b),
+	TBL_ENTRY(0xf4c), TBL_ENTRY(0xf4d), TBL_ENTRY(0xf4e), TBL_ENTRY(0xf4f),
+	TBL_ENTRY(0xf50), TBL_ENTRY(0xf51), TBL_ENTRY(0xf52), TBL_ENTRY(0xf53),
+	TBL_ENTRY(0xf54), TBL_ENTRY(0xf55), TBL_ENTRY(0xf56), TBL_ENTRY(0xf57),
+	TBL_ENTRY(0xf58), TBL_ENTRY(0xf59), TBL_ENTRY(0xf5a), TBL_ENTRY(0xf5b),
+	TBL_ENTRY(0xf5c), TBL_ENTRY(0xf5d), TBL_ENTRY(0xf5e), TBL_ENTRY(0xf5f),
+	TBL_ENTRY(0xf60), TBL_ENTRY(0xf61), TBL_ENTRY(0xf62), TBL_ENTRY(0xf63),
+	TBL_ENTRY(0xf64), TBL_ENTRY(0xf65), TBL_ENTRY(0xf66), TBL_ENTRY(0xf67),
+	TBL_ENTRY(0xf68), TBL_ENTRY(0xf69), TBL_ENTRY(0xf6a), TBL_ENTRY(0xf6b),
+	TBL_ENTRY(0xf6c), TBL_ENTRY(0xf6d), TBL_ENTRY(0xf6e), TBL_ENTRY(0xf6f),
+	TBL_ENTRY(0xf70), TBL_ENTRY(0xf71), TBL_ENTRY(0xf72), TBL_ENTRY(0xf73),
+	TBL_ENTRY(0xf74), TBL_ENTRY(0xf75), TBL_ENTRY(0xf76), TBL_ENTRY(0xf77),
+	TBL_ENTRY(0xf78), TBL_ENTRY(0xf79), TBL_ENTRY(0xf7a), TBL_ENTRY(0xf7b),
+	TBL_ENTRY(0xf7c), TBL_ENTRY(0xf7d), TBL_ENTRY(0xf7e), TBL_ENTRY(0xf7f),
+	TBL_ENTRY(0xf80), TBL_ENTRY(0xf81), TBL_ENTRY(0xf82), TBL_ENTRY(0xf83),
+	TBL_ENTRY(0xf84), TBL_ENTRY(0xf85), TBL_ENTRY(0xf86), TBL_ENTRY(0xf87),
+	TBL_ENTRY(0xf88), TBL_ENTRY(0xf89), TBL_ENTRY(0xf8a), TBL_ENTRY(0xf8b),
+	TBL_ENTRY(0xf8c), TBL_ENTRY(0xf8d), TBL_ENTRY(0xf8e), TBL_ENTRY(0xf8f),
+	TBL_ENTRY(0xf90), TBL_ENTRY(0xf91), TBL_ENTRY(0xf92), TBL_ENTRY(0xf93),
+	TBL_ENTRY(0xf94), TBL_ENTRY(0xf95), TBL_ENTRY(0xf96), TBL_ENTRY(0xf97),
+	TBL_ENTRY(0xf98), TBL_ENTRY(0xf99), TBL_ENTRY(0xf9a), TBL_ENTRY(0xf9b),
+	TBL_ENTRY(0xf9c), TBL_ENTRY(0xf9d), TBL_ENTRY(0xf9e), TBL_ENTRY(0xf9f),
+	TBL_ENTRY(0xfa0), TBL_ENTRY(0xfa1), TBL_ENTRY(0xfa2), TBL_ENTRY(0xfa3),
+	TBL_ENTRY(0xfa4), TBL_ENTRY(0xfa5), TBL_ENTRY(0xfa6), TBL_ENTRY(0xfa7),
+	TBL_ENTRY(0xfa8), TBL_ENTRY(0xfa9), TBL_ENTRY(0xfaa), TBL_ENTRY(0xfab),
+	TBL_ENTRY(0xfac), TBL_ENTRY(0xfad), TBL_ENTRY(0xfae), TBL_ENTRY(0xfaf),
+	TBL_ENTRY(0xfb0), TBL_ENTRY(0xfb1), TBL_ENTRY(0xfb2), TBL_ENTRY(0xfb3),
+	TBL_ENTRY(0xfb4), TBL_ENTRY(0xfb5), TBL_ENTRY(0xfb6), TBL_ENTRY(0xfb7),
+	TBL_ENTRY(0xfb8), TBL_ENTRY(0xfb9), TBL_ENTRY(0xfba), TBL_ENTRY(0xfbb),
+	TBL_ENTRY(0xfbc), TBL_ENTRY(0xfbd), TBL_ENTRY(0xfbe), TBL_ENTRY(0xfbf),
+	TBL_ENTRY(0xfc0), TBL_ENTRY(0xfc1), TBL_ENTRY(0xfc2), TBL_ENTRY(0xfc3),
+	TBL_ENTRY(0xfc4), TBL_ENTRY(0xfc5), TBL_ENTRY(0xfc6), TBL_ENTRY(0xfc7),
+	TBL_ENTRY(0xfc8), TBL_ENTRY(0xfc9), TBL_ENTRY(0xfca), TBL_ENTRY(0xfcb),
+	TBL_ENTRY(0xfcc), TBL_ENTRY(0xfcd), TBL_ENTRY(0xfce), TBL_ENTRY(0xfcf),
+	TBL_ENTRY(0xfd0), TBL_ENTRY(0xfd1), TBL_ENTRY(0xfd2), TBL_ENTRY(0xfd3),
+	TBL_ENTRY(0xfd4), TBL_ENTRY(0xfd5), TBL_ENTRY(0xfd6), TBL_ENTRY(0xfd7),
+	TBL_ENTRY(0xfd8), TBL_ENTRY(0xfd9), TBL_ENTRY(0xfda), TBL_ENTRY(0xfdb),
+	TBL_ENTRY(0xfdc), TBL_ENTRY(0xfdd), TBL_ENTRY(0xfde), TBL_ENTRY(0xfdf),
+	TBL_ENTRY(0xfe0), TBL_ENTRY(0xfe1), TBL_ENTRY(0xfe2), TBL_ENTRY(0xfe3),
+	TBL_ENTRY(0xfe4), TBL_ENTRY(0xfe5), TBL_ENTRY(0xfe6), TBL_ENTRY(0xfe7),
+	TBL_ENTRY(0xfe8), TBL_ENTRY(0xfe9), TBL_ENTRY(0xfea), TBL_ENTRY(0xfeb),
+	TBL_ENTRY(0xfec), TBL_ENTRY(0xfed), TBL_ENTRY(0xfee), TBL_ENTRY(0xfef),
+	TBL_ENTRY(0xff0), TBL_ENTRY(0xff1), TBL_ENTRY(0xff2), TBL_ENTRY(0xff3),
+	TBL_ENTRY(0xff4), TBL_ENTRY(0xff5), TBL_ENTRY(0xff6), TBL_ENTRY(0xff7),
+	TBL_ENTRY(0xff8), TBL_ENTRY(0xff9), TBL_ENTRY(0xffa), TBL_ENTRY(0xffb),
+	TBL_ENTRY(0xffc), TBL_ENTRY(0xffd), TBL_ENTRY(0xffe), TBL_ENTRY(0xfff),
+};
diff --git a/arch/arm/cpu/armv7/uniphier/lowlevel_init.S b/arch/arm/cpu/armv7/uniphier/lowlevel_init.S
new file mode 100644
index 0000000000..0ea12d3cfc
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/lowlevel_init.S
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/system.h>
+#include <asm/arch/led.h>
+#include <asm/arch/arm-mpcore.h>
+#include <asm/arch/sbc-regs.h>
+
+ENTRY(lowlevel_init)
+	mov	r8, lr			@ persevere link reg across call
+
+	/*
+	 * The UniPhier Boot ROM loads SPL code to the L2 cache.
+	 * But CPUs can only do instruction fetch now because start.S has
+	 * cleared C and M bits.
+	 * First we need to turn on MMU and Dcache again to get back
+	 * data access to L2.
+	 */
+	mrc	p15, 0, r0, c1, c0, 0		@ SCTLR (System Contrl Register)
+	orr	r0, r0, #(CR_C | CR_M)		@ enable MMU and Dcache
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Now we are using the page table embedded in the Boot ROM.
+	 * It is not handy since it is not a straight mapped table for sLD3.
+	 * What we need to do next is to switch over to the page table in SPL.
+	 */
+	ldr	r3, =init_page_table	@ page table must be 16KB aligned
+
+	/* Disable MMU and Dcache before switching Page Table */
+	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Contrl Register)
+	bic	r0, r0, #(CR_C | CR_M)	@ disable MMU and Dcache
+	mcr	p15, 0, r0, c1, c0, 0
+
+	bl	enable_mmu
+
+#ifdef CONFIG_UNIPHIER_SMP
+	/*
+	 * ACTLR (Auxiliary Control Register) for Cortex-A9
+	 * bit[9]  Parity on
+	 * bit[8]  Alloc in one way
+	 * bit[7]  EXCL (Exclusive cache bit)
+	 * bit[6]  SMP
+	 * bit[3]  Write full line of zeros mode
+	 * bit[2]  L1 Prefetch enable
+	 * bit[1]  L2 prefetch enable
+	 * bit[0]  FW (Cache and TLB maintenance broadcast)
+	 */
+	mrc	p15, 0, r0, c1, c0, 1	@ ACTLR (Auxiliary Control Register)
+	orr	r0, r0, #0x41		@ enable SMP, FW bit
+	mcr	p15, 0, r0, c1, c0, 1
+
+	/* branch by CPU ID */
+	mrc	p15, 0, r0, c0, c0, 5	@ MPIDR (Multiprocessor Affinity Register)
+	and  	r0, r0, #0x3
+	cmp	r0, #0x0
+	beq	primary_cpu
+	ldr	r1, =ROM_BOOT_ROMRSV2
+	mov	r0, #0
+	str	r0, [r1]
+0:	wfe
+	ldr	r0, [r1]
+	cmp	r0, #0
+	beq	0b
+	bx	r0			@ r0: entry point of U-Boot main for the secondary CPU
+primary_cpu:
+	ldr	r1, =ROM_BOOT_ROMRSV2
+	ldr	r0, =_start		@ entry for the secondary CPU
+	str	r0, [r1]
+	ldr	r0, [r1]		@ make sure str is complete before sev
+	sev				@ kick the sedoncary CPU
+	mrc	p15, 4, r1, c15, c0, 0	@ Configuration Base Address Register
+	bfc	r1, #0, #13		@ clear bit 12-0
+	mov	r0, #-1
+	str	r0, [r1, #SCU_INV_ALL]	@ SCU Invalidate All Register
+	mov	r0, #1			@ SCU enable
+	str	r0, [r1, #SCU_CTRL]	@ SCU Control Register
+#endif
+
+	bl	setup_init_ram		@ RAM area for temporary stack pointer
+
+	mov	lr, r8			@ restore link
+	mov	pc, lr			@ back to my caller
+ENDPROC(lowlevel_init)
+
+ENTRY(enable_mmu)
+	mrc	p15, 0, r0, c2, c0, 2	@ TTBCR (Translation Table Base Control Register)
+	bic	r0, r0, #0x37
+	orr	r0, r0, #0x20		@ disable TTBR1
+	mcr	p15, 0, r0, c2, c0, 2
+
+	orr	r0, r3, #0x8		@ Outer Cacheability for table walks: WBWA
+	mcr	p15, 0, r0, c2, c0, 0   @ TTBR0
+
+	mov	r0, #0
+	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
+
+	mov	r0, #-1			@ manager for all domains (No permission check)
+	mcr	p15, 0, r0, c3, c0, 0   @ DACR (Domain Access Control Register)
+
+	dsb
+	isb
+	/*
+	 * MMU on:
+	 * TLBs was already invalidated in "../start.S"
+	 * So, we don't need to invalidate it here.
+	 */
+	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Contrl Register)
+	orr	r0, r0, #(CR_C | CR_M)	@ MMU and Dcache enable
+	mcr	p15, 0, r0, c1, c0, 0
+
+	mov	pc, lr
+ENDPROC(enable_mmu)
+
+#include <asm/arch/ssc-regs.h>
+
+#define BOOT_RAM_SIZE    (SSC_WAY_SIZE)
+#define BOOT_WAY_BITS    (0x00000100)   /* way 8 */
+
+ENTRY(setup_init_ram)
+	/*
+	 * Touch to zero for the boot way
+	 */
+0:
+	/*
+	 * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
+	 */
+	ldr	r0, = 0x00408006	@ touch to zero with address range
+	ldr	r1, = SSCOQM
+	str	r0, [r1]
+	ldr	r0, = (CONFIG_SYS_INIT_SP_ADDR - BOOT_RAM_SIZE)	@ base address
+	ldr	r1, = SSCOQAD
+	str	r0, [r1]
+	ldr	r0, = BOOT_RAM_SIZE
+	ldr	r1, = SSCOQSZ
+	str	r0, [r1]
+	ldr	r0, = BOOT_WAY_BITS
+	ldr	r1, = SSCOQWN
+	str	r0, [r1]
+	ldr	r1, = SSCOPPQSEF
+	ldr	r0, [r1]
+	cmp	r0, #0			@ check if the command is successfully set
+	bne	0b			@ try again if an error occurres
+
+	ldr	r1, = SSCOLPQS
+1:
+	ldr	r0, [r1]
+	cmp	r0, #0x4
+	bne	1b			@ wait until the operation is completed
+	str	r0, [r1]		@ clear the complete notification flag
+
+	mov	pc, lr
+ENDPROC(setup_init_ram)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
new file mode 100644
index 0000000000..b385e19544
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
@@ -0,0 +1,10 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+obj-y += boot-mode.o
+obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
+		sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
+obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
+	umc_init.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c
new file mode 100644
index 0000000000..85f37f299b
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/bcu-regs.h>
+
+#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
+
+void bcu_init(void)
+{
+	int shift;
+
+	writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */
+	writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
+	writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
+	writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
+	writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
+
+	/* Specify DDR channel */
+	shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
+	writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
+
+	shift -= 32;
+	writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
+
+	shift -= 32;
+	writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c
new file mode 100644
index 0000000000..27d772e8cb
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/board.h>
+
+int checkboard(void)
+{
+	puts("Board: PH1-LD4 Board\n");
+
+	return check_support_card();
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c
new file mode 100644
index 0000000000..4302277dfc
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/led.h>
+#include <asm/arch/board.h>
+
+void bcu_init(void);
+void sbc_init(void);
+void sg_init(void);
+void pll_init(void);
+void pin_init(void);
+void clkrst_init(void);
+
+int board_postclk_init(void)
+{
+	bcu_init();
+
+	sbc_init();
+
+	sg_init();
+
+	pll_init();
+
+	uniphier_board_init();
+
+	led_write(B, 1, , );
+
+	clkrst_init();
+
+	led_write(B, 2, , );
+
+	pin_init();
+
+	led_write(B, 3, , );
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c
new file mode 100644
index 0000000000..d359b56291
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c
@@ -0,0 +1 @@
+#include "../ph1-pro4/boot-mode.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c
new file mode 100644
index 0000000000..18965a94c5
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sc-regs.h>
+
+void clkrst_init(void)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(SC_RSTCTRL);
+	tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
+		| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
+	writel(tmp, SC_RSTCTRL);
+	readl(SC_RSTCTRL); /* dummy read */
+
+	/* privide clocks */
+	tmp = readl(SC_CLKCTRL);
+	tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
+	     | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
+	writel(tmp, SC_CLKCTRL);
+	readl(SC_CLKCTRL); /* dummy read */
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c
new file mode 100644
index 0000000000..a7429402f3
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sg-regs.h>
+
+void pin_init(void)
+{
+	u32 tmp;
+
+	/* Comment format:    PAD Name -> Function Name */
+
+#ifdef CONFIG_UNIPHIER_SERIAL
+	sg_set_pinsel(85, 1);	/* HSDOUT3 -> RXD0 */
+	sg_set_pinsel(88, 1);	/* HDDOUT6 -> TXD0 */
+
+	sg_set_pinsel(69, 23);	/* PCIOWR -> TXD1 */
+	sg_set_pinsel(70, 23);	/* PCIORD -> RXD1 */
+
+	sg_set_pinsel(128, 13);	/* XIRQ6 -> TXD2 */
+	sg_set_pinsel(129, 13);	/* XIRQ7 -> RXD2 */
+
+	sg_set_pinsel(110, 1);	/* SBO0 -> TXD3 */
+	sg_set_pinsel(111, 1);	/* SBI0 -> RXD3 */
+#endif
+
+#ifdef CONFIG_NAND_DENALI
+	sg_set_pinsel(158, 0);	/* XNFRE -> XNFRE_GB */
+	sg_set_pinsel(159, 0);	/* XNFWE -> XNFWE_GB */
+	sg_set_pinsel(160, 0);	/* XFALE -> NFALE_GB */
+	sg_set_pinsel(161, 0);	/* XFCLE -> NFCLE_GB */
+	sg_set_pinsel(162, 0);	/* XNFWP -> XFNWP_GB */
+	sg_set_pinsel(163, 0);	/* XNFCE0 -> XNFCE0_GB */
+	sg_set_pinsel(164, 0);	/* NANDRYBY0 -> NANDRYBY0_GB */
+	sg_set_pinsel(22, 0);	/* MMCCLK  -> XFNCE1_GB */
+	sg_set_pinsel(23, 0);	/* MMCCMD  -> NANDRYBY1_GB */
+	sg_set_pinsel(24, 0);	/* MMCDAT0 -> NFD0_GB */
+	sg_set_pinsel(25, 0);	/* MMCDAT1 -> NFD1_GB */
+	sg_set_pinsel(26, 0);	/* MMCDAT2 -> NFD2_GB */
+	sg_set_pinsel(27, 0);	/* MMCDAT3 -> NFD3_GB */
+	sg_set_pinsel(28, 0);	/* MMCDAT4 -> NFD4_GB */
+	sg_set_pinsel(29, 0);	/* MMCDAT5 -> NFD5_GB */
+	sg_set_pinsel(30, 0);	/* MMCDAT6 -> NFD6_GB */
+	sg_set_pinsel(31, 0);	/* MMCDAT7 -> NFD7_GB */
+#endif
+
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+	sg_set_pinsel(53, 0);	/* USB0VBUS -> USB0VBUS */
+	sg_set_pinsel(54, 0);	/* USB0OD   -> USB0OD */
+	sg_set_pinsel(55, 0);	/* USB1VBUS -> USB1VBUS */
+	sg_set_pinsel(56, 0);	/* USB1OD   -> USB1OD */
+	/* sg_set_pinsel(67, 23); */ /* PCOE -> USB2VBUS */
+	/* sg_set_pinsel(68, 23); */ /* PCWAIT -> USB2OD */
+#endif
+
+	tmp = readl(SG_IECTRL);
+	tmp |= 0x41;
+	writel(tmp, SG_IECTRL);
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c
new file mode 100644
index 0000000000..68b9d5ff27
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sc-regs.h>
+#include <asm/arch/sg-regs.h>
+
+#undef DPLL_SSC_RATE_1PER
+
+void dpll_init(void)
+{
+	u32 tmp;
+
+	/*
+	 * Set Frequency
+	 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
+	 * to FOUT (DPLLCTRL.bit[29:20])
+	 */
+	tmp = readl(SC_DPLLCTRL);
+	tmp &= ~0x000f0000;
+#if CONFIG_DDR_FREQ == 1600
+	tmp |= 0x000c0000;
+#elif CONFIG_DDR_FREQ == 1333
+	tmp |= 0x000d0000;
+#else
+# error "Unknown frequency"
+#endif
+
+#if defined(DPLL_SSC_RATE_1PER)
+	tmp &= ~SC_DPLLCTRL_SSC_RATE;
+#else
+	tmp |= SC_DPLLCTRL_SSC_RATE;
+#endif
+	writel(tmp, SC_DPLLCTRL);
+
+	tmp = readl(SC_DPLLCTRL2);
+	tmp |= SC_DPLLCTRL2_NRSTDS;
+	writel(tmp, SC_DPLLCTRL2);
+}
+
+void upll_init(void)
+{
+	u32 tmp, clk_mode_upll, clk_mode_axosel;
+
+	tmp = readl(SG_PINMON0);
+	clk_mode_upll   = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
+	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+	/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
+	tmp = readl(SC_UPLLCTRL);
+	tmp &= ~0x18000000;
+	writel(tmp, SC_UPLLCTRL);
+
+	if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
+		if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+		    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+			/* AXO: 25MHz */
+			tmp &= ~0x07ffffff;
+			tmp |= 0x0228f5c0;
+		} else {
+			/* AXO: default 24.576MHz */
+			tmp &= ~0x07ffffff;
+			tmp |= 0x02328000;
+		}
+	}
+
+	writel(tmp, SC_UPLLCTRL);
+
+	/* set 1 to K_LD(UPLLCTRL.bit[27]) */
+	tmp |= 0x08000000;
+	writel(tmp, SC_UPLLCTRL);
+
+	/* wait 10 usec */
+	udelay(10);
+
+	/* set 1 to SNRT(UPLLCTRL.bit[28]) */
+	tmp |= 0x10000000;
+	writel(tmp, SC_UPLLCTRL);
+}
+
+void vpll_init(void)
+{
+	u32 tmp, clk_mode_axosel;
+
+	tmp = readl(SG_PINMON0);
+	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+	/* set 1 to VPLA27WP and VPLA27WP */
+	tmp = readl(SC_VPLL27ACTRL);
+	tmp |= 0x00000001;
+	writel(tmp, SC_VPLL27ACTRL);
+	tmp = readl(SC_VPLL27BCTRL);
+	tmp |= 0x00000001;
+	writel(tmp, SC_VPLL27BCTRL);
+
+	/* Set 0 to VPLA_K_LD and VPLB_K_LD */
+	tmp = readl(SC_VPLL27ACTRL3);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27ACTRL3);
+	tmp = readl(SC_VPLL27BCTRL3);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27BCTRL3);
+
+	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp &= ~0x0000007f;
+	tmp |= 0x00000020;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp &= ~0x0000007f;
+	tmp |= 0x00000020;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+		/* AXO: 25MHz */
+		tmp = readl(SC_VPLL27ACTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x00066664;
+		writel(tmp, SC_VPLL27ACTRL3);
+		tmp = readl(SC_VPLL27BCTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x00066664;
+		writel(tmp, SC_VPLL27BCTRL3);
+	} else {
+		/* AXO: default 24.576MHz */
+		tmp = readl(SC_VPLL27ACTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x000f5800;
+		writel(tmp, SC_VPLL27ACTRL3);
+		tmp = readl(SC_VPLL27BCTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x000f5800;
+		writel(tmp, SC_VPLL27BCTRL3);
+	}
+
+	/* Set 1 to VPLA_K_LD and VPLB_K_LD */
+	tmp = readl(SC_VPLL27ACTRL3);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27ACTRL3);
+	tmp = readl(SC_VPLL27BCTRL3);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27BCTRL3);
+
+	/* wait 10 usec */
+	udelay(10);
+
+	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	/* set 0 to VPLA27WP and VPLA27WP */
+	tmp = readl(SC_VPLL27ACTRL);
+	tmp &= ~0x00000001;
+	writel(tmp, SC_VPLL27ACTRL);
+	tmp = readl(SC_VPLL27BCTRL);
+	tmp |= ~0x00000001;
+	writel(tmp, SC_VPLL27BCTRL);
+}
+
+void pll_init(void)
+{
+	dpll_init();
+	upll_init();
+	vpll_init();
+
+	/*
+	 * Wait 500 usec until dpll get stable
+	 * We wait 10 usec in upll_init() and vpll_init()
+	 * so 20 usec can be saved here.
+	 */
+	udelay(480);
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c
new file mode 100644
index 0000000000..837b2a891b
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c
@@ -0,0 +1 @@
+#include "../ph1-pro4/pll_spectrum.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
new file mode 100644
index 0000000000..a37ed1674f
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sbc-regs.h>
+#include <asm/arch/sg-regs.h>
+
+void sbc_init(void)
+{
+	/* XECS1: sub/boot memory (boot swap = off/on) */
+	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
+	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
+	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
+	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
+
+#if !defined(CONFIG_SPL_BUILD)
+	/* XECS0: boot/sub memory (boot swap = off/on) */
+	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
+	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
+	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
+	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
+#endif
+	/* XECS3: peripherals */
+	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
+	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
+	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
+	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
+
+	/* base address regsiters */
+	writel(0x0000bc01, SBBASE0);
+	writel(0x0400bc01, SBBASE1);
+	writel(0x0800bf01, SBBASE3);
+
+#if !defined(CONFIG_SPL_BUILD)
+	/* enable access to sub memory when boot swap is on */
+	sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
+#endif
+	sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c
new file mode 100644
index 0000000000..b4dd799a88
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sg-regs.h>
+
+void sg_init(void)
+{
+	u32 tmp;
+
+	/* Set DDR size */
+	tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
+	tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
+#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
+	tmp |= SG_MEMCONF_SPARSEMEM;
+#endif
+	writel(tmp, SG_MEMCONF);
+
+	/* Input ports must be enabled deasserting reset of cores */
+	tmp = readl(SG_IECTRL);
+	tmp |= 0x1;
+	writel(tmp, SG_IECTRL);
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c
new file mode 100644
index 0000000000..1344ac1caa
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/umc-regs.h>
+
+static inline void umc_start_ssif(void __iomem *ssif_base)
+{
+	writel(0x00000000, ssif_base + 0x0000b004);
+	writel(0xffffffff, ssif_base + 0x0000c004);
+	writel(0x000fffcf, ssif_base + 0x0000c008);
+	writel(0x00000001, ssif_base + 0x0000b000);
+	writel(0x00000001, ssif_base + 0x0000c000);
+	writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+	writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+
+	writel(0x00000001, ssif_base + UMC_CPURST);
+	writel(0x00000001, ssif_base + UMC_IDSRST);
+	writel(0x00000001, ssif_base + UMC_IXMRST);
+	writel(0x00000001, ssif_base + UMC_MDMRST);
+	writel(0x00000001, ssif_base + UMC_MDDRST);
+	writel(0x00000001, ssif_base + UMC_SIORST);
+	writel(0x00000001, ssif_base + UMC_VIORST);
+	writel(0x00000001, ssif_base + UMC_FRCRST);
+	writel(0x00000001, ssif_base + UMC_RGLRST);
+	writel(0x00000001, ssif_base + UMC_AIORST);
+	writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+		       int size, int freq)
+{
+	if (freq == 1333) {
+		writel(0x45990b11, dramcont + UMC_CMDCTLA);
+		writel(0x16958924, dramcont + UMC_CMDCTLB);
+		writel(0x5101046A, dramcont + UMC_INITCTLA);
+
+		if (size == 1)
+			writel(0x27028B0A, dramcont + UMC_INITCTLB);
+		else if (size == 2)
+			writel(0x38028B0A, dramcont + UMC_INITCTLB);
+
+		writel(0x000FF0FF, dramcont + UMC_INITCTLC);
+		writel(0x00000b51, dramcont + UMC_DRMMR0);
+	} else if (freq == 1600) {
+		writel(0x36BB0F17, dramcont + UMC_CMDCTLA);
+		writel(0x18C6AA24, dramcont + UMC_CMDCTLB);
+		writel(0x5101387F, dramcont + UMC_INITCTLA);
+
+		if (size == 1)
+			writel(0x2F030D3F, dramcont + UMC_INITCTLB);
+		else if (size == 2)
+			writel(0x43030D3F, dramcont + UMC_INITCTLB);
+
+		writel(0x00FF00FF, dramcont + UMC_INITCTLC);
+		writel(0x00000d71, dramcont + UMC_DRMMR0);
+	}
+
+	writel(0x00000006, dramcont + UMC_DRMMR1);
+
+	if (freq == 1333)
+		writel(0x00000290, dramcont + UMC_DRMMR2);
+	else if (freq == 1600)
+		writel(0x00000298, dramcont + UMC_DRMMR2);
+
+	writel(0x00000800, dramcont + UMC_DRMMR3);
+
+	if (freq == 1333) {
+		if (size == 1)
+			writel(0x00240512, dramcont + UMC_SPCCTLA);
+		else if (size == 2)
+			writel(0x00350512, dramcont + UMC_SPCCTLA);
+
+		writel(0x00ff0006, dramcont + UMC_SPCCTLB);
+		writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
+	} else if (freq == 1600) {
+		if (size == 1)
+			writel(0x002B0617, dramcont + UMC_SPCCTLA);
+		else if (size == 2)
+			writel(0x003F0617, dramcont + UMC_SPCCTLA);
+
+		writel(0x00ff0008, dramcont + UMC_SPCCTLB);
+		writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
+	}
+
+	writel(0x04060806, dramcont + UMC_WDATACTL_D0);
+	writel(0x04a02000, dramcont + UMC_DATASET);
+	writel(0x00000000, ca_base + 0x2300);
+	writel(0x00400020, dramcont + UMC_DCCGCTL);
+	writel(0x00000003, dramcont + 0x7000);
+	writel(0x0000000f, dramcont + 0x8000);
+	writel(0x000000c3, dramcont + 0x8004);
+	writel(0x00000071, dramcont + 0x8008);
+	writel(0x0000003b, dramcont + UMC_DICGCTLA);
+	writel(0x020a0808, dramcont + UMC_DICGCTLB);
+	writel(0x00000004, dramcont + UMC_FLOWCTLG);
+	writel(0x80000201, ca_base + 0xc20);
+	writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
+	writel(0x00200000, dramcont + UMC_FLOWCTLB);
+	writel(0x00004444, dramcont + UMC_FLOWCTLC);
+	writel(0x200a0a00, dramcont + UMC_SPCSETB);
+	writel(0x00000000, dramcont + UMC_SPCSETD);
+	writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
+}
+
+static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
+{
+	void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
+	void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
+	void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
+	void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
+	void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+
+	umc_dram_init_start(dramcont0);
+	umc_dram_init_start(dramcont1);
+	umc_dram_init_poll(dramcont0);
+	umc_dram_init_poll(dramcont1);
+
+	writel(0x00000101, dramcont0 + UMC_DIOCTLA);
+
+	writel(0x00000101, dramcont1 + UMC_DIOCTLA);
+
+	umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
+	umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
+
+	umc_start_ssif(ssif_base);
+
+	return 0;
+}
+
+int umc_init(void)
+{
+	return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
+					CONFIG_SDRAM1_SIZE / 0x08000000);
+}
+
+#if CONFIG_DDR_FREQ != 1333 && CONFIG_DDR_FREQ != 1600
+#error Unsupported DDR Frequency.
+#endif
+
+#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
+    (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
+    CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
+/* OK */
+#else
+#error Unsupported DDR configuration.
+#endif
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
new file mode 100644
index 0000000000..712afd1bee
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
@@ -0,0 +1,10 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+obj-y += boot-mode.o
+obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \
+				sg_init.o pll_init.o clkrst_init.o pinctrl.o
+obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
+	umc_init.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c
new file mode 100644
index 0000000000..325a4f6160
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/board.h>
+
+int checkboard(void)
+{
+	puts("Board: PH1-Pro4 Board\n");
+
+	return check_support_card();
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c
new file mode 100644
index 0000000000..7198829988
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/led.h>
+#include <asm/arch/board.h>
+
+void sbc_init(void);
+void sg_init(void);
+void pll_init(void);
+void pin_init(void);
+void clkrst_init(void);
+
+int board_postclk_init(void)
+{
+	sbc_init();
+
+	sg_init();
+
+	pll_init();
+
+	uniphier_board_init();
+
+	led_write(B, 1, , );
+
+	clkrst_init();
+
+	led_write(B, 2, , );
+
+	pin_init();
+
+	led_write(B, 3, , );
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c
new file mode 100644
index 0000000000..33bccff2a5
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/boot-device.h>
+#include <asm/arch/sg-regs.h>
+#include <asm/arch/sbc-regs.h>
+
+struct boot_device_info boot_device_table[] = {
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize   1MB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize   1MB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"},
+	{BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+	{BOOT_DEVICE_NONE, "Reserved"},
+	{BOOT_DEVICE_NONE, "Reserved"},
+	{BOOT_DEVICE_NONE, "Reserved"},
+	{BOOT_DEVICE_NONE, "Reserved"},
+	{BOOT_DEVICE_NONE, "Reserved"},
+	{BOOT_DEVICE_NONE, "Reserved"},
+	{BOOT_DEVICE_NONE, ""}
+};
+
+u32 get_boot_mode_sel(void)
+{
+	return (readl(SG_PINMON0) >> 1) & 0x1f;
+}
+
+u32 spl_boot_device(void)
+{
+	u32 boot_mode;
+
+	if (boot_is_swapped())
+		return BOOT_DEVICE_NOR;
+
+	boot_mode = get_boot_mode_sel();
+
+	return boot_device_table[boot_mode].type;
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c
new file mode 100644
index 0000000000..18965a94c5
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sc-regs.h>
+
+void clkrst_init(void)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(SC_RSTCTRL);
+	tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
+		| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
+	writel(tmp, SC_RSTCTRL);
+	readl(SC_RSTCTRL); /* dummy read */
+
+	/* privide clocks */
+	tmp = readl(SC_CLKCTRL);
+	tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
+	     | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
+	writel(tmp, SC_CLKCTRL);
+	readl(SC_CLKCTRL); /* dummy read */
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c
new file mode 100644
index 0000000000..503c247d6b
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sg-regs.h>
+
+void pin_init(void)
+{
+	/* Comment format:    PAD Name -> Function Name */
+
+#ifdef CONFIG_UNIPHIER_SERIAL
+	sg_set_pinsel(127, 0);	/* RXD0 -> RXD0 */
+	sg_set_pinsel(128, 0);	/* TXD0 -> TXD0 */
+	sg_set_pinsel(129, 0);	/* RXD1 -> RXD1 */
+	sg_set_pinsel(130, 0);	/* TXD1 -> TXD1 */
+	sg_set_pinsel(131, 0);	/* RXD2 -> RXD2 */
+	sg_set_pinsel(132, 0);	/* TXD2 -> TXD2 */
+	sg_set_pinsel(88, 2);	/* CH6CLK -> RXD3 */
+	sg_set_pinsel(89, 2);	/* CH6VAL -> TXD3 */
+#endif
+
+#ifdef CONFIG_NAND_DENALI
+	sg_set_pinsel(40, 0);	/* NFD0   -> NFD0 */
+	sg_set_pinsel(41, 0);	/* NFD1   -> NFD1 */
+	sg_set_pinsel(42, 0);	/* NFD2   -> NFD2 */
+	sg_set_pinsel(43, 0);	/* NFD3   -> NFD3 */
+	sg_set_pinsel(44, 0);	/* NFD4   -> NFD4 */
+	sg_set_pinsel(45, 0);	/* NFD5   -> NFD5 */
+	sg_set_pinsel(46, 0);	/* NFD6   -> NFD6 */
+	sg_set_pinsel(47, 0);	/* NFD7   -> NFD7 */
+	sg_set_pinsel(48, 0);	/* NFALE  -> NFALE */
+	sg_set_pinsel(49, 0);	/* NFCLE  -> NFCLE */
+	sg_set_pinsel(50, 0);	/* XNFRE  -> XNFRE */
+	sg_set_pinsel(51, 0);	/* XNFWE  -> XNFWE */
+	sg_set_pinsel(52, 0);	/* XNFWP  -> XNFWP */
+	sg_set_pinsel(53, 0);	/* XNFCE0 -> XNFCE0 */
+	sg_set_pinsel(54, 0);	/* NRYBY0 -> NRYBY0 */
+#endif
+
+	writel(1, SG_LOADPINCTRL);
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c
new file mode 100644
index 0000000000..2dcc0892cc
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sc-regs.h>
+#include <asm/arch/sg-regs.h>
+
+#undef DPLL_SSC_RATE_1PER
+
+void dpll_init(void)
+{
+	u32 tmp;
+
+	/*
+	 * Set Frequency
+	 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
+	 * to FOUT ( DPLLCTRL.bit[29:20] )
+	 */
+	tmp = readl(SC_DPLLCTRL);
+	tmp &= ~(0x000f0000);
+#if CONFIG_DDR_FREQ == 1600
+	tmp |= 0x000c0000;
+#elif CONFIG_DDR_FREQ == 1333
+	tmp |= 0x000d0000;
+#else
+# error "Unsupported frequency"
+#endif
+
+	/*
+	 * Set Moduration rate
+	 * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
+	 */
+#if defined(DPLL_SSC_RATE_1PER)
+	tmp &= ~0x00008000;
+#else
+	tmp |= 0x00008000;
+#endif
+	writel(tmp, SC_DPLLCTRL);
+
+	tmp = readl(SC_DPLLCTRL2);
+	tmp |= SC_DPLLCTRL2_NRSTDS;
+	writel(tmp, SC_DPLLCTRL2);
+}
+
+void stop_mpll(void)
+{
+	u32 tmp;
+
+	tmp = readl(SC_MPLLOSCCTL);
+
+	if (!(tmp & SC_MPLLOSCCTL_MPLLST))
+		return; /* already stopped */
+
+	tmp &= ~SC_MPLLOSCCTL_MPLLEN;
+	writel(tmp, SC_MPLLOSCCTL);
+
+	while (readl(SC_MPLLOSCCTL) & SC_MPLLOSCCTL_MPLLST)
+		;
+}
+
+void vpll_init(void)
+{
+	u32 tmp, clk_mode_axosel;
+
+	/* Set VPLL27A &  VPLL27B */
+	tmp = readl(SG_PINMON0);
+	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+#if defined(CONFIG_MACH_PH1_PRO4)
+	/* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
+	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
+	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
+		return;
+#endif
+
+	/* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
+	tmp = readl(SC_VPLL27ACTRL);
+	tmp |= 0x00000001;
+	writel(tmp, SC_VPLL27ACTRL);
+	tmp = readl(SC_VPLL27BCTRL);
+	tmp |= 0x00000001;
+	writel(tmp, SC_VPLL27BCTRL);
+
+	/* Unset VPLA_K_LD and VPLB_K_LD bit */
+	tmp = readl(SC_VPLL27ACTRL3);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27ACTRL3);
+	tmp = readl(SC_VPLL27BCTRL3);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27BCTRL3);
+
+	/* Set VPLA_M and VPLB_M to 0x20 */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp &= ~0x0000007f;
+	tmp |= 0x00000020;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp &= ~0x0000007f;
+	tmp |= 0x00000020;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
+	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
+		/* Set VPLA_K and VPLB_K for AXO: 25MHz */
+		tmp = readl(SC_VPLL27ACTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x00066666;
+		writel(tmp, SC_VPLL27ACTRL3);
+		tmp = readl(SC_VPLL27BCTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x00066666;
+		writel(tmp, SC_VPLL27BCTRL3);
+	} else {
+		/* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
+		tmp = readl(SC_VPLL27ACTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x000f5800;
+		writel(tmp, SC_VPLL27ACTRL3);
+		tmp = readl(SC_VPLL27BCTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x000f5800;
+		writel(tmp, SC_VPLL27BCTRL3);
+	}
+
+	/* wait 1 usec */
+	udelay(1);
+
+	/* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
+	tmp = readl(SC_VPLL27ACTRL3);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27ACTRL3);
+	tmp = readl(SC_VPLL27BCTRL3);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27BCTRL3);
+
+	/* Unset VPLA_SNRST and VPLB_SNRST bit */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	/* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
+	tmp = readl(SC_VPLL27ACTRL);
+	tmp &= ~0x00000001;
+	writel(tmp, SC_VPLL27ACTRL);
+	tmp = readl(SC_VPLL27BCTRL);
+	tmp &= ~0x00000001;
+	writel(tmp, SC_VPLL27BCTRL);
+}
+
+void pll_init(void)
+{
+	dpll_init();
+	stop_mpll();
+	vpll_init();
+
+	/*
+	 * Wait 500 usec until dpll get stable
+	 * We wait 1 usec in vpll_init() so 1 usec can be saved here.
+	 */
+	udelay(499);
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c
new file mode 100644
index 0000000000..4538d1af44
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sc-regs.h>
+
+void enable_dpll_ssc(void)
+{
+	u32 tmp;
+
+	tmp = readl(SC_DPLLCTRL);
+	tmp |= SC_DPLLCTRL_SSC_EN;
+	writel(tmp, SC_DPLLCTRL);
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
new file mode 100644
index 0000000000..f113db54d1
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sbc-regs.h>
+#include <asm/arch/sg-regs.h>
+
+void sbc_init(void)
+{
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
+	/*
+	 * Only CS1 is connected to support card.
+	 * BKSZ[1:0] should be set to "01".
+	 */
+	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
+	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
+	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
+	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
+
+	if (readl(SBBASE0) & 0x1) {
+		/*
+		 * Boot Swap Off: boot from mask ROM
+		 * 0x00000000-0x01ffffff: mask ROM
+		 * 0x02000000-0x3effffff: memory bank (31MB)
+		 * 0x03f00000-0x3fffffff: peripherals (1MB)
+		 */
+		writel(0x0000be01, SBBASE0); /* dummy */
+		writel(0x0200be01, SBBASE1);
+	} else {
+		/*
+		 * Boot Swap On: boot from external NOR/SRAM
+		 * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
+		 *
+		 * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
+		 * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
+		 */
+		writel(0x0000bc01, SBBASE0);
+	}
+#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+#if !defined(CONFIG_SPL_BUILD)
+	/* XECS0: boot/sub memory (boot swap = off/on) */
+	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
+	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
+	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
+	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
+#endif
+	/* XECS1: sub/boot memory (boot swap = off/on) */
+	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
+	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
+	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
+	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
+
+	/* XECS3: peripherals */
+	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
+	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
+	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
+	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
+
+	writel(0x0000bc01, SBBASE0); /* boot memory */
+	writel(0x0400bc01, SBBASE1); /* sub memory */
+	writel(0x0800bf01, SBBASE3); /* peripherals */
+
+#if !defined(CONFIG_SPL_BUILD)
+	sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
+#endif
+	sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
+	writel(0x00000001, SG_LOADPINCTRL);
+
+#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
new file mode 100644
index 0000000000..b4dd799a88
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sg-regs.h>
+
+void sg_init(void)
+{
+	u32 tmp;
+
+	/* Set DDR size */
+	tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
+	tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
+#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
+	tmp |= SG_MEMCONF_SPARSEMEM;
+#endif
+	writel(tmp, SG_MEMCONF);
+
+	/* Input ports must be enabled deasserting reset of cores */
+	tmp = readl(SG_IECTRL);
+	tmp |= 0x1;
+	writel(tmp, SG_IECTRL);
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c
new file mode 100644
index 0000000000..dd462875bb
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/umc-regs.h>
+
+static inline void umc_start_ssif(void __iomem *ssif_base)
+{
+	writel(0x00000001, ssif_base + 0x0000b004);
+	writel(0xffffffff, ssif_base + 0x0000c004);
+	writel(0x07ffffff, ssif_base + 0x0000c008);
+	writel(0x00000001, ssif_base + 0x0000b000);
+	writel(0x00000001, ssif_base + 0x0000c000);
+
+	writel(0x03010100, ssif_base + UMC_HDMCHSEL);
+	writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+	writel(0x03010100, ssif_base + UMC_DVCCHSEL);
+	writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+	writel(0x00000000, ssif_base + 0x0000c044);		/* DCGIV_SSIF_REG */
+
+	writel(0x00000001, ssif_base + UMC_CPURST);
+	writel(0x00000001, ssif_base + UMC_IDSRST);
+	writel(0x00000001, ssif_base + UMC_IXMRST);
+	writel(0x00000001, ssif_base + UMC_HDMRST);
+	writel(0x00000001, ssif_base + UMC_MDMRST);
+	writel(0x00000001, ssif_base + UMC_HDDRST);
+	writel(0x00000001, ssif_base + UMC_MDDRST);
+	writel(0x00000001, ssif_base + UMC_SIORST);
+	writel(0x00000001, ssif_base + UMC_GIORST);
+	writel(0x00000001, ssif_base + UMC_HD2RST);
+	writel(0x00000001, ssif_base + UMC_VIORST);
+	writel(0x00000001, ssif_base + UMC_DVCRST);
+	writel(0x00000001, ssif_base + UMC_RGLRST);
+	writel(0x00000001, ssif_base + UMC_VPERST);
+	writel(0x00000001, ssif_base + UMC_AIORST);
+	writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+		       int size, int freq)
+{
+	writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
+	writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
+	writel(0x5101387f, dramcont + UMC_INITCTLA);
+	writel(0x43030d3f, dramcont + UMC_INITCTLB);
+	writel(0x00ff00ff, dramcont + UMC_INITCTLC);
+	writel(0x00000d71, dramcont + UMC_DRMMR0);
+	writel(0x00000006, dramcont + UMC_DRMMR1);
+	writel(0x00000298, dramcont + UMC_DRMMR2);
+	writel(0x00000000, dramcont + UMC_DRMMR3);
+	writel(0x003f0617, dramcont + UMC_SPCCTLA);
+	writel(0x00ff0008, dramcont + UMC_SPCCTLB);
+	writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
+	writel(0x000c00ae, dramcont + UMC_RDATACTL_D1);
+	writel(0x04060802, dramcont + UMC_WDATACTL_D0);
+	writel(0x04060802, dramcont + UMC_WDATACTL_D1);
+	writel(0x04a02000, dramcont + UMC_DATASET);
+	writel(0x00000000, ca_base + 0x2300);
+	writel(0x00400020, dramcont + UMC_DCCGCTL);
+	writel(0x0000000f, dramcont + 0x7000);
+	writel(0x0000000f, dramcont + 0x8000);
+	writel(0x000000c3, dramcont + 0x8004);
+	writel(0x00000071, dramcont + 0x8008);
+	writel(0x00000004, dramcont + UMC_FLOWCTLG);
+	writel(0x00000000, dramcont + 0x0060);
+	writel(0x80000201, ca_base + 0xc20);
+	writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
+	writel(0x00200000, dramcont + UMC_FLOWCTLB);
+	writel(0x00004444, dramcont + UMC_FLOWCTLC);
+	writel(0x200a0a00, dramcont + UMC_SPCSETB);
+	writel(0x00010000, dramcont + UMC_SPCSETD);
+	writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
+}
+
+static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
+{
+	void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
+	void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
+	void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
+	void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
+	void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+
+	umc_dram_init_start(dramcont0);
+	umc_dram_init_start(dramcont1);
+	umc_dram_init_poll(dramcont0);
+	umc_dram_init_poll(dramcont1);
+
+	writel(0x00000101, dramcont0 + UMC_DIOCTLA);
+
+	writel(0x00000103, dramcont0 + UMC_DIOCTLA);
+
+	writel(0x00000101, dramcont1 + UMC_DIOCTLA);
+
+	writel(0x00000103, dramcont1 + UMC_DIOCTLA);
+
+	umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
+	umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
+
+	umc_start_ssif(ssif_base);
+
+	return 0;
+}
+
+int umc_init(void)
+{
+	return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
+					CONFIG_SDRAM1_SIZE / 0x08000000);
+}
+
+#if CONFIG_DDR_FREQ != 1600
+#error Unsupported DDR frequency.
+#endif
+
+#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \
+     (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \
+    ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \
+     (CONFIG_SDRAM1_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH1 == 1))
+/* OK */
+#else
+ #error Unsupported DDR configuration.
+#endif
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
new file mode 100644
index 0000000000..b385e19544
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
@@ -0,0 +1,10 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+obj-y += boot-mode.o
+obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
+		sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
+obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
+	umc_init.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c
new file mode 100644
index 0000000000..69b172e4e7
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c
@@ -0,0 +1 @@
+#include "../ph1-ld4/bcu_init.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c
new file mode 100644
index 0000000000..15dc289c01
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/board.h>
+
+int checkboard(void)
+{
+	puts("Board: PH1-sLD8 Board\n");
+
+	return check_support_card();
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c
new file mode 100644
index 0000000000..287b33c21d
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c
@@ -0,0 +1 @@
+#include "../ph1-ld4/board_postclk_init.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c
new file mode 100644
index 0000000000..d359b56291
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c
@@ -0,0 +1 @@
+#include "../ph1-pro4/boot-mode.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c
new file mode 100644
index 0000000000..18965a94c5
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sc-regs.h>
+
+void clkrst_init(void)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(SC_RSTCTRL);
+	tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
+		| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
+	writel(tmp, SC_RSTCTRL);
+	readl(SC_RSTCTRL); /* dummy read */
+
+	/* privide clocks */
+	tmp = readl(SC_CLKCTRL);
+	tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
+	     | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
+	writel(tmp, SC_CLKCTRL);
+	readl(SC_CLKCTRL); /* dummy read */
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c
new file mode 100644
index 0000000000..2b6403f88f
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sg-regs.h>
+
+void pin_init(void)
+{
+	/* Comment format:    PAD Name -> Function Name */
+
+#ifdef CONFIG_UNIPHIER_SERIAL
+	sg_set_pinsel(70, 3);	/* HDDOUT0 -> TXD0 */
+	sg_set_pinsel(71, 3);	/* HSDOUT1 -> RXD0 */
+
+	sg_set_pinsel(114, 0);	/* TXD1 -> TXD1 */
+	sg_set_pinsel(115, 0);	/* RXD1 -> RXD1 */
+
+	sg_set_pinsel(112, 1);	/* SBO1 -> TXD2 */
+	sg_set_pinsel(113, 1);	/* SBI1 -> RXD2 */
+
+	sg_set_pinsel(110, 1);	/* SBO0 -> TXD3 */
+	sg_set_pinsel(111, 1);	/* SBI0 -> RXD3 */
+#endif
+
+#ifdef CONFIG_NAND_DENALI
+	sg_set_pinsel(15, 0);	/* XNFRE_GB -> XNFRE_GB */
+	sg_set_pinsel(16, 0);	/* XNFWE_GB -> XNFWE_GB */
+	sg_set_pinsel(17, 0);	/* XFALE_GB -> NFALE_GB */
+	sg_set_pinsel(18, 0);	/* XFCLE_GB -> NFCLE_GB */
+	sg_set_pinsel(19, 0);	/* XNFWP_GB -> XFNWP_GB */
+	sg_set_pinsel(20, 0);	/* XNFCE0_GB -> XNFCE0_GB */
+	sg_set_pinsel(21, 0);	/* NANDRYBY0_GB -> NANDRYBY0_GB */
+	sg_set_pinsel(22, 0);	/* XFNCE1_GB  -> XFNCE1_GB */
+	sg_set_pinsel(23, 0);	/* NANDRYBY1_GB  -> NANDRYBY1_GB */
+	sg_set_pinsel(24, 0);	/* NFD0_GB -> NFD0_GB */
+	sg_set_pinsel(25, 0);	/* NFD1_GB -> NFD1_GB */
+	sg_set_pinsel(26, 0);	/* NFD2_GB -> NFD2_GB */
+	sg_set_pinsel(27, 0);	/* NFD3_GB -> NFD3_GB */
+	sg_set_pinsel(28, 0);	/* NFD4_GB -> NFD4_GB */
+	sg_set_pinsel(29, 0);	/* NFD5_GB -> NFD5_GB */
+	sg_set_pinsel(30, 0);	/* NFD6_GB -> NFD6_GB */
+	sg_set_pinsel(31, 0);	/* NFD7_GB -> NFD7_GB */
+#endif
+
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+	sg_set_pinsel(41, 0);	/* USB0VBUS -> USB0VBUS */
+	sg_set_pinsel(42, 0);	/* USB0OD   -> USB0OD */
+	sg_set_pinsel(43, 0);	/* USB1VBUS -> USB1VBUS */
+	sg_set_pinsel(44, 0);	/* USB1OD   -> USB1OD */
+	/* sg_set_pinsel(114, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */
+	/* sg_set_pinsel(115, 4); */ /* RXD1 -> USB2OD */
+#endif
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c
new file mode 100644
index 0000000000..4d87053430
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sc-regs.h>
+#include <asm/arch/sg-regs.h>
+
+void dpll_init(void)
+{
+	u32 tmp;
+	/*
+	 * Set DPLL SSC parameters for DPLLCTRL3
+	 * [23]    DIVN_TEST    0x1
+	 * [22:16] DIVN         0x50
+	 * [10]    FREFSEL_TEST 0x1
+	 * [9:8]   FREFSEL      0x2
+	 * [4]     ICPD_TEST    0x1
+	 * [3:0]   ICPD         0xb
+	 */
+	tmp = readl(SC_DPLLCTRL3);
+	tmp &= ~0x00ff0717;
+	tmp |= 0x00d0061b;
+	writel(tmp, SC_DPLLCTRL3);
+
+	/*
+	 * Set DPLL SSC parameters for DPLLCTRL
+	 *                    <-1%>          <-2%>
+	 * [29:20] SSC_UPCNT 132 (0x084)    132  (0x084)
+	 * [14:0]  SSC_dK    6335(0x18bf)   12710(0x31a6)
+	 */
+	tmp = readl(SC_DPLLCTRL);
+	tmp &= ~0x3ff07fff;
+#ifdef CONFIG_DPLL_SSC_RATE_1PER
+	tmp |= 0x084018bf;
+#else
+	tmp |= 0x084031a6;
+#endif
+	writel(tmp, SC_DPLLCTRL);
+
+	/*
+	 * Set DPLL SSC parameters for DPLLCTRL2
+	 * [31:29]  SSC_STEP     0
+	 * [27]     SSC_REG_REF  1
+	 * [26:20]  SSC_M        79     (0x4f)
+	 * [19:0]   SSC_K        964689 (0xeb851)
+	 */
+	tmp = readl(SC_DPLLCTRL2);
+	tmp &= ~0xefffffff;
+	tmp |= 0x0cfeb851;
+	writel(tmp, SC_DPLLCTRL2);
+}
+
+void upll_init(void)
+{
+	u32 tmp, clk_mode_upll, clk_mode_axosel;
+
+	tmp = readl(SG_PINMON0);
+	clk_mode_upll   = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
+	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+	/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
+	tmp = readl(SC_UPLLCTRL);
+	tmp &= ~0x18000000;
+	writel(tmp, SC_UPLLCTRL);
+
+	if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
+		if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+		    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+			/* AXO: 25MHz */
+			tmp &= ~0x07ffffff;
+			tmp |= 0x0228f5c0;
+		} else {
+			/* AXO: default 24.576MHz */
+			tmp &= ~0x07ffffff;
+			tmp |= 0x02328000;
+		}
+	}
+
+	writel(tmp, SC_UPLLCTRL);
+
+	/* set 1 to K_LD(UPLLCTRL.bit[27]) */
+	tmp |= 0x08000000;
+	writel(tmp, SC_UPLLCTRL);
+
+	/* wait 10 usec */
+	udelay(10);
+
+	/* set 1 to SNRT(UPLLCTRL.bit[28]) */
+	tmp |= 0x10000000;
+	writel(tmp, SC_UPLLCTRL);
+}
+
+void vpll_init(void)
+{
+	u32 tmp, clk_mode_axosel;
+
+	tmp = readl(SG_PINMON0);
+	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+	/* set 1 to VPLA27WP and VPLA27WP */
+	tmp = readl(SC_VPLL27ACTRL);
+	tmp |= 0x00000001;
+	writel(tmp, SC_VPLL27ACTRL);
+	tmp = readl(SC_VPLL27BCTRL);
+	tmp |= 0x00000001;
+	writel(tmp, SC_VPLL27BCTRL);
+
+	/* Set 0 to VPLA_K_LD and VPLB_K_LD */
+	tmp = readl(SC_VPLL27ACTRL3);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27ACTRL3);
+	tmp = readl(SC_VPLL27BCTRL3);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27BCTRL3);
+
+	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp &= ~0x0000007f;
+	tmp |= 0x00000020;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp &= ~0x0000007f;
+	tmp |= 0x00000020;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+		/* AXO: 25MHz */
+		tmp = readl(SC_VPLL27ACTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x00066664;
+		writel(tmp, SC_VPLL27ACTRL3);
+		tmp = readl(SC_VPLL27BCTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x00066664;
+		writel(tmp, SC_VPLL27BCTRL3);
+	} else {
+		/* AXO: default 24.576MHz */
+		tmp = readl(SC_VPLL27ACTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x000f5800;
+		writel(tmp, SC_VPLL27ACTRL3);
+		tmp = readl(SC_VPLL27BCTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x000f5800;
+		writel(tmp, SC_VPLL27BCTRL3);
+	}
+
+	/* Set 1 to VPLA_K_LD and VPLB_K_LD */
+	tmp = readl(SC_VPLL27ACTRL3);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27ACTRL3);
+	tmp = readl(SC_VPLL27BCTRL3);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27BCTRL3);
+
+	/* wait 10 usec */
+	udelay(10);
+
+	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	/* set 0 to VPLA27WP and VPLA27WP */
+	tmp = readl(SC_VPLL27ACTRL);
+	tmp &= ~0x00000001;
+	writel(tmp, SC_VPLL27ACTRL);
+	tmp = readl(SC_VPLL27BCTRL);
+	tmp |= ~0x00000001;
+	writel(tmp, SC_VPLL27BCTRL);
+}
+
+void pll_init(void)
+{
+	dpll_init();
+	upll_init();
+	vpll_init();
+
+	/*
+	 * Wait 500 usec until dpll get stable
+	 * We wait 10 usec in upll_init() and vpll_init()
+	 * so 20 usec can be saved here.
+	 */
+	udelay(480);
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c
new file mode 100644
index 0000000000..9b8c4855e5
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c
@@ -0,0 +1 @@
+#include "../ph1-ld4/pll_spectrum.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
new file mode 100644
index 0000000000..af44dee4f6
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sbc-regs.h>
+#include <asm/arch/sg-regs.h>
+
+void sbc_init(void)
+{
+#if !defined(CONFIG_SPL_BUILD)
+	/* XECS0 : dummy */
+	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
+	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
+	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
+	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
+#endif
+	/* XECS1 : boot memory (always boot swap = on) */
+	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
+	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
+	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
+	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
+
+	/* XECS4 : sub memory */
+	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
+	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
+	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
+	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
+
+	/* XECS5 : peripherals */
+	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
+	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
+	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
+	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
+
+	/* base address regsiters */
+	writel(0x0000bc01, SBBASE0); /* boot memory */
+	writel(0x0900bfff, SBBASE1); /* dummy */
+	writel(0x0400bc01, SBBASE4); /* sub memory */
+	writel(0x0800bf01, SBBASE5); /* peripherals */
+
+	sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
+	sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
+
+	/* dummy read to assure write process */
+	readl(SG_PINCTRL(33));
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c
new file mode 100644
index 0000000000..a808289a56
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c
@@ -0,0 +1 @@
+#include "../ph1-ld4/sg_init.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c
new file mode 100644
index 0000000000..ff2dcb1640
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/umc-regs.h>
+
+static inline void umc_start_ssif(void __iomem *ssif_base)
+{
+	writel(0x00000000, ssif_base + 0x0000b004);
+	writel(0xffffffff, ssif_base + 0x0000c004);
+	writel(0x000fffcf, ssif_base + 0x0000c008);
+	writel(0x00000001, ssif_base + 0x0000b000);
+	writel(0x00000001, ssif_base + 0x0000c000);
+	writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+	writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+
+	writel(0x00000001, ssif_base + UMC_CPURST);
+	writel(0x00000001, ssif_base + UMC_IDSRST);
+	writel(0x00000001, ssif_base + UMC_IXMRST);
+	writel(0x00000001, ssif_base + UMC_MDMRST);
+	writel(0x00000001, ssif_base + UMC_MDDRST);
+	writel(0x00000001, ssif_base + UMC_SIORST);
+	writel(0x00000001, ssif_base + UMC_VIORST);
+	writel(0x00000001, ssif_base + UMC_FRCRST);
+	writel(0x00000001, ssif_base + UMC_RGLRST);
+	writel(0x00000001, ssif_base + UMC_AIORST);
+	writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+		       int size, int freq)
+{
+#ifdef CONFIG_DDR_STANDARD
+	writel(0x55990b11, dramcont + UMC_CMDCTLA);
+	writel(0x16958944, dramcont + UMC_CMDCTLB);
+#else
+	writel(0x45990b11, dramcont + UMC_CMDCTLA);
+	writel(0x16958924, dramcont + UMC_CMDCTLB);
+#endif
+
+	writel(0x5101046A, dramcont + UMC_INITCTLA);
+
+	if (size == 1)
+		writel(0x27028B0A, dramcont + UMC_INITCTLB);
+	else if (size == 2)
+		writel(0x38028B0A, dramcont + UMC_INITCTLB);
+
+	writel(0x00FF00FF, dramcont + UMC_INITCTLC);
+	writel(0x00000b51, dramcont + UMC_DRMMR0);
+	writel(0x00000006, dramcont + UMC_DRMMR1);
+	writel(0x00000290, dramcont + UMC_DRMMR2);
+
+#ifdef CONFIG_DDR_STANDARD
+	writel(0x00000000, dramcont + UMC_DRMMR3);
+#else
+	writel(0x00000800, dramcont + UMC_DRMMR3);
+#endif
+
+	if (size == 1)
+		writel(0x00240512, dramcont + UMC_SPCCTLA);
+	else if (size == 2)
+		writel(0x00350512, dramcont + UMC_SPCCTLA);
+
+	writel(0x00ff0006, dramcont + UMC_SPCCTLB);
+	writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
+	writel(0x04060806, dramcont + UMC_WDATACTL_D0);
+	writel(0x04a02000, dramcont + UMC_DATASET);
+	writel(0x00000000, ca_base + 0x2300);
+	writel(0x00400020, dramcont + UMC_DCCGCTL);
+	writel(0x00000003, dramcont + 0x7000);
+	writel(0x0000004f, dramcont + 0x8000);
+	writel(0x000000c3, dramcont + 0x8004);
+	writel(0x00000077, dramcont + 0x8008);
+	writel(0x0000003b, dramcont + UMC_DICGCTLA);
+	writel(0x020a0808, dramcont + UMC_DICGCTLB);
+	writel(0x00000004, dramcont + UMC_FLOWCTLG);
+	writel(0x80000201, ca_base + 0xc20);
+	writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
+	writel(0x00200000, dramcont + UMC_FLOWCTLB);
+	writel(0x00004444, dramcont + UMC_FLOWCTLC);
+	writel(0x200a0a00, dramcont + UMC_SPCSETB);
+	writel(0x00000000, dramcont + UMC_SPCSETD);
+	writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
+}
+
+static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
+{
+	void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
+	void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
+	void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
+	void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
+	void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+
+	umc_dram_init_start(dramcont0);
+	umc_dram_init_start(dramcont1);
+	umc_dram_init_poll(dramcont0);
+	umc_dram_init_poll(dramcont1);
+
+	writel(0x00000101, dramcont0 + UMC_DIOCTLA);
+
+	writel(0x00000101, dramcont1 + UMC_DIOCTLA);
+
+	umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
+	umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
+
+	umc_start_ssif(ssif_base);
+
+	return 0;
+}
+
+int umc_init(void)
+{
+	return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
+					CONFIG_SDRAM1_SIZE / 0x08000000);
+}
+
+#if CONFIG_DDR_FREQ != 1333
+#error Unsupported DDR frequency.
+#endif
+
+#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
+    (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
+    CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
+/* OK */
+#else
+#error Unsupported DDR configuration.
+#endif
diff --git a/arch/arm/cpu/armv7/uniphier/reset.c b/arch/arm/cpu/armv7/uniphier/reset.c
new file mode 100644
index 0000000000..b0dc9673b4
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/reset.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sc-regs.h>
+#include <asm/arch/board.h>
+
+void reset_cpu(unsigned long ignored)
+{
+	u32 tmp;
+
+	uniphier_board_reset();
+
+	writel(5, SC_IRQTIMSET); /* default value */
+
+	tmp  = readl(SC_SLFRSTSEL);
+	tmp &= ~0x3; /* mask [1:0] */
+	tmp |= 0x0;  /* XRST reboot */
+	writel(tmp, SC_SLFRSTSEL);
+
+	tmp = readl(SC_SLFRSTCTL);
+	tmp |= 0x1;
+	writel(tmp, SC_SLFRSTCTL);
+}
diff --git a/arch/arm/cpu/armv7/uniphier/smp.S b/arch/arm/cpu/armv7/uniphier/smp.S
new file mode 100644
index 0000000000..25ba981cea
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/smp.S
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2013 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/system.h>
+#include <asm/arch/led.h>
+#include <asm/arch/sbc-regs.h>
+
+/* Entry point of U-Boot main program for the secondary CPU */
+LENTRY(secondary_entry)
+	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Contrl Register)
+	bic	r0, r0, #(CR_C | CR_M)	@ MMU and Dcache disable
+	mcr	p15, 0, r0, c1, c0, 0
+	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
+	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
+	dsb
+	led_write(C,0,,)
+	ldr	r1, =ROM_BOOT_ROMRSV2
+	mov	r0, #0
+	str	r0, [r1]
+0:	wfe
+	ldr	r4, [r1]		@ r4: entry point for secondary CPUs
+	cmp	r4, #0
+	beq	0b
+	led_write(C, P, U, 1)
+	bx	r4			@ secondary CPUs jump to linux
+ENDPROC(secondary_entry)
+
+ENTRY(wakeup_secondary)
+	ldr	r1, =ROM_BOOT_ROMRSV2
+0:	ldr	r0, [r1]
+	cmp	r0, #0
+	bne	0b
+
+	/* set entry address and send event to the secondary CPU */
+	ldr	r0, =secondary_entry
+	str	r0, [r1]
+	ldr	r0, [r1]	@ make sure store is complete
+	mov	r0, #0x100
+0:	subs	r0, r0, #1	@ I don't know the reason, but without this wait
+	bne	0b		@ fails to wake up the secondary CPU
+	sev
+
+	/* wait until the secondary CPU reach to secondary_entry */
+0:	ldr	r0, [r1]
+	cmp	r0, #0
+	bne	0b
+	bx	lr
+ENDPROC(wakeup_secondary)
diff --git a/arch/arm/cpu/armv7/uniphier/spl.c b/arch/arm/cpu/armv7/uniphier/spl.c
new file mode 100644
index 0000000000..40d28adaf3
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/spl.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2013-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+void spl_board_init(void)
+{
+#if defined(CONFIG_BOARD_POSTCLK_INIT)
+	board_postclk_init();
+#endif
+	dram_init();
+}
diff --git a/arch/arm/cpu/armv7/uniphier/support_card.c b/arch/arm/cpu/armv7/uniphier/support_card.c
new file mode 100644
index 0000000000..40d49409c2
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/support_card.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/board.h>
+
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
+
+#define PFC_MICRO_SUPPORT_CARD_RESET	\
+				((CONFIG_SUPPORT_CARD_BASE) + 0x000D0034)
+#define PFC_MICRO_SUPPORT_CARD_REVISION	\
+				((CONFIG_SUPPORT_CARD_BASE) + 0x000D00E0)
+/*
+ * 0: reset deassert, 1: reset
+ *
+ * bit[0]: LAN, I2C, LED
+ * bit[1]: UART
+ */
+void support_card_reset_deassert(void)
+{
+	writel(0, PFC_MICRO_SUPPORT_CARD_RESET);
+}
+
+void support_card_reset(void)
+{
+	writel(3, PFC_MICRO_SUPPORT_CARD_RESET);
+}
+
+static int support_card_show_revision(void)
+{
+	u32 revision;
+
+	revision = readl(PFC_MICRO_SUPPORT_CARD_REVISION);
+	printf("(PFC CPLD version %d.%d)\n", revision >> 4, revision & 0xf);
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+
+#define DCC_MICRO_SUPPORT_CARD_RESET_LAN	\
+				((CONFIG_SUPPORT_CARD_BASE) + 0x00401300)
+#define DCC_MICRO_SUPPORT_CARD_RESET_UART	\
+				((CONFIG_SUPPORT_CARD_BASE) + 0x00401304)
+#define DCC_MICRO_SUPPORT_CARD_RESET_I2C	\
+				((CONFIG_SUPPORT_CARD_BASE) + 0x00401308)
+#define DCC_MICRO_SUPPORT_CARD_REVISION		\
+				((CONFIG_SUPPORT_CARD_BASE) + 0x005000E0)
+
+void support_card_reset_deassert(void)
+{
+	writel(1, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
+	writel(1, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
+	writel(1, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
+}
+
+void support_card_reset(void)
+{
+	writel(0, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
+	writel(0, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
+	writel(0, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
+}
+
+static int support_card_show_revision(void)
+{
+	u32 revision;
+
+	revision = readl(DCC_MICRO_SUPPORT_CARD_REVISION);
+
+	if (revision >= 0x67) {
+		printf("(DCC CPLD version 3.%d.%d)\n",
+		       revision >> 4, revision & 0xf);
+		return 0;
+	} else {
+		printf("(DCC CPLD unknown version)\n");
+		return -1;
+	}
+}
+#endif
+
+void support_card_init(void)
+{
+	/*
+	 * After power on, we need to keep the LAN controller in reset state
+	 * for a while. (200 usec)
+	 * Fortunatelly, enough wait time is already inserted in pll_init()
+	 * function. So we do not have to wait here.
+	 */
+	support_card_reset_deassert();
+}
+
+int check_support_card(void)
+{
+	printf("SC:    Micro Support Card ");
+	return support_card_show_revision();
+}
+
+#if defined(CONFIG_SMC911X)
+#include <netdev.h>
+
+int board_eth_init(bd_t *bis)
+{
+	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+#endif
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+
+#include <mtd/cfi_flash.h>
+
+#if CONFIG_SYS_MAX_FLASH_BANKS > 1
+static phys_addr_t flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS] =
+					CONFIG_SYS_FLASH_BANKS_LIST;
+
+phys_addr_t cfi_flash_bank_addr(int i)
+{
+	return flash_banks_list[i];
+}
+#endif
+
+int mem_is_flash(phys_addr_t base)
+{
+	const int loop = 128;
+	u32 *scratch_addr;
+	u32 saved_value;
+	int ret = 1;
+	int i;
+
+	scratch_addr = map_physmem(base + 0x01e00000,
+					sizeof(u32) * loop, MAP_NOCACHE);
+
+	for (i = 0; i < loop; i++, scratch_addr++) {
+		saved_value = readl(scratch_addr);
+		writel(~saved_value, scratch_addr);
+		if (readl(scratch_addr) != saved_value) {
+			/* We assume no memory or SRAM here. */
+			writel(saved_value, scratch_addr);
+			ret = 0;
+			break;
+		}
+	}
+
+	unmap_physmem(scratch_addr, MAP_NOCACHE);
+
+	return ret;
+}
+
+int board_flash_wp_on(void)
+{
+	int i;
+	int ret = 1;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		if (mem_is_flash(cfi_flash_bank_addr(i))) {
+			/*
+			 * We found at least one flash.
+			 * We need to return 0 and call flash_init().
+			 */
+			ret = 0;
+		}
+#if CONFIG_SYS_MAX_FLASH_BANKS > 1
+		else {
+			/*
+			 * We might have a SRAM here.
+			 * To prevent SRAM data from being destroyed,
+			 * we set dummy address (SDRAM).
+			 */
+			flash_banks_list[i] = 0x80000000 + 0x10000 * i;
+		}
+#endif
+	}
+
+	return ret;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/uniphier/timer.c b/arch/arm/cpu/armv7/uniphier/timer.c
new file mode 100644
index 0000000000..6edc0842a9
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/timer.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/arm-mpcore.h>
+
+#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */
+#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1)
+
+static void *get_global_timer_base(void)
+{
+	void *val;
+
+	asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (val) : : "memory");
+
+	return val + GLOBAL_TIMER_OFFSET;
+}
+
+unsigned long timer_read_counter(void)
+{
+	/*
+	 * ARM 64bit Global Timer is too much for our purpose.
+	 * We use only lower 32 bit of the timer counter.
+	 */
+	return readl(get_global_timer_base() + GTIMER_CNT_L);
+}
+
+int timer_init(void)
+{
+	/* enable timer */
+	writel(PRESCALER << 8 | 1, get_global_timer_base() + GTIMER_CTRL);
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
new file mode 100644
index 0000000000..3d1655bd5c
--- /dev/null
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -0,0 +1,6 @@
+if ARM64
+
+config SYS_CPU
+	default "armv8"
+
+endif
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
index 9249537c65..f920eebc56 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile
+++ b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
@@ -7,3 +7,5 @@
 obj-y += cpu.o
 obj-y += lowlevel.o
 obj-y += speed.o
+obj-$(CONFIG_MP) += mp.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index c129d032f4..47b947f44f 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -11,6 +11,7 @@
 #include <asm/io.h>
 #include <asm/arch-fsl-lsch3/immap_lsch3.h>
 #include "cpu.h"
+#include "mp.h"
 #include "speed.h"
 #include <fsl_mc.h>
 
@@ -434,3 +435,15 @@ int cpu_eth_init(bd_t *bis)
 #endif
 	return error;
 }
+
+
+int arch_early_init_r(void)
+{
+	int rv;
+	rv = fsl_lsch3_wake_seconday_cores();
+
+	if (rv)
+		printf("Did not wake secondary cores\n");
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h b/arch/arm/cpu/armv8/fsl-lsch3/cpu.h
index 28544d7c14..2e3312b99b 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.h
@@ -5,3 +5,4 @@
  */
 
 int fsl_qoriq_core_to_cluster(unsigned int core);
+u32 cpu_mask(void);
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
new file mode 100644
index 0000000000..e392eb9149
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include "mp.h"
+
+#ifdef CONFIG_MP
+void ft_fixup_cpu(void *blob)
+{
+	int off;
+	__maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
+	fdt32_t *reg;
+	int addr_cells;
+	u64 val;
+	size_t *boot_code_size = &(__secondary_boot_code_size);
+
+	off = fdt_path_offset(blob, "/cpus");
+	if (off < 0) {
+		puts("couldn't find /cpus node\n");
+		return;
+	}
+	of_bus_default_count_cells(blob, off, &addr_cells, NULL);
+
+	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
+	while (off != -FDT_ERR_NOTFOUND) {
+		reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
+		if (reg) {
+			val = spin_tbl_addr;
+			val += id_to_core(of_read_number(reg, addr_cells))
+				* SPIN_TABLE_ELEM_SIZE;
+			val = cpu_to_fdt64(val);
+			fdt_setprop_string(blob, off, "enable-method",
+					   "spin-table");
+			fdt_setprop(blob, off, "cpu-release-addr",
+				    &val, sizeof(val));
+		} else {
+			puts("Warning: found cpu node without reg property\n");
+		}
+		off = fdt_node_offset_by_prop_value(blob, off, "device_type",
+						    "cpu", 4);
+	}
+
+	fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code,
+			*boot_code_size);
+}
+#endif
+
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_MP
+	ft_fixup_cpu(blob);
+#endif
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
index ad32b6cd52..2a88aab283 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
@@ -8,7 +8,9 @@
 
 #include <config.h>
 #include <linux/linkage.h>
+#include <asm/gic.h>
 #include <asm/macro.h>
+#include "mp.h"
 
 ENTRY(lowlevel_init)
 	mov	x29, lr			/* Save LR */
@@ -35,31 +37,114 @@ ENTRY(lowlevel_init)
 #endif
 #endif
 
-	branch_if_master x0, x1, 1f
+	branch_if_master x0, x1, 2f
 
-	/*
-	 * Slave should wait for master clearing spin table.
-	 * This sync prevent salves observing incorrect
-	 * value of spin table and jumping to wrong place.
-	 */
-#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
-#ifdef CONFIG_GICV2
-	ldr	x0, =GICC_BASE
-#endif
-	bl	gic_wait_for_interrupt
-#endif
-
-	/*
-	 * All processors will enter EL2 and optionally EL1.
-	 */
-	bl	armv8_switch_to_el2
-#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
-	bl	armv8_switch_to_el1
-#endif
-	b	2f
-
-1:
+	ldr	x0, =secondary_boot_func
+	blr	x0
 2:
 	mov	lr, x29			/* Restore LR */
 	ret
 ENDPROC(lowlevel_init)
+
+	/* Keep literals not used by the secondary boot code outside it */
+	.ltorg
+
+	/* Using 64 bit alignment since the spin table is accessed as data */
+	.align 4
+	.global secondary_boot_code
+	/* Secondary Boot Code starts here */
+secondary_boot_code:
+	.global __spin_table
+__spin_table:
+	.space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
+
+	.align 2
+ENTRY(secondary_boot_func)
+	/*
+	 * MPIDR_EL1 Fields:
+	 * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
+	 * MPIDR[7:2] = AFF0_RES
+	 * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
+	 * MPIDR[23:16] = AFF2_CLUSTERID
+	 * MPIDR[24] = MT
+	 * MPIDR[29:25] = RES0
+	 * MPIDR[30] = U
+	 * MPIDR[31] = ME
+	 * MPIDR[39:32] = AFF3
+	 *
+	 * Linear Processor ID (LPID) calculation from MPIDR_EL1:
+	 * (We only use AFF0_CPUID and AFF1_CLUSTERID for now
+	 * until AFF2_CLUSTERID and AFF3 have non-zero values)
+	 *
+	 * LPID = MPIDR[15:8] | MPIDR[1:0]
+	 */
+	mrs	x0, mpidr_el1
+	ubfm	x1, x0, #8, #15
+	ubfm	x2, x0, #0, #1
+	orr	x10, x2, x1, lsl #2	/* x10 has LPID */
+	ubfm    x9, x0, #0, #15         /* x9 contains MPIDR[15:0] */
+	/*
+	 * offset of the spin table element for this core from start of spin
+	 * table (each elem is padded to 64 bytes)
+	 */
+	lsl	x1, x10, #6
+	ldr	x0, =__spin_table
+	/* physical address of this cpus spin table element */
+	add	x11, x1, x0
+
+	str	x9, [x11, #16]	/* LPID */
+	mov	x4, #1
+	str	x4, [x11, #8]	/* STATUS */
+	dsb	sy
+#if defined(CONFIG_GICV3)
+	gic_wait_for_interrupt_m x0
+#elif defined(CONFIG_GICV2)
+        ldr     x0, =GICC_BASE
+        gic_wait_for_interrupt_m x0, w1
+#endif
+
+	bl secondary_switch_to_el2
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+	bl secondary_switch_to_el1
+#endif
+
+slave_cpu:
+	wfe
+	ldr	x0, [x11]
+	cbz	x0, slave_cpu
+#ifndef CONFIG_ARMV8_SWITCH_TO_EL1
+	mrs     x1, sctlr_el2
+#else
+	mrs     x1, sctlr_el1
+#endif
+	tbz     x1, #25, cpu_is_le
+	rev     x0, x0                  /* BE to LE conversion */
+cpu_is_le:
+	br	x0			/* branch to the given address */
+ENDPROC(secondary_boot_func)
+
+ENTRY(secondary_switch_to_el2)
+	switch_el x0, 1f, 0f, 0f
+0:	ret
+1:	armv8_switch_to_el2_m x0
+ENDPROC(secondary_switch_to_el2)
+
+ENTRY(secondary_switch_to_el1)
+	switch_el x0, 0f, 1f, 0f
+0:	ret
+1:	armv8_switch_to_el1_m x0, x1
+ENDPROC(secondary_switch_to_el1)
+
+	/* Ensure that the literals used by the secondary boot code are
+	 * assembled within it (this is required so that we can protect
+	 * this area with a single memreserve region
+	 */
+	.ltorg
+
+	/* 64 bit alignment for elements accessed as data */
+	.align 4
+	.globl __secondary_boot_code_size
+	.type __secondary_boot_code_size, %object
+	/* Secondary Boot Code ends here */
+__secondary_boot_code_size:
+	.quad .-secondary_boot_code
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
new file mode 100644
index 0000000000..94998bf37b
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include "mp.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void *get_spin_tbl_addr(void)
+{
+	return &__spin_table;
+}
+
+phys_addr_t determine_mp_bootpg(void)
+{
+	return (phys_addr_t)&secondary_boot_code;
+}
+
+int fsl_lsch3_wake_seconday_cores(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+	u32 cores, cpu_up_mask = 1;
+	int i, timeout = 10;
+	u64 *table = get_spin_tbl_addr();
+
+	cores = cpu_mask();
+	/* Clear spin table so that secondary processors
+	 * observe the correct value after waking up from wfe.
+	 */
+	memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE);
+	flush_dcache_range((unsigned long)table,
+			   (unsigned long)table +
+			   (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
+
+	printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
+	out_le32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
+	out_le32(&gur->bootlocptrl, (u32)gd->relocaddr);
+	out_le32(&gur->scratchrw[6], 1);
+	asm volatile("dsb st" : : : "memory");
+	rst->brrl = cores;
+	asm volatile("dsb st" : : : "memory");
+
+	/* This is needed as a precautionary measure.
+	 * If some code before this has accidentally  released the secondary
+	 * cores then the pre-bootloader code will trap them in a "wfe" unless
+	 * the scratchrw[6] is set. In this case we need a sev here to get these
+	 * cores moving again.
+	 */
+	asm volatile("sev");
+
+	while (timeout--) {
+		flush_dcache_range((unsigned long)table, (unsigned long)table +
+				   CONFIG_MAX_CPUS * 64);
+		for (i = 1; i < CONFIG_MAX_CPUS; i++) {
+			if (table[i * WORDS_PER_SPIN_TABLE_ENTRY +
+					SPIN_TABLE_ELEM_STATUS_IDX])
+				cpu_up_mask |= 1 << i;
+		}
+		if (hweight32(cpu_up_mask) == hweight32(cores))
+			break;
+		udelay(10);
+	}
+	if (timeout <= 0) {
+		printf("Not all cores (0x%x) are up (0x%x)\n",
+		       cores, cpu_up_mask);
+		return 1;
+	}
+	printf("All (%d) cores are up.\n", hweight32(cores));
+
+	return 0;
+}
+
+int is_core_valid(unsigned int core)
+{
+	return !!((1 << core) & cpu_mask());
+}
+
+int cpu_reset(int nr)
+{
+	puts("Feature is not implemented.\n");
+
+	return 0;
+}
+
+int cpu_disable(int nr)
+{
+	puts("Feature is not implemented.\n");
+
+	return 0;
+}
+
+int core_to_pos(int nr)
+{
+	u32 cores = cpu_mask();
+	int i, count = 0;
+
+	if (nr == 0) {
+		return 0;
+	} else if (nr >= hweight32(cores)) {
+		puts("Not a valid core number.\n");
+		return -1;
+	}
+
+	for (i = 1; i < 32; i++) {
+		if (is_core_valid(i)) {
+			count++;
+			if (count == nr)
+				break;
+		}
+	}
+
+	return count;
+}
+
+int cpu_status(int nr)
+{
+	u64 *table;
+	int pos;
+
+	if (nr == 0) {
+		table = (u64 *)get_spin_tbl_addr();
+		printf("table base @ 0x%p\n", table);
+	} else {
+		pos = core_to_pos(nr);
+		if (pos < 0)
+			return -1;
+		table = (u64 *)get_spin_tbl_addr() + pos *
+			WORDS_PER_SPIN_TABLE_ENTRY;
+		printf("table @ 0x%p\n", table);
+		printf("   addr - 0x%016llx\n",
+		       table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]);
+		printf("   status   - 0x%016llx\n",
+		       table[SPIN_TABLE_ELEM_STATUS_IDX]);
+		printf("   lpid  - 0x%016llx\n",
+		       table[SPIN_TABLE_ELEM_LPID_IDX]);
+	}
+
+	return 0;
+}
+
+int cpu_release(int nr, int argc, char * const argv[])
+{
+	u64 boot_addr;
+	u64 *table = (u64 *)get_spin_tbl_addr();
+	int pos;
+
+	pos = core_to_pos(nr);
+	if (pos <= 0)
+		return -1;
+
+	table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
+	boot_addr = simple_strtoull(argv[0], NULL, 16);
+	table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
+	flush_dcache_range((unsigned long)table,
+			   (unsigned long)table + SPIN_TABLE_ELEM_SIZE);
+	asm volatile("dsb st");
+	smp_kick_all_cpus();	/* only those with entry addr set will run */
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h b/arch/arm/cpu/armv8/fsl-lsch3/mp.h
new file mode 100644
index 0000000000..06ac0bcf36
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2014, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _FSL_CH3_MP_H
+#define _FSL_CH3_MP_H
+
+/*
+* Each spin table element is defined as
+* struct {
+*      uint64_t entry_addr;
+*      uint64_t status;
+*      uint64_t lpid;
+* };
+* we pad this struct to 64 bytes so each entry is in its own cacheline
+* the actual spin table is an array of these structures
+*/
+#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX	0
+#define SPIN_TABLE_ELEM_STATUS_IDX	1
+#define SPIN_TABLE_ELEM_LPID_IDX	2
+#define WORDS_PER_SPIN_TABLE_ENTRY	8	/* pad to 64 bytes */
+#define SPIN_TABLE_ELEM_SIZE		64
+
+#define id_to_core(x)	((x & 3) | (x >> 6))
+#ifndef __ASSEMBLY__
+extern u64 __spin_table[];
+extern u64 *secondary_boot_code;
+extern size_t __secondary_boot_code_size;
+int fsl_lsch3_wake_seconday_cores(void);
+void *get_spin_tbl_addr(void);
+phys_addr_t determine_mp_bootpg(void);
+void secondary_boot_func(void);
+#endif
+#endif /* _FSL_CH3_MP_H */
diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
index 38dea5c518..ade1cdead8 100644
--- a/arch/arm/cpu/armv8/transition.S
+++ b/arch/arm/cpu/armv8/transition.S
@@ -14,70 +14,11 @@
 ENTRY(armv8_switch_to_el2)
 	switch_el x0, 1f, 0f, 0f
 0:	ret
-1:
-	mov	x0, #0x5b1	/* Non-secure EL0/EL1 | HVC | 64bit EL2 */
-	msr	scr_el3, x0
-	msr	cptr_el3, xzr	/* Disable coprocessor traps to EL3 */
-	mov	x0, #0x33ff
-	msr	cptr_el2, x0	/* Disable coprocessor traps to EL2 */
-
-	/* Initialize SCTLR_EL2 */
-	msr	sctlr_el2, xzr
-
-	/* Return to the EL2_SP2 mode from EL3 */
-	mov	x0, sp
-	msr	sp_el2, x0	/* Migrate SP */
-	mrs	x0, vbar_el3
-	msr	vbar_el2, x0	/* Migrate VBAR */
-	mov	x0, #0x3c9
-	msr	spsr_el3, x0	/* EL2_SP2 | D | A | I | F */
-	msr	elr_el3, lr
-	eret
+1:	armv8_switch_to_el2_m x0
 ENDPROC(armv8_switch_to_el2)
 
 ENTRY(armv8_switch_to_el1)
 	switch_el x0, 0f, 1f, 0f
 0:	ret
-1:
-	/* Initialize Generic Timers */
-	mrs	x0, cnthctl_el2
-	orr	x0, x0, #0x3		/* Enable EL1 access to timers */
-	msr	cnthctl_el2, x0
-	msr	cntvoff_el2, xzr
-	mrs	x0, cntkctl_el1
-	orr	x0, x0, #0x3		/* Enable EL0 access to timers */
-	msr	cntkctl_el1, x0
-
-	/* Initilize MPID/MPIDR registers */
-	mrs	x0, midr_el1
-	mrs	x1, mpidr_el1
-	msr	vpidr_el2, x0
-	msr	vmpidr_el2, x1
-
-	/* Disable coprocessor traps */
-	mov	x0, #0x33ff
-	msr	cptr_el2, x0		/* Disable coprocessor traps to EL2 */
-	msr	hstr_el2, xzr		/* Disable coprocessor traps to EL2 */
-	mov	x0, #3 << 20
-	msr	cpacr_el1, x0		/* Enable FP/SIMD at EL1 */
-
-	/* Initialize HCR_EL2 */
-	mov	x0, #(1 << 31)		/* 64bit EL1 */
-	orr	x0, x0, #(1 << 29)	/* Disable HVC */
-	msr	hcr_el2, x0
-
-	/* SCTLR_EL1 initialization */
-	mov	x0, #0x0800
-	movk	x0, #0x30d0, lsl #16
-	msr	sctlr_el1, x0
-
-	/* Return to the EL1_SP1 mode from EL2 */
-	mov	x0, sp
-	msr	sp_el1, x0		/* Migrate SP */
-	mrs	x0, vbar_el2
-	msr	vbar_el1, x0		/* Migrate VBAR */
-	mov	x0, #0x3c5
-	msr	spsr_el2, x0		/* EL1_SP1 | D | A | I | F */
-	msr	elr_el2, lr
-	eret
+1:	armv8_switch_to_el1_m x0, x1
 ENDPROC(armv8_switch_to_el1)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1ccd8274d2..5f2b946fdd 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -9,7 +9,6 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 	exynos5250-smdk5250.dtb \
 	exynos5420-smdk5420.dtb \
 	exynos5420-peach-pit.dtb
-dtb-$(CONFIG_MX6) += imx6q-sabreauto.dtb
 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra20-medcom-wide.dtb \
 	tegra20-paz00.dtb \
diff --git a/arch/arm/dts/imx6q-sabreauto.dts b/arch/arm/dts/imx6q-sabreauto.dts
deleted file mode 100644
index 7af2a88fd0..0000000000
--- a/arch/arm/dts/imx6q-sabreauto.dts
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-/dts-v1/;
-
-/ {
-	model = "Freescale i.MX6 Quad SABRE Automotive Board";
-	compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
-};
diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h
index 04f6239fd0..27331ff2d1 100644
--- a/arch/arm/include/asm/arch-at91/at91_pmc.h
+++ b/arch/arm/include/asm/arch-at91/at91_pmc.h
@@ -54,7 +54,7 @@ typedef struct at91_pmc {
 	u32	reserved5[21];
 	u32	wpmr;		/* 0xE4 Write Protect Mode Register (CAP0) */
 	u32	wpsr;		/* 0xE8 Write Protect Status Register (CAP0) */
-#ifdef CONFIG_SAMA5D3
+#ifdef CPU_HAS_PCR
 	u32	reserved6[8];
 	u32	pcer1;		/* 0x100 Periperial Clock Enable Register 1 */
 	u32	pcdr1;		/* 0x104 Periperial Clock Disable Register 1 */
@@ -147,6 +147,10 @@ typedef struct at91_pmc {
 #define AT91_PMC_IXR_PCKRDY3		0x00000800
 #define AT91_PMC_IXR_MOSCSELS		0x00010000
 
+#define AT91_PMC_PCR_PID_MASK		(0x3f)
+#define AT91_PMC_PCR_CMD_WRITE		(0x1 << 12)
+#define AT91_PMC_PCR_EN			(0x1 << 28)
+
 #define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
 #define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */
 #define		AT91RM9200_PMC_MCKUDP	(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
diff --git a/arch/arm/include/asm/arch-at91/clk.h b/arch/arm/include/asm/arch-at91/clk.h
index ce9e28f11c..4076a78a86 100644
--- a/arch/arm/include/asm/arch-at91/clk.h
+++ b/arch/arm/include/asm/arch-at91/clk.h
@@ -80,4 +80,5 @@ static inline unsigned long get_mci_clk_rate(void)
 
 int at91_clock_init(unsigned long main_clock);
 void at91_periph_clk_enable(int id);
+void at91_periph_clk_disable(int id);
 #endif /* __ASM_ARM_ARCH_CLK_H__ */
diff --git a/arch/arm/include/asm/arch-at91/sama5d3.h b/arch/arm/include/asm/arch-at91/sama5d3.h
index 6d936f47fa..f7bc4ad338 100644
--- a/arch/arm/include/asm/arch-at91/sama5d3.h
+++ b/arch/arm/include/asm/arch-at91/sama5d3.h
@@ -188,6 +188,7 @@
 #define ATMEL_PIO_PORTS		5
 #define CPU_HAS_PIO3
 #define PIO_SCDR_DIV		0x3fff
+#define CPU_HAS_PCR
 
 /*
  * PMECC table in ROM
diff --git a/arch/arm/include/asm/arch-at91/sama5d3_smc.h b/arch/arm/include/asm/arch-at91/sama5d3_smc.h
index 6caa9b6ed8..a859b6db9b 100644
--- a/arch/arm/include/asm/arch-at91/sama5d3_smc.h
+++ b/arch/arm/include/asm/arch-at91/sama5d3_smc.h
@@ -14,7 +14,8 @@
 #define AT91_ASM_SMC_SETUP0	(ATMEL_BASE_SMC + 0x600)
 #define AT91_ASM_SMC_PULSE0	(ATMEL_BASE_SMC + 0x604)
 #define AT91_ASM_SMC_CYCLE0	(ATMEL_BASE_SMC + 0x608)
-#define AT91_ASM_SMC_MODE0	(ATMEL_BASE_SMC + 0x60C)
+#define AT91_ASM_SMC_TIMINGS0	(ATMEL_BASE_SMC + 0x60c)
+#define AT91_ASM_SMC_MODE0	(ATMEL_BASE_SMC + 0x610)
 #else
 struct at91_cs {
 	u32	setup;		/* 0x600 SMC Setup Register */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index b17410a58a..da551e8839 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -8,7 +8,7 @@
 #define _ASM_ARMV8_FSL_LSCH3_CONFIG_
 
 #include <fsl_ddrc_version.h>
-
+#define CONFIG_MP
 #define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000	/* initial RAM */
 /* Link Definitions */
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
@@ -16,8 +16,10 @@
 #define CONFIG_SYS_IMMR				0x01000000
 #define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
 #define CONFIG_SYS_FSL_DDR2_ADDR		(CONFIG_SYS_IMMR + 0x00090000)
+#define CONFIG_SYS_FSL_DDR3_ADDR		0x08210000
 #define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00E00000)
 #define CONFIG_SYS_FSL_PMU_ADDR			(CONFIG_SYS_IMMR + 0x00E30000)
+#define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00E60000)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR	(CONFIG_SYS_IMMR + 0x00300000)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR	(CONFIG_SYS_IMMR + 0x00310000)
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR + 0x00370000)
@@ -60,7 +62,7 @@
 #ifdef CONFIG_LS2085A
 #define CONFIG_MAX_CPUS				16
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
-#define CONFIG_NUM_DDR_CONTROLLERS		2
+#define CONFIG_NUM_DDR_CONTROLLERS		3
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
 #else
 #error SoC not defined
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
index 18e66bdf41..ee1d6512d9 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
@@ -113,4 +113,39 @@ struct ccsr_clk_ctrl {
 		u8  res_04[0x20-0x04];
 	} clkcncsr[8];
 };
+
+struct ccsr_reset {
+	u32 rstcr;			/* 0x000 */
+	u32 rstcrsp;			/* 0x004 */
+	u8 res_008[0x10-0x08];		/* 0x008 */
+	u32 rstrqmr1;			/* 0x010 */
+	u32 rstrqmr2;			/* 0x014 */
+	u32 rstrqsr1;			/* 0x018 */
+	u32 rstrqsr2;			/* 0x01c */
+	u32 rstrqwdtmrl;		/* 0x020 */
+	u32 rstrqwdtmru;		/* 0x024 */
+	u8 res_028[0x30-0x28];		/* 0x028 */
+	u32 rstrqwdtsrl;		/* 0x030 */
+	u32 rstrqwdtsru;		/* 0x034 */
+	u8 res_038[0x60-0x38];		/* 0x038 */
+	u32 brrl;			/* 0x060 */
+	u32 brru;			/* 0x064 */
+	u8 res_068[0x80-0x68];		/* 0x068 */
+	u32 pirset;			/* 0x080 */
+	u32 pirclr;			/* 0x084 */
+	u8 res_088[0x90-0x88];		/* 0x088 */
+	u32 brcorenbr;			/* 0x090 */
+	u8 res_094[0x100-0x94];		/* 0x094 */
+	u32 rcw_reqr;			/* 0x100 */
+	u32 rcw_completion;		/* 0x104 */
+	u8 res_108[0x110-0x108];	/* 0x108 */
+	u32 pbi_reqr;			/* 0x110 */
+	u32 pbi_completion;		/* 0x114 */
+	u8 res_118[0xa00-0x118];	/* 0x118 */
+	u32 qmbm_warmrst;		/* 0xa00 */
+	u32 soc_warmrst;		/* 0xa04 */
+	u8 res_a08[0xbf8-0xa08];	/* 0xa08 */
+	u32 ip_rev1;			/* 0xbf8 */
+	u32 ip_rev2;			/* 0xbfc */
+};
 #endif /* __ARCH_FSL_LSCH3_IMMAP_H */
diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h
index 4d229a25fa..6bf35d3543 100644
--- a/arch/arm/include/asm/arch-keystone/ddr3.h
+++ b/arch/arm/include/asm/arch-keystone/ddr3.h
@@ -50,6 +50,7 @@ struct ddr3_emif_config {
 
 void ddr3_init(void);
 void ddr3_reset_ddrphy(void);
+void ddr3_err_reset_workaround(void);
 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
 
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index d6726a1eca..76e6441e57 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -121,9 +121,11 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_CLOCK_BASE			KS2_PLL_CNTRL_BASE
 #define KS2_RSTCTRL_RSTYPE		(KS2_PLL_CNTRL_BASE + 0xe4)
 #define KS2_RSTCTRL			(KS2_PLL_CNTRL_BASE + 0xe8)
+#define KS2_RSTCTRL_RSCFG		(KS2_PLL_CNTRL_BASE + 0xec)
 #define KS2_RSTCTRL_KEY			0x5a69
 #define KS2_RSTCTRL_MASK		0xffff0000
 #define KS2_RSTCTRL_SWRST		0xfffe0000
+#define KS2_RSTYPE_PLL_SOFT		BIT(13)
 
 /* SPI */
 #define KS2_SPI0_BASE			0x21000400
diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h b/arch/arm/include/asm/arch-kirkwood/spi.h
index b1cf614ca9..e512dcec16 100644
--- a/arch/arm/include/asm/arch-kirkwood/spi.h
+++ b/arch/arm/include/asm/arch-kirkwood/spi.h
@@ -43,10 +43,10 @@ struct kwspi_registers {
 #define KWSPI_XFERLEN_2BYTE	(1 << 5)
 #define KWSPI_XFERLEN_MASK	(1 << 5)
 #define KWSPI_ADRLEN_1BYTE	0
-#define KWSPI_ADRLEN_2BYTE	1 << 8
-#define KWSPI_ADRLEN_3BYTE	2 << 8
-#define KWSPI_ADRLEN_4BYTE	3 << 8
-#define KWSPI_ADRLEN_MASK	3 << 8
+#define KWSPI_ADRLEN_2BYTE	(1 << 8)
+#define KWSPI_ADRLEN_3BYTE	(2 << 8)
+#define KWSPI_ADRLEN_4BYTE	(3 << 8)
+#define KWSPI_ADRLEN_MASK	(3 << 8)
 #define KWSPI_TIMEOUT		10000
 
 #endif /* __KW_SPI_H__ */
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index ed78c33e0a..a500b5bc3b 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -50,7 +50,11 @@
 #ifdef CONFIG_DDR_SPD
 #define CONFIG_SYS_FSL_DDR_BE
 #define CONFIG_VERY_BIG_RAM
+#ifdef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDRC_GEN4
+#else
 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3
+#endif
 #define CONFIG_SYS_FSL_DDR
 #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
@@ -71,6 +75,7 @@
 #define CONFIG_MAX_CPUS				2
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
 #define CONFIG_NUM_DDR_CONTROLLERS		1
+#define CONFIG_SYS_FSL_DDR_VER			FSL_DDR_VER_5_0
 #else
 #error SoC not defined
 #endif
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 339c789110..c11674ff8a 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -52,12 +52,17 @@ enum enet_freq {
 u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);
+void setup_gpmi_io_clk(u32 cfg);
 void enable_ocotp_clk(unsigned char enable);
 void enable_usboh3_clk(unsigned char enable);
+void enable_uart_clk(unsigned char enable);
+int enable_cspi_clock(unsigned char enable, unsigned spi_num);
+int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
 int enable_sata_clock(void);
 int enable_pcie_clock(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 int enable_spi_clk(unsigned char enable, unsigned spi_num);
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(enum enet_freq freq);
+void enable_enet_clk(unsigned char enable);
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 2631beb924..22614fcd0e 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -419,6 +419,19 @@ struct iomuxc {
 	u32 gpr[14];
 };
 
+struct gpc {
+	u32	cntr;
+	u32	pgr;
+	u32	imr1;
+	u32	imr2;
+	u32	imr3;
+	u32	imr4;
+	u32	isr1;
+	u32	isr2;
+	u32	isr3;
+	u32	isr4;
+};
+
 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET		20
 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK		(3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET		16
diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h
index f54db6944d..9b3a91f076 100644
--- a/arch/arm/include/asm/arch-mx6/iomux.h
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@@ -18,6 +18,12 @@
 #define IOMUXC_GPR1_REF_SSP_EN			(1 << 16)
 #define IOMUXC_GPR1_TEST_POWERDOWN		(1 << 18)
 
+/*
+ * IOMUXC_GPR5 bit fields
+ */
+#define IOMUXC_GPR5_PCIE_BTNRST			(1 << 19)
+#define IOMUXC_GPR5_PCIE_PERST			(1 << 18)
+
 /*
  * IOMUXC_GPR8 bit fields
  */
@@ -35,12 +41,15 @@
 /*
  * IOMUXC_GPR12 bit fields
  */
+#define IOMUXC_GPR12_RX_EQ_2			(0x2 << 0)
+#define IOMUXC_GPR12_RX_EQ_MASK			(0x7 << 0)
 #define IOMUXC_GPR12_LOS_LEVEL_9		(0x9 << 4)
 #define IOMUXC_GPR12_LOS_LEVEL_MASK		(0x1f << 4)
 #define IOMUXC_GPR12_APPS_LTSSM_ENABLE		(1 << 10)
 #define IOMUXC_GPR12_DEVICE_TYPE_EP		(0x0 << 12)
 #define IOMUXC_GPR12_DEVICE_TYPE_RC		(0x4 << 12)
 #define IOMUXC_GPR12_DEVICE_TYPE_MASK		(0xf << 12)
+#define IOMUXC_GPR12_TEST_POWERDOWN		(1 << 30)
 
 /*
  * IOMUXC_GPR13 bit fields
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 306d6998ce..c35a905141 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -20,8 +20,9 @@ u32 get_cpu_rev(void);
 /* returns MXC_CPU_ value */
 #define cpu_type(rev) (((rev) >> 12)&0xff)
 
-/* use with MXC_CPU_ constants */
-#define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu)
+/* both macros return/take MXC_CPU_ constants */
+#define get_cpu_type()	(cpu_type(get_cpu_rev()))
+#define is_cpu_type(cpu) (get_cpu_type() == cpu)
 
 const char *get_imx_type(u32 imxtype);
 unsigned imx_ddr_size(void);
diff --git a/arch/arm/include/asm/arch-uniphier/arm-mpcore.h b/arch/arm/include/asm/arch-uniphier/arm-mpcore.h
new file mode 100644
index 0000000000..cf7cd46c10
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/arm-mpcore.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_ARM_MPCORE_H
+#define ARCH_ARM_MPCORE_H
+
+/* Snoop Control Unit */
+#define SCU_OFFSET		0x00
+
+/* SCU Control Register */
+#define SCU_CTRL		0x00
+/* SCU Configuration Register */
+#define SCU_CONF		0x04
+/* SCU CPU Power Status Register */
+#define SCU_PWR_STATUS		0x08
+/* SCU Invalidate All Registers in Secure State */
+#define SCU_INV_ALL		0x0C
+/* SCU Filtering Start Address Register */
+#define SCU_FILTER_START	0x40
+/* SCU Filtering End Address Register */
+#define SCU_FILTER_END		0x44
+/* SCU Access Control Register */
+#define SCU_SAC			0x50
+/* SCU Non-secure Access Control Register */
+#define SCU_SNSAC		0x54
+
+/* Global Timer */
+#define GLOBAL_TIMER_OFFSET	0x200
+
+/* Global Timer Counter Registers */
+#define GTIMER_CNT_L		0x00
+#define GTIMER_CNT_H		0x04
+/* Global Timer Control Register */
+#define GTIMER_CTRL		0x08
+/* Global Timer Interrupt Status Register */
+#define GTIMER_STAT		0x0C
+/* Comparator Value Registers */
+#define GTIMER_CMP_L		0x10
+#define GTIMER_CMP_H		0x14
+/* Auto-increment Register */
+#define GTIMER_INC		0x18
+
+#endif /* ARCH_ARM_MPCORE_H */
diff --git a/arch/arm/include/asm/arch-uniphier/bcu-regs.h b/arch/arm/include/asm/arch-uniphier/bcu-regs.h
new file mode 100644
index 0000000000..0dfd94e5d7
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/bcu-regs.h
@@ -0,0 +1,30 @@
+/*
+ * UniPhier BCU (Bus Control Unit) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_BCU_REGS_H
+#define ARCH_BCU_REGS_H
+
+#define	BCU_BASE		0x50080000
+
+#define	BCSCR(x)                (BCU_BASE + 0x180 + (x) * 4)
+#define	BCSCR0			(BCSCR(0))
+#define	BCSCR1			(BCSCR(1))
+#define	BCSCR2			(BCSCR(2))
+#define	BCSCR3			(BCSCR(3))
+#define	BCSCR4			(BCSCR(4))
+#define	BCSCR5			(BCSCR(5))
+
+#define	BCIPPCCHR(x)		(BCU_BASE + 0x0280 + (x) * 4)
+#define	BCIPPCCHR0		(BCIPPCCHR(0))
+#define	BCIPPCCHR1		(BCIPPCCHR(1))
+#define	BCIPPCCHR2		(BCIPPCCHR(2))
+#define	BCIPPCCHR3		(BCIPPCCHR(3))
+#define	BCIPPCCHR4		(BCIPPCCHR(4))
+#define	BCIPPCCHR5		(BCIPPCCHR(5))
+
+#endif  /* ARCH_BCU_REGS_H */
diff --git a/arch/arm/include/asm/arch-uniphier/board.h b/arch/arm/include/asm/arch-uniphier/board.h
new file mode 100644
index 0000000000..e6ba4e4ee4
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/board.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_BOARD_H
+#define ARCH_BOARD_H
+
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) || \
+	defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+void support_card_reset(void);
+void support_card_init(void);
+int check_support_card(void);
+#else
+#define support_card_reset() do {} while (0)
+#define support_card_init()  do {} while (0)
+static inline int check_support_card(void)
+{
+	return 0;
+}
+#endif
+
+static inline void uniphier_board_reset(void)
+{
+	support_card_reset();
+}
+
+static inline void uniphier_board_init(void)
+{
+	support_card_init();
+}
+
+#endif /* ARCH_BOARD_H */
diff --git a/arch/arm/include/asm/arch-uniphier/boot-device.h b/arch/arm/include/asm/arch-uniphier/boot-device.h
new file mode 100644
index 0000000000..6987f57669
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/boot-device.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_BOOT_DEVICE_H_
+#define _ASM_BOOT_DEVICE_H_
+
+u32 get_boot_mode_sel(void);
+
+struct boot_device_info {
+	u32 type;
+	char *info;
+};
+
+extern struct boot_device_info boot_device_table[];
+
+#endif /* _ASM_BOOT_DEVICE_H_ */
diff --git a/arch/arm/include/asm/arch-uniphier/led.h b/arch/arm/include/asm/arch-uniphier/led.h
new file mode 100644
index 0000000000..21277dac76
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/led.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_LED_H
+#define ARCH_LED_H
+
+#include <config.h>
+
+#define LED_CHAR_0	0x7e
+#define LED_CHAR_1	0x0c
+#define LED_CHAR_2	0xb6
+#define LED_CHAR_3	0x9e
+#define LED_CHAR_4	0xcc
+#define LED_CHAR_5	0xda
+#define LED_CHAR_6	0xfa
+#define LED_CHAR_7	0x4e
+#define LED_CHAR_8	0xfe
+#define LED_CHAR_9	0xde
+
+#define LED_CHAR_A	0xee
+#define LED_CHAR_B	0xf8
+#define LED_CHAR_C	0x72
+#define LED_CHAR_D	0xbc
+#define LED_CHAR_E	0xf2
+#define LED_CHAR_F	0xe2
+#define LED_CHAR_G	0x7a
+#define LED_CHAR_H	0xe8
+#define LED_CHAR_I	0x08
+#define LED_CHAR_J	0x3c
+#define LED_CHAR_K	0xea
+#define LED_CHAR_L	0x70
+#define LED_CHAR_M	0x6e
+#define LED_CHAR_N	0xa8
+#define LED_CHAR_O	0xb8
+#define LED_CHAR_P	0xe6
+#define LED_CHAR_Q	0xce
+#define LED_CHAR_R	0xa0
+#define LED_CHAR_S	0xc8
+#define LED_CHAR_T	0x8c
+#define LED_CHAR_U	0x7c
+#define LED_CHAR_V	0x54
+#define LED_CHAR_W	0xfc
+#define LED_CHAR_X	0xec
+#define LED_CHAR_Y	0xdc
+#define LED_CHAR_Z	0xa4
+
+#define LED_CHAR_SPACE	0x00
+#define LED_CHAR_DOT	0x01
+
+#define LED_CHAR_	(LED_CHAR_SPACE)
+
+/** Macro to translate 4 characters into integer to display led */
+#define LED_C2I(C0, C1, C2, C3)			\
+	(~(					\
+		(LED_CHAR_##C0 << 24) |		\
+		(LED_CHAR_##C1 << 16) |		\
+		(LED_CHAR_##C2 <<  8) |		\
+		(LED_CHAR_##C3)			\
+	))
+
+#if defined(CONFIG_SUPPORT_CARD_LED_BASE)
+
+#define LED_ADDR    CONFIG_SUPPORT_CARD_LED_BASE
+
+#ifdef __ASSEMBLY__
+
+#define led_write(C0, C1, C2, C3)  raw_led_write LED_C2I(C0, C1, C2, C3)
+.macro raw_led_write data
+	ldr r0, =\data
+	ldr r1, =LED_ADDR
+	str r0, [r1]
+.endm
+
+#else /* __ASSEMBLY__ */
+
+#include <asm/io.h>
+
+#define led_write(C0, C1, C2, C3)		\
+do {						\
+	raw_led_write(LED_C2I(C0, C1, C2, C3));	\
+} while (0)
+
+static inline void raw_led_write(u32 data)
+{
+	writel(data, LED_ADDR);
+}
+
+#endif /* __ASSEMBLY__ */
+
+#else /* CONFIG_SUPPORT_CARD_LED_BASE */
+
+#define led_write(C0, C1, C2, C3)
+#define raw_led_write(x)
+
+#endif /* CONFIG_SUPPORT_CARD_LED_BASE */
+
+#endif /* ARCH_LED_H */
diff --git a/arch/arm/include/asm/arch-uniphier/sbc-regs.h b/arch/arm/include/asm/arch-uniphier/sbc-regs.h
new file mode 100644
index 0000000000..8e410788ef
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/sbc-regs.h
@@ -0,0 +1,108 @@
+/*
+ * UniPhier SBC (System Bus Controller) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_SBC_REGS_H
+#define ARCH_SBC_REGS_H
+
+#define	SBBASE_BASE		0x58c00100
+#define	SBBASE(x)		(SBBASE_BASE + (x) * 0x10)
+
+#define	SBBASE0			(SBBASE(0))
+#define	SBBASE1			(SBBASE(1))
+#define	SBBASE2			(SBBASE(2))
+#define	SBBASE3			(SBBASE(3))
+#define	SBBASE4			(SBBASE(4))
+#define	SBBASE5			(SBBASE(5))
+#define	SBBASE6			(SBBASE(6))
+#define	SBBASE7			(SBBASE(7))
+
+#define	SBBASE_BANK_ENABLE	(0x00000001)
+
+#define	SBCTRL_BASE		0x58c00200
+#define	SBCTRL(x, y)		(SBCTRL_BASE + (x) * 0x10 + (y) * 4)
+
+#define	SBCTRL00		SBCTRL(0, 0)
+#define	SBCTRL01		SBCTRL(0, 1)
+#define	SBCTRL02		SBCTRL(0, 2)
+#define	SBCTRL03		SBCTRL(0, 3)
+#define	SBCTRL04		(SBCTRL_BASE + 0x100)
+
+#define	SBCTRL10		SBCTRL(1, 0)
+#define	SBCTRL11		SBCTRL(1, 1)
+#define	SBCTRL12		SBCTRL(1, 2)
+#define	SBCTRL13		SBCTRL(1, 3)
+#define	SBCTRL14		(SBCTRL_BASE + 0x110)
+
+#define	SBCTRL20		SBCTRL(2, 0)
+#define	SBCTRL21		SBCTRL(2, 1)
+#define	SBCTRL22		SBCTRL(2, 2)
+#define	SBCTRL23		SBCTRL(2, 3)
+#define	SBCTRL24		(SBCTRL_BASE + 0x120)
+
+#define	SBCTRL30		SBCTRL(3, 0)
+#define	SBCTRL31		SBCTRL(3, 1)
+#define	SBCTRL32		SBCTRL(3, 2)
+#define	SBCTRL33		SBCTRL(3, 3)
+#define	SBCTRL34		(SBCTRL_BASE + 0x130)
+
+#define	SBCTRL40		SBCTRL(4, 0)
+#define	SBCTRL41		SBCTRL(4, 1)
+#define	SBCTRL42		SBCTRL(4, 2)
+#define	SBCTRL43		SBCTRL(4, 3)
+#define	SBCTRL44		(SBCTRL_BASE + 0x140)
+
+#define	SBCTRL50		SBCTRL(5, 0)
+#define	SBCTRL51		SBCTRL(5, 1)
+#define	SBCTRL52		SBCTRL(5, 2)
+#define	SBCTRL53		SBCTRL(5, 3)
+#define	SBCTRL54		(SBCTRL_BASE + 0x150)
+
+#define	SBCTRL60		SBCTRL(6, 0)
+#define	SBCTRL61		SBCTRL(6, 1)
+#define	SBCTRL62		SBCTRL(6, 2)
+#define	SBCTRL63		SBCTRL(6, 3)
+#define	SBCTRL64		(SBCTRL_BASE + 0x160)
+
+#define	SBCTRL70		SBCTRL(7, 0)
+#define	SBCTRL71		SBCTRL(7, 1)
+#define	SBCTRL72		SBCTRL(7, 2)
+#define	SBCTRL73		SBCTRL(7, 3)
+#define	SBCTRL74		(SBCTRL_BASE + 0x170)
+
+/* slower but LED works */
+#define SBCTRL0_SAVEPIN_PERI_VALUE	0x55450000
+#define SBCTRL1_SAVEPIN_PERI_VALUE	0x07168d00
+#define SBCTRL2_SAVEPIN_PERI_VALUE	0x34000009
+#define SBCTRL4_SAVEPIN_PERI_VALUE	0x02110110
+
+/* faster but LED does not work */
+#define SBCTRL0_SAVEPIN_MEM_VALUE	0x55450000
+#define SBCTRL1_SAVEPIN_MEM_VALUE	0x06057700
+/* NOR flash needs more wait counts than SRAM */
+#define SBCTRL2_SAVEPIN_MEM_VALUE	0x34000009
+#define SBCTRL4_SAVEPIN_MEM_VALUE	0x02110210
+
+#define SBCTRL0_ADMULTIPLX_PERI_VALUE	0x33120000
+#define SBCTRL1_ADMULTIPLX_PERI_VALUE	0x03005500
+#define SBCTRL2_ADMULTIPLX_PERI_VALUE	0x14000020
+
+#define SBCTRL0_ADMULTIPLX_MEM_VALUE	0x33120000
+#define SBCTRL1_ADMULTIPLX_MEM_VALUE	0x03005500
+#define SBCTRL2_ADMULTIPLX_MEM_VALUE	0x14000010
+
+#define ROM_BOOT_ROMRSV2		0x59801208
+
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+static inline int boot_is_swapped(void)
+{
+	return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
+}
+#endif
+
+#endif	/* ARCH_SBC_REGS_H */
diff --git a/arch/arm/include/asm/arch-uniphier/sc-regs.h b/arch/arm/include/asm/arch-uniphier/sc-regs.h
new file mode 100644
index 0000000000..1197bb52d4
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/sc-regs.h
@@ -0,0 +1,62 @@
+/*
+ * UniPhier SC (System Control) block registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_SC_REGS_H
+#define ARCH_SC_REGS_H
+
+#define SC_BASE_ADDR			0x61840000
+
+#define SC_MPLLOSCCTL                   (SC_BASE_ADDR | 0x1184)
+#define SC_MPLLOSCCTL_MPLLEN		(0x1 << 0)
+#define SC_MPLLOSCCTL_MPLLST		(0x1 << 1)
+
+#define SC_DPLLCTRL			(SC_BASE_ADDR | 0x1200)
+#define SC_DPLLCTRL_SSC_EN		(0x1 << 31)
+#define SC_DPLLCTRL_FOUTMODE_MASK        (0xf << 16)
+#define SC_DPLLCTRL_SSC_RATE		(0x1 << 15)
+
+#define SC_DPLLCTRL2			(SC_BASE_ADDR | 0x1204)
+#define SC_DPLLCTRL2_NRSTDS		(0x1 << 28)
+
+#define SC_DPLLCTRL3			(SC_BASE_ADDR | 0x1208)
+#define SC_DPLLCTRL3_LPFSEL_COEF2	(0x0 << 31)
+#define SC_DPLLCTRL3_LPFSEL_COEF3	(0x1 << 31)
+
+#define SC_UPLLCTRL			(SC_BASE_ADDR | 0x1210)
+
+#define SC_VPLL27ACTRL			(SC_BASE_ADDR | 0x1270)
+#define SC_VPLL27ACTRL2			(SC_BASE_ADDR | 0x1274)
+#define SC_VPLL27ACTRL3			(SC_BASE_ADDR | 0x1278)
+
+#define SC_VPLL27BCTRL			(SC_BASE_ADDR | 0x1290)
+#define SC_VPLL27BCTRL2			(SC_BASE_ADDR | 0x1294)
+#define SC_VPLL27BCTRL3			(SC_BASE_ADDR | 0x1298)
+
+#define SC_RSTCTRL			(SC_BASE_ADDR | 0x2000)
+#define SC_RSTCTRL_NRST_ETHER		(0x1 << 12)
+#define SC_RSTCTRL_NRST_UMC1		(0x1 <<  5)
+#define SC_RSTCTRL_NRST_UMC0		(0x1 <<  4)
+#define SC_RSTCTRL_NRST_NAND		(0x1 <<  2)
+
+#define SC_RSTCTRL2			(SC_BASE_ADDR | 0x2004)
+#define SC_RSTCTRL3			(SC_BASE_ADDR | 0x2008)
+
+#define SC_CLKCTRL			(SC_BASE_ADDR | 0x2104)
+#define SC_CLKCTRL_CLK_ETHER		(0x1 << 12)
+#define SC_CLKCTRL_CLK_MIO		(0x1 << 11)
+#define SC_CLKCTRL_CLK_UMC		(0x1 <<  4)
+#define SC_CLKCTRL_CLK_NAND		(0x1 <<  2)
+#define SC_CLKCTRL_CLK_SBC		(0x1 <<  1)
+#define SC_CLKCTRL_CLK_PERI		(0x1 <<  0)
+
+/* System reset control register */
+#define SC_IRQTIMSET			(SC_BASE_ADDR | 0x3000)
+#define SC_SLFRSTSEL			(SC_BASE_ADDR | 0x3010)
+#define SC_SLFRSTCTL			(SC_BASE_ADDR | 0x3014)
+
+#endif /* ARCH_SC_REGS_H */
diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h b/arch/arm/include/asm/arch-uniphier/sg-regs.h
new file mode 100644
index 0000000000..79d7ec7148
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/sg-regs.h
@@ -0,0 +1,182 @@
+/*
+ * UniPhier SG (SoC Glue) block registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_SG_REGS_H
+#define ARCH_SG_REGS_H
+
+/* Base Address */
+#define SG_CTRL_BASE			0x5f800000
+#define SG_DBG_BASE			0x5f900000
+
+/* Revision */
+#define SG_REVISION			(SG_CTRL_BASE | 0x0000)
+#define SG_REVISION_TYPE_SHIFT		16
+#define SG_REVISION_TYPE_MASK		(0xff << SG_REVISION_TYPE_SHIFT)
+#define SG_REVISION_MODEL_SHIFT		8
+#define SG_REVISION_MODEL_MASK		(0x3 << SG_REVISION_MODEL_SHIFT)
+#define SG_REVISION_REV_SHIFT		0
+#define SG_REVISION_REV_MASK		(0x1f << SG_REVISION_REV_SHIFT)
+
+/* Memory Configuration */
+#define SG_MEMCONF			(SG_CTRL_BASE | 0x0400)
+
+#define SG_MEMCONF_CH0_SIZE_64MB	((0x0 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_SIZE_128MB	((0x0 << 10) | (0x02 << 0))
+#define SG_MEMCONF_CH0_SIZE_256MB	((0x0 << 10) | (0x03 << 0))
+#define SG_MEMCONF_CH0_SIZE_512MB	((0x1 << 10) | (0x00 << 0))
+#define SG_MEMCONF_CH0_SIZE_1024MB	((0x1 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_NUM_1		(0x1 << 8)
+#define SG_MEMCONF_CH0_NUM_2		(0x0 << 8)
+
+#define SG_MEMCONF_CH1_SIZE_64MB	((0x0 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_SIZE_128MB	((0x0 << 11) | (0x02 << 2))
+#define SG_MEMCONF_CH1_SIZE_256MB	((0x0 << 11) | (0x03 << 2))
+#define SG_MEMCONF_CH1_SIZE_512MB	((0x1 << 11) | (0x00 << 2))
+#define SG_MEMCONF_CH1_SIZE_1024MB	((0x1 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_NUM_1		(0x1 << 9)
+#define SG_MEMCONF_CH1_NUM_2		(0x0 << 9)
+
+#define SG_MEMCONF_SPARSEMEM		(0x1 << 4)
+
+/* Pin Control */
+#define SG_PINCTRL_BASE			(SG_CTRL_BASE | 0x1000)
+
+#if defined(CONFIG_MACH_PH1_PRO4)
+# define SG_PINCTRL(n)			(SG_PINCTRL_BASE + (n) * 8)
+#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+# define SG_PINCTRL(n)			(SG_PINCTRL_BASE + (n) * 4)
+#endif
+
+#if defined(CONFIG_MACH_PH1_PRO4)
+#define SG_PINSELBITS			4
+#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+#define SG_PINSELBITS			8
+#endif
+
+#define SG_PINSEL_ADDR(n)		(SG_PINCTRL((n) * (SG_PINSELBITS) / 32))
+#define SG_PINSEL_MASK(n)		(~(((1 << (SG_PINSELBITS)) - 1) << \
+						((n) * (SG_PINSELBITS) % 32)))
+#define SG_PINSEL_MODE(n, mode)		((mode) << ((n) * (SG_PINSELBITS) % 32))
+
+/* Only for PH1-Pro4 */
+#define SG_LOADPINCTRL			(SG_CTRL_BASE | 0x1700)
+
+/* Input Enable */
+#define SG_IECTRL			(SG_CTRL_BASE | 0x1d00)
+
+/* Pin Monitor */
+#define SG_PINMON0			(SG_DBG_BASE | 0x0100)
+
+#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK	(0x3 << 19)
+#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT	(0x0 << 19)
+#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A	(0x2 << 19)
+#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B	(0x3 << 19)
+
+#define SG_PINMON0_CLK_MODE_AXOSEL_MASK		(0x3 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ	(0x0 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ	(0x1 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ	(0x2 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ	(0x3 << 16)
+
+#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT	(0x0 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U	(0x1 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ	(0x2 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A	(0x3 << 16)
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#include <asm/io.h>
+
+static inline void sg_set_pinsel(int n, int value)
+{
+	writel((readl(SG_PINSEL_ADDR(n)) & SG_PINSEL_MASK(n))
+	       | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n));
+}
+
+static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
+{
+	int size_mb = (size >> 20) / num;
+	u32 ret;
+
+	switch (size_mb) {
+	case 64:
+		ret = SG_MEMCONF_CH0_SIZE_64MB;
+		break;
+	case 128:
+		ret = SG_MEMCONF_CH0_SIZE_128MB;
+		break;
+	case 256:
+		ret = SG_MEMCONF_CH0_SIZE_256MB;
+		break;
+	case 512:
+		ret = SG_MEMCONF_CH0_SIZE_512MB;
+		break;
+	case 1024:
+		ret = SG_MEMCONF_CH0_SIZE_1024MB;
+		break;
+	default:
+		BUG();
+		break;
+	}
+
+	switch (num) {
+	case 1:
+		ret |= SG_MEMCONF_CH0_NUM_1;
+		break;
+	case 2:
+		ret |= SG_MEMCONF_CH0_NUM_2;
+		break;
+	default:
+		BUG();
+		break;
+	}
+	return ret;
+}
+
+static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
+{
+	int size_mb = (size >> 20) / num;
+	u32 ret;
+
+	switch (size_mb) {
+	case 64:
+		ret = SG_MEMCONF_CH1_SIZE_64MB;
+		break;
+	case 128:
+		ret = SG_MEMCONF_CH1_SIZE_128MB;
+		break;
+	case 256:
+		ret = SG_MEMCONF_CH1_SIZE_256MB;
+		break;
+	case 512:
+		ret = SG_MEMCONF_CH1_SIZE_512MB;
+		break;
+	case 1024:
+		ret = SG_MEMCONF_CH1_SIZE_1024MB;
+		break;
+	default:
+		BUG();
+		break;
+	}
+
+	switch (num) {
+	case 1:
+		ret |= SG_MEMCONF_CH1_NUM_1;
+		break;
+	case 2:
+		ret |= SG_MEMCONF_CH1_NUM_2;
+		break;
+	default:
+		BUG();
+		break;
+	}
+	return ret;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* ARCH_SG_REGS_H */
diff --git a/arch/arm/include/asm/arch-uniphier/ssc-regs.h b/arch/arm/include/asm/arch-uniphier/ssc-regs.h
new file mode 100644
index 0000000000..77b3470c6d
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/ssc-regs.h
@@ -0,0 +1,67 @@
+/*
+ * UniPhier System Cache (L2 Cache) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_SSC_REGS_H
+#define ARCH_SSC_REGS_H
+
+#define SSCC			0x500c0000
+#define SSCC_BST		(0x1 << 20)
+#define SSCC_ACT		(0x1 << 19)
+#define SSCC_WTG		(0x1 << 18)
+#define SSCC_PRD		(0x1 << 17)
+#define SSCC_WBWA		(0x1 << 16)
+#define SSCC_EX			(0x1 << 13)
+#define SSCC_ON			(0x1 <<  0)
+
+#define SSCLPDAWCR		0x500c0030
+
+#define SSCOPE			0x506c0244
+#define SSCOPE_CM_SYNC		0x00000008
+
+#define SSCOQM			0x506c0248
+#define SSCOQM_TID_MASK		(0x3 << 21)
+#define SSCOQM_TID_BY_WAY	(0x2 << 21)
+#define SSCOQM_TID_BY_INST_WAY	(0x1 << 21)
+#define SSCOQM_TID_BY_DATA_WAY	(0x0 << 21)
+#define SSCOQM_S_MASK		(0x3 << 17)
+#define SSCOQM_S_WAY		(0x2 << 17)
+#define SSCOQM_S_ALL		(0x1 << 17)
+#define SSCOQM_S_ADDRESS	(0x0 << 17)
+#define SSCOQM_CE		(0x1 << 15)
+#define SSCOQM_CW		(0x1 << 14)
+#define SSCOQM_CM_MASK		(0x7)
+#define SSCOQM_CM_DIRT_TOUCH	(0x7)
+#define SSCOQM_CM_ZERO_TOUCH	(0x6)
+#define SSCOQM_CM_NORM_TOUCH	(0x5)
+#define SSCOQM_CM_PREF_FETCH	(0x4)
+#define SSCOQM_CM_SSC_FETCH	(0x3)
+#define SSCOQM_CM_WB_INV	(0x2)
+#define SSCOQM_CM_WB		(0x1)
+#define SSCOQM_CM_INV		(0x0)
+
+#define SSCOQAD			0x506c024c
+#define SSCOQSZ			0x506c0250
+#define SSCOQWN			0x506c0258
+
+#define SSCOPPQSEF		0x506c025c
+#define SSCOPPQSEF_FE		(0x1 << 1)
+#define SSCOPPQSEF_OE		(0x1 << 0)
+
+#define SSCOLPQS		0x506c0260
+#define SSCOLPQS_EF		(0x1 << 2)
+#define SSCOLPQS_EST		(0x1 << 1)
+#define SSCOLPQS_QST		(0x1 << 0)
+
+#define SSCOQCE0		0x506c0270
+
+#define SSC_LINE_SIZE		128
+#define SSC_NUM_ENTRIES		256
+#define SSC_WAY_SIZE		((SSC_LINE_SIZE) * (SSC_NUM_ENTRIES))
+#define SSC_RANGE_OP_MAX_SIZE	(0x00400000 - (SSC_LINE_SIZE))
+
+#endif  /* ARCH_SSC_REGS_H */
diff --git a/arch/arm/include/asm/arch-uniphier/umc-regs.h b/arch/arm/include/asm/arch-uniphier/umc-regs.h
new file mode 100644
index 0000000000..6159281fd3
--- /dev/null
+++ b/arch/arm/include/asm/arch-uniphier/umc-regs.h
@@ -0,0 +1,119 @@
+/*
+ * UniPhier UMC (Universal Memory Controller) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_UMC_REGS_H
+#define ARCH_UMC_REGS_H
+
+#define UMC_BASE		0x5b800000
+
+/* SSIF registers */
+#define UMC_SSIF_BASE		UMC_BASE
+
+#define UMC_CPURST		0x00000700
+#define UMC_IDSRST		0x0000070C
+#define UMC_IXMRST		0x00000714
+#define UMC_HDMRST		0x00000718
+#define UMC_MDMRST		0x0000071C
+#define UMC_HDDRST		0x00000720
+#define UMC_MDDRST		0x00000724
+#define UMC_SIORST		0x00000728
+#define UMC_GIORST		0x0000072C
+#define UMC_HD2RST		0x00000734
+#define UMC_VIORST		0x0000073C
+#define UMC_FRCRST		0x00000748 /* LD4/sLD8 */
+#define UMC_DVCRST		0x00000748 /* Pro4 */
+#define UMC_RGLRST		0x00000750
+#define UMC_VPERST		0x00000758
+#define UMC_AIORST		0x00000764
+#define UMC_DMDRST		0x00000770
+
+#define UMC_HDMCHSEL		0x00000898
+#define UMC_MDMCHSEL		0x0000089C
+#define UMC_DVCCHSEL		0x000008C8
+#define UMC_DMDCHSEL		0x000008F0
+
+#define UMC_CLKEN_SSIF_FETCH	0x0000C060
+#define UMC_CLKEN_SSIF_COMQUE0	0x0000C064
+#define UMC_CLKEN_SSIF_COMWC0	0x0000C068
+#define UMC_CLKEN_SSIF_COMRC0	0x0000C06C
+#define UMC_CLKEN_SSIF_COMQUE1	0x0000C070
+#define UMC_CLKEN_SSIF_COMWC1	0x0000C074
+#define UMC_CLKEN_SSIF_COMRC1	0x0000C078
+#define UMC_CLKEN_SSIF_WC	0x0000C07C
+#define UMC_CLKEN_SSIF_RC	0x0000C080
+#define UMC_CLKEN_SSIF_DST	0x0000C084
+
+/* CA registers */
+#define UMC_CA_BASE(ch)		(UMC_BASE + 0x00001000 + 0x00001000 * (ch))
+
+/* DRAM controller registers */
+#define UMC_DRAMCONT_BASE(ch)	(UMC_BASE + 0x00400000 + 0x00200000 * (ch))
+
+#define UMC_CMDCTLA		0x00000000
+#define UMC_CMDCTLB		0x00000004
+#define UMC_INITCTLA		0x00000008
+#define UMC_INITCTLB		0x0000000C
+#define UMC_INITCTLC		0x00000010
+#define UMC_INITSET		0x00000014
+#define UMC_INITSTAT		0x00000018
+#define UMC_DRMMR0		0x0000001C
+#define UMC_DRMMR1		0x00000020
+#define UMC_DRMMR2		0x00000024
+#define UMC_DRMMR3		0x00000028
+#define UMC_SPCCTLA		0x00000030
+#define UMC_SPCCTLB		0x00000034
+#define UMC_SPCSETA		0x00000038
+#define UMC_SPCSETB		0x0000003C
+#define UMC_SPCSETC		0x00000040
+#define UMC_SPCSETD		0x00000044
+#define UMC_SPCSTATA		0x00000050
+#define UMC_SPCSTATB		0x00000054
+#define UMC_SPCSTATC		0x00000058
+#define UMC_ACSSETA		0x00000060
+#define UMC_FLOWCTLA		0x00000400
+#define UMC_FLOWCTLB		0x00000404
+#define UMC_FLOWCTLC		0x00000408
+#define UMC_FLOWCTLG		0x00000508
+#define UMC_RDATACTL_D0		0x00000600
+#define UMC_WDATACTL_D0		0x00000604
+#define UMC_RDATACTL_D1		0x00000608
+#define UMC_WDATACTL_D1		0x0000060C
+#define UMC_DATASET		0x00000610
+#define UMC_DCCGCTL		0x00000720
+#define UMC_DICGCTLA		0x00000724
+#define UMC_DICGCTLB		0x00000728
+#define UMC_DIOCTLA		0x00000C00
+#define UMC_DFICUPDCTLA		0x00000C20
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+static inline void umc_polling(u32 address, u32 expval, u32 mask)
+{
+	u32 nmask = ~mask;
+	u32 data;
+	do {
+		data = readl(address) & nmask;
+	} while (data != expval);
+}
+
+static inline void umc_dram_init_start(void __iomem *dramcont)
+{
+	writel(0x00000002, dramcont + UMC_INITSET);
+}
+
+static inline void umc_dram_init_poll(void __iomem *dramcont)
+{
+	while ((readl(dramcont + UMC_INITSTAT) & 0x00000002))
+		;
+}
+
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/imx-common/mxc_i2c.h b/arch/arm/include/asm/imx-common/mxc_i2c.h
index 47a9edc81b..182c2f397f 100644
--- a/arch/arm/include/asm/imx-common/mxc_i2c.h
+++ b/arch/arm/include/asm/imx-common/mxc_i2c.h
@@ -19,6 +19,39 @@ struct i2c_pads_info {
 	struct i2c_pin_ctrl sda;
 };
 
+#if defined(CONFIG_MX6QDL)
+#define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \
+	struct i2c_pads_info mx6q_##name = {		\
+		.scl = {				\
+			.i2c_mode = MX6Q_##scl_i2c,	\
+			.gpio_mode = MX6Q_##scl_gpio,	\
+			.gp = scl_gp,			\
+		},					\
+		.sda = {				\
+			.i2c_mode = MX6Q_##sda_i2c,	\
+			.gpio_mode = MX6Q_##sda_gpio,	\
+			.gp = sda_gp,			\
+		}					\
+	};						\
+	struct i2c_pads_info mx6s_##name = {		\
+		.scl = {				\
+			.i2c_mode = MX6DL_##scl_i2c,	\
+			.gpio_mode = MX6DL_##scl_gpio,	\
+			.gp = scl_gp,			\
+		},					\
+		.sda = {				\
+			.i2c_mode = MX6DL_##sda_i2c,	\
+			.gpio_mode = MX6DL_##sda_gpio,	\
+			.gp = sda_gp,			\
+		}					\
+	};
+
+
+#define I2C_PADS_INFO(name)	\
+	(is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) ? \
+					&mx6q_##name : &mx6s_##name
+#endif
+
 void setup_i2c(unsigned i2c_index, int speed, int slave_addr,
 		struct i2c_pads_info *p);
 void bus_i2c_init(void *base, int speed, int slave_addr,
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index f77e4b880e..541b443254 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -105,6 +105,99 @@ lr	.req	x30
 	cbz	\xreg1, \master_label
 .endm
 
+.macro armv8_switch_to_el2_m, xreg1
+	/* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
+	mov	\xreg1, #0x5b1
+	msr	scr_el3, \xreg1
+	msr	cptr_el3, xzr		/* Disable coprocessor traps to EL3 */
+	mov	\xreg1, #0x33ff
+	msr	cptr_el2, \xreg1	/* Disable coprocessor traps to EL2 */
+
+	/* Initialize SCTLR_EL2
+	 *
+	 * setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1
+	 * and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) +
+	 * EE,WXN,I,SA,C,A,M to 0
+	 */
+	mov	\xreg1, #0x0830
+	movk	\xreg1, #0x30C5, lsl #16
+	msr	sctlr_el2, \xreg1
+
+	/* Return to the EL2_SP2 mode from EL3 */
+	mov	\xreg1, sp
+	msr	sp_el2, \xreg1		/* Migrate SP */
+	mrs	\xreg1, vbar_el3
+	msr	vbar_el2, \xreg1	/* Migrate VBAR */
+	mov	\xreg1, #0x3c9
+	msr	spsr_el3, \xreg1	/* EL2_SP2 | D | A | I | F */
+	msr	elr_el3, lr
+	eret
+.endm
+
+.macro armv8_switch_to_el1_m, xreg1, xreg2
+	/* Initialize Generic Timers */
+	mrs	\xreg1, cnthctl_el2
+	orr	\xreg1, \xreg1, #0x3	/* Enable EL1 access to timers */
+	msr	cnthctl_el2, \xreg1
+	msr	cntvoff_el2, xzr
+
+	/* Initilize MPID/MPIDR registers */
+	mrs	\xreg1, midr_el1
+	mrs	\xreg2, mpidr_el1
+	msr	vpidr_el2, \xreg1
+	msr	vmpidr_el2, \xreg2
+
+	/* Disable coprocessor traps */
+	mov	\xreg1, #0x33ff
+	msr	cptr_el2, \xreg1	/* Disable coprocessor traps to EL2 */
+	msr	hstr_el2, xzr		/* Disable coprocessor traps to EL2 */
+	mov	\xreg1, #3 << 20
+	msr	cpacr_el1, \xreg1	/* Enable FP/SIMD at EL1 */
+
+	/* Initialize HCR_EL2 */
+	mov	\xreg1, #(1 << 31)		/* 64bit EL1 */
+	orr	\xreg1, \xreg1, #(1 << 29)	/* Disable HVC */
+	msr	hcr_el2, \xreg1
+
+	/* SCTLR_EL1 initialization
+	 *
+	 * setting RES1 bits (29,28,23,22,20,11) to 1
+	 * and RES0 bits (31,30,27,21,17,13,10,6) +
+	 * UCI,EE,EOE,WXN,nTWE,nTWI,UCT,DZE,I,UMA,SED,ITD,
+	 * CP15BEN,SA0,SA,C,A,M to 0
+	 */
+	mov	\xreg1, #0x0800
+	movk	\xreg1, #0x30d0, lsl #16
+	msr	sctlr_el1, \xreg1
+
+	/* Return to the EL1_SP1 mode from EL2 */
+	mov	\xreg1, sp
+	msr	sp_el1, \xreg1		/* Migrate SP */
+	mrs	\xreg1, vbar_el2
+	msr	vbar_el1, \xreg1	/* Migrate VBAR */
+	mov	\xreg1, #0x3c5
+	msr	spsr_el2, \xreg1	/* EL1_SP1 | D | A | I | F */
+	msr	elr_el2, lr
+	eret
+.endm
+
+#if defined(CONFIG_GICV3)
+.macro gic_wait_for_interrupt_m xreg1
+0 :	wfi
+	mrs     \xreg1, ICC_IAR1_EL1
+	msr     ICC_EOIR1_EL1, \xreg1
+	cbnz    \xreg1, 0b
+.endm
+#elif defined(CONFIG_GICV2)
+.macro gic_wait_for_interrupt_m xreg1, wreg2
+0 :	wfi
+	ldr     \wreg2, [\xreg1, GICC_AIAR]
+	str     \wreg2, [\xreg1, GICC_AEOIR]
+	and	\wreg2, \wreg2, #3ff
+	cbnz    \wreg2, 0b
+.endm
+#endif
+
 #endif /* CONFIG_ARM64 */
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S
index d56396ea22..a3e18f7713 100644
--- a/arch/arm/lib/gic_64.S
+++ b/arch/arm/lib/gic_64.S
@@ -10,8 +10,8 @@
 #include <asm-offsets.h>
 #include <config.h>
 #include <linux/linkage.h>
-#include <asm/macro.h>
 #include <asm/gic.h>
+#include <asm/macro.h>
 
 
 /*************************************************************************
@@ -181,14 +181,10 @@ ENDPROC(gic_kick_secondary_cpus)
  *
  *************************************************************************/
 ENTRY(gic_wait_for_interrupt)
-0:	wfi
 #if defined(CONFIG_GICV3)
-	mrs	x9, ICC_IAR1_EL1
-	msr	ICC_EOIR1_EL1, x9
+	gic_wait_for_interrupt_m x9
 #elif defined(CONFIG_GICV2)
-	ldr	w9, [x0, GICC_AIAR]
-	str	w9, [x0, GICC_AEOIR]
+	gic_wait_for_interrupt_m x0, w9
 #endif
-	cbnz	w9, 0b
 	ret
 ENDPROC(gic_wait_for_interrupt)
diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
index 75ab546923..dfcc596815 100644
--- a/arch/arm/lib/spl.c
+++ b/arch/arm/lib/spl.c
@@ -28,6 +28,9 @@ void __weak board_init_f(ulong dummy)
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
+	/* Set global data pointer. */
+	gd = &gdata;
+
 	board_init_r(NULL, 0);
 }
 
diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk
index 6329b6c74f..fec02f2b82 100644
--- a/arch/powerpc/config.mk
+++ b/arch/powerpc/config.mk
@@ -11,6 +11,7 @@ endif
 
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
 LDFLAGS_FINAL += --gc-sections
+LDFLAGS_FINAL += --bss-plt
 PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections -fdata-sections \
 								-meabi
 PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 6274f929dd..3d6ec843df 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -441,7 +441,7 @@ phys_size_t initdram(int board_type)
 
 /* Board-specific functions defined in each board's ddr.c */
 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
-	unsigned int ctrl_num);
+	unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
 		       phys_addr_t *rpn);
 unsigned int
@@ -459,7 +459,7 @@ static void dump_spd_ddr_reg(void)
 		spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
 
 	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
-		fsl_ddr_get_spd(spd[i], i);
+		fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
 
 	puts("SPD data of all dimms (zero vaule is omitted)...\n");
 	puts("Byte (hex)  ");
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index d1fc76a13e..8edf5bb20e 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -186,11 +186,6 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 #endif
 
 	cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
-	/* Is serdes enabled at all? */
-	if (!cfg) {
-		printf("SERDES%d is not enabled\n", sd + 1);
-		return 0;
-	}
 
 /* Erratum A-007186
  * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
diff --git a/board/ip860/u-boot.lds b/arch/powerpc/cpu/mpc8xx/u-boot.lds
similarity index 100%
rename from board/ip860/u-boot.lds
rename to arch/powerpc/cpu/mpc8xx/u-boot.lds
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 9273745299..4cec5e118f 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2012 Freescale Semiconductor, Inc.
+ * Copyright 2009-2014 Freescale Semiconductor, Inc.
  *
  * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
  * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
@@ -123,14 +123,14 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 {
 	const char *modes[] = { "host", "peripheral", "otg" };
 	const char *phys[] = { "ulpi", "utmi" };
-	const char *dr_mode_type = NULL;
-	const char *dr_phy_type = NULL;
 	int usb_mode_off = -1;
 	int usb_phy_off = -1;
 	char str[5];
 	int i, j;
 
 	for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
+		const char *dr_mode_type = NULL;
+		const char *dr_phy_type = NULL;
 		int mode_idx = -1, phy_idx = -1;
 		snprintf(str, 5, "%s%d", "usb", i);
 		if (hwconfig(str)) {
@@ -150,18 +150,16 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 				}
 			}
 
-			if (mode_idx < 0 || phy_idx < 0) {
-				puts("ERROR: wrong usb mode/phy defined!!\n");
-				return;
-			}
-
-			dr_mode_type = modes[mode_idx];
-			dr_phy_type = phys[phy_idx];
-
 			if (mode_idx < 0 && phy_idx < 0) {
 				printf("WARNING: invalid phy or mode\n");
 				return;
 			}
+
+			if (mode_idx > -1)
+				dr_mode_type = modes[mode_idx];
+
+			if (phy_idx > -1)
+				dr_phy_type = phys[phy_idx];
 		}
 
 		usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c
index 59b3fe977d..b57b2c30fe 100644
--- a/arch/x86/lib/physmem.c
+++ b/arch/x86/lib/physmem.c
@@ -189,7 +189,7 @@ phys_addr_t arch_phys_memset(phys_addr_t start, int c, phys_size_t size)
 
 	/* Handle memory below 4GB. */
 	if (start <= max_addr) {
-		phys_size_t low_size = MIN(max_addr + 1 - start, size);
+		phys_size_t low_size = min(max_addr + 1 - start, size);
 		void *start_ptr = (void *)(uintptr_t)start;
 
 		assert(((phys_addr_t)(uintptr_t)start) == start);
@@ -208,7 +208,7 @@ phys_addr_t arch_phys_memset(phys_addr_t start, int c, phys_size_t size)
 		/* Handle the first partial page. */
 		if (offset) {
 			phys_addr_t end =
-				MIN(map_addr + LARGE_PAGE_SIZE, start + size);
+				min(map_addr + LARGE_PAGE_SIZE, start + size);
 			phys_size_t cur_size = end - start;
 			x86_phys_memset_page(map_addr, offset, c, cur_size);
 			size -= cur_size;
diff --git a/board/LaCie/net2big_v2/MAINTAINERS b/board/LaCie/net2big_v2/MAINTAINERS
index 1afaa5ce5c..205c75e4cb 100644
--- a/board/LaCie/net2big_v2/MAINTAINERS
+++ b/board/LaCie/net2big_v2/MAINTAINERS
@@ -1,5 +1,5 @@
 NET2BIG_V2 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/LaCie/net2big_v2/
 F:	include/configs/lacie_kw.h
diff --git a/board/LaCie/netspace_v2/MAINTAINERS b/board/LaCie/netspace_v2/MAINTAINERS
index ad3dfa1565..55fd50d4eb 100644
--- a/board/LaCie/netspace_v2/MAINTAINERS
+++ b/board/LaCie/netspace_v2/MAINTAINERS
@@ -8,7 +8,7 @@ F:	configs/netspace_max_v2_defconfig
 F:	configs/netspace_v2_defconfig
 
 NETSPACE_LITE_V2 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	configs/netspace_lite_v2_defconfig
 F:	configs/netspace_mini_v2_defconfig
diff --git a/board/LaCie/wireless_space/MAINTAINERS b/board/LaCie/wireless_space/MAINTAINERS
index 8b36bff32b..8a27b9a234 100644
--- a/board/LaCie/wireless_space/MAINTAINERS
+++ b/board/LaCie/wireless_space/MAINTAINERS
@@ -1,5 +1,5 @@
 WIRELESS_SPACE BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/LaCie/wireless_space/
 F:	include/configs/wireless_space.h
diff --git a/board/Marvell/db64360/MAINTAINERS b/board/Marvell/db64360/MAINTAINERS
index 7383207f75..af3eb24a2b 100644
--- a/board/Marvell/db64360/MAINTAINERS
+++ b/board/Marvell/db64360/MAINTAINERS
@@ -1,5 +1,5 @@
 DB64360 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/Marvell/db64360/
 F:	include/configs/DB64360.h
diff --git a/board/Marvell/db64460/MAINTAINERS b/board/Marvell/db64460/MAINTAINERS
index 751aac2be3..a30c51c54b 100644
--- a/board/Marvell/db64460/MAINTAINERS
+++ b/board/Marvell/db64460/MAINTAINERS
@@ -1,5 +1,5 @@
 DB64460 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/Marvell/db64460/
 F:	include/configs/DB64460.h
diff --git a/board/Marvell/openrd/MAINTAINERS b/board/Marvell/openrd/MAINTAINERS
index 7a52a8eeee..7a189ab6d5 100644
--- a/board/Marvell/openrd/MAINTAINERS
+++ b/board/Marvell/openrd/MAINTAINERS
@@ -6,7 +6,7 @@ F:	include/configs/openrd.h
 F:	configs/openrd_base_defconfig
 
 OPENRD_CLIENT BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	configs/openrd_client_defconfig
 F:	configs/openrd_ultimate_defconfig
diff --git a/board/a3000/MAINTAINERS b/board/a3000/MAINTAINERS
index 2d8560f628..303e5fdacb 100644
--- a/board/a3000/MAINTAINERS
+++ b/board/a3000/MAINTAINERS
@@ -1,5 +1,5 @@
 A3000 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/a3000/
 F:	include/configs/A3000.h
diff --git a/board/amcc/bluestone/MAINTAINERS b/board/amcc/bluestone/MAINTAINERS
index 4a329e9738..9eb9bbd01b 100644
--- a/board/amcc/bluestone/MAINTAINERS
+++ b/board/amcc/bluestone/MAINTAINERS
@@ -1,5 +1,5 @@
 BLUESTONE BOARD
-M:	Tirumala Marri <tmarri@apm.com>
+#M:	Tirumala Marri <tmarri@apm.com>
 S:	Orphan (since 2014-03)
 F:	board/amcc/bluestone/
 F:	include/configs/bluestone.h
diff --git a/board/amcc/bubinga/MAINTAINERS b/board/amcc/bubinga/MAINTAINERS
index 9d5ace2ae5..3299cc34e3 100644
--- a/board/amcc/bubinga/MAINTAINERS
+++ b/board/amcc/bubinga/MAINTAINERS
@@ -1,5 +1,5 @@
 BUBINGA BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/amcc/bubinga/
 F:	include/configs/bubinga.h
diff --git a/board/amcc/yucca/MAINTAINERS b/board/amcc/yucca/MAINTAINERS
index 0663003984..1cbdb0e70d 100644
--- a/board/amcc/yucca/MAINTAINERS
+++ b/board/amcc/yucca/MAINTAINERS
@@ -1,5 +1,5 @@
 YUCCA BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/amcc/yucca/
 F:	include/configs/yucca.h
diff --git a/board/armltd/versatile/MAINTAINERS b/board/armltd/versatile/MAINTAINERS
index f390e53307..a56dd99bb3 100644
--- a/board/armltd/versatile/MAINTAINERS
+++ b/board/armltd/versatile/MAINTAINERS
@@ -1,5 +1,5 @@
 VERSATILE BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/armltd/versatile/
 F:	include/configs/versatile.h
diff --git a/board/armltd/vexpress/MAINTAINERS b/board/armltd/vexpress/MAINTAINERS
index e730f4f170..a6943d7426 100644
--- a/board/armltd/vexpress/MAINTAINERS
+++ b/board/armltd/vexpress/MAINTAINERS
@@ -1,12 +1,12 @@
 VEXPRESS BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/armltd/vexpress/
 F:	include/configs/vexpress_ca15_tc2.h
 F:	configs/vexpress_ca15_tc2_defconfig
 
 VEXPRESS_CA5X2 BOARD
-M:	Matt Waddel <matt.waddel@linaro.org>
+#M:	Matt Waddel <matt.waddel@linaro.org>
 S:	Orphan (since 2014-08)
 F:	include/configs/vexpress_ca5x2.h
 F:	configs/vexpress_ca5x2_defconfig
diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig
index 94944095c3..7ebea6317f 100644
--- a/board/armltd/vexpress64/Kconfig
+++ b/board/armltd/vexpress64/Kconfig
@@ -1,24 +1,5 @@
 if TARGET_VEXPRESS_AEMV8A
 
-config SYS_CPU
-	default "armv8"
-
-config SYS_BOARD
-	default "vexpress64"
-
-config SYS_VENDOR
-	default "armltd"
-
-config SYS_CONFIG_NAME
-	default "vexpress_aemv8a"
-
-endif
-
-if TARGET_VEXPRESS_AEMV8A_SEMI
-
-config SYS_CPU
-	default "armv8"
-
 config SYS_BOARD
 	default "vexpress64"
 
diff --git a/board/atmel/atngw100/MAINTAINERS b/board/atmel/atngw100/MAINTAINERS
index dd698eaac8..1c319f66b4 100644
--- a/board/atmel/atngw100/MAINTAINERS
+++ b/board/atmel/atngw100/MAINTAINERS
@@ -1,5 +1,5 @@
 ATNGW100 BOARD
-M:	Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+#M:	Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
 S:	Orphan (since 2014-06)
 F:	board/atmel/atngw100/
 F:	include/configs/atngw100.h
diff --git a/board/atmel/atstk1000/MAINTAINERS b/board/atmel/atstk1000/MAINTAINERS
index 76365b0c10..378e1b3dbc 100644
--- a/board/atmel/atstk1000/MAINTAINERS
+++ b/board/atmel/atstk1000/MAINTAINERS
@@ -1,5 +1,5 @@
 ATSTK1000 BOARD
-M:	Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+#M:	Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
 S:	Orphan (since 2014-06)
 F:	board/atmel/atstk1000/
 F:	include/configs/atstk1002.h
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index c835c12d02..f53754bc87 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -67,6 +67,61 @@ void sama5d3xek_nand_hw_init(void)
 }
 #endif
 
+#ifndef CONFIG_SYS_NO_FLASH
+static void sama5d3xek_nor_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	at91_periph_clk_enable(ATMEL_ID_SMC);
+
+	/* Configure SMC CS0 for NOR flash */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[0].setup);
+	writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) |
+	       AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11),
+	       &smc->cs[0].pulse);
+	writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14),
+	       &smc->cs[0].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0)  |
+	       AT91_SMC_TIMINGS_TAR(0)  | AT91_SMC_TIMINGS_TRR(0)   |
+	       AT91_SMC_TIMINGS_TWB(0)  | AT91_SMC_TIMINGS_RBNSEL(0)|
+	       AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_16 |
+	       AT91_SMC_MODE_TDF_CYCLE(1),
+	       &smc->cs[0].mode);
+
+	/* Address pin (A1 ~ A23) configuration */
+	at91_set_a_periph(AT91_PIO_PORTE, 1, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 2, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 3, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 4, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 5, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 6, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 7, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 8, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 9, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 10, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 11, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 12, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 13, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 14, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 15, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 16, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 17, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 18, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 19, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 20, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 21, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 22, 0);
+	at91_set_a_periph(AT91_PIO_PORTE, 23, 0);
+	/* CS0 pin configuration */
+	at91_set_a_periph(AT91_PIO_PORTE, 26, 0);
+}
+#endif
+
 #ifdef CONFIG_CMD_USB
 static void sama5d3xek_usb_hw_init(void)
 {
@@ -181,6 +236,9 @@ int board_init(void)
 #ifdef CONFIG_NAND_ATMEL
 	sama5d3xek_nand_hw_init();
 #endif
+#ifndef CONFIG_SYS_NO_FLASH
+	sama5d3xek_nor_hw_init();
+#endif
 #ifdef CONFIG_CMD_USB
 	sama5d3xek_usb_hw_init();
 #endif
diff --git a/board/bc3450/MAINTAINERS b/board/bc3450/MAINTAINERS
index e2a8363d8f..81a7076093 100644
--- a/board/bc3450/MAINTAINERS
+++ b/board/bc3450/MAINTAINERS
@@ -1,5 +1,5 @@
 BC3450 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/bc3450/
 F:	include/configs/BC3450.h
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 60a09f4bb3..7edfe19367 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -328,6 +328,11 @@ int board_mmc_init(bd_t *bis)
 #endif
 
 #ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
+}
+
 iomux_v3_cfg_t const ecspi1_pads[] = {
 	/* SS1 */
 	MX6_PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(NO_PAD_CTRL),
diff --git a/board/calao/sbc35_a9g20/MAINTAINERS b/board/calao/sbc35_a9g20/MAINTAINERS
index d275230095..0ac8225d06 100644
--- a/board/calao/sbc35_a9g20/MAINTAINERS
+++ b/board/calao/sbc35_a9g20/MAINTAINERS
@@ -1,5 +1,5 @@
 SBC35_A9G20 BOARD
-M:	Albin Tonnerre <albin.tonnerre@free-electrons.com>
+#M:	Albin Tonnerre <albin.tonnerre@free-electrons.com>
 S:	Orphan (since 2014-06)
 F:	board/calao/sbc35_a9g20/
 F:	include/configs/sbc35_a9g20.h
diff --git a/board/calao/tny_a9260/MAINTAINERS b/board/calao/tny_a9260/MAINTAINERS
index 5a71b8effc..1f24e3948b 100644
--- a/board/calao/tny_a9260/MAINTAINERS
+++ b/board/calao/tny_a9260/MAINTAINERS
@@ -1,5 +1,5 @@
 TNY_A9260 BOARD
-M:	Albin Tonnerre <albin.tonnerre@free-electrons.com>
+#M:	Albin Tonnerre <albin.tonnerre@free-electrons.com>
 S:	Orphan (since 2014-06)
 F:	board/calao/tny_a9260/
 F:	include/configs/tny_a9260.h
diff --git a/board/canmb/MAINTAINERS b/board/canmb/MAINTAINERS
index aa4eb301c0..71750ead47 100644
--- a/board/canmb/MAINTAINERS
+++ b/board/canmb/MAINTAINERS
@@ -1,5 +1,5 @@
 CANMB BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/canmb/
 F:	include/configs/canmb.h
diff --git a/board/cm-bf527/MAINTAINERS b/board/cm-bf527/MAINTAINERS
index 789f5c4769..fefcfcfb7d 100644
--- a/board/cm-bf527/MAINTAINERS
+++ b/board/cm-bf527/MAINTAINERS
@@ -1,5 +1,5 @@
 CM-BF527 BOARD
-M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 S:	Orphan (since 2014-03)
 F:	board/cm-bf527/
 F:	include/configs/cm-bf527.h
diff --git a/board/cm-bf533/MAINTAINERS b/board/cm-bf533/MAINTAINERS
index f643043d56..0bf51fb1ea 100644
--- a/board/cm-bf533/MAINTAINERS
+++ b/board/cm-bf533/MAINTAINERS
@@ -1,5 +1,5 @@
 CM-BF533 BOARD
-M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 S:	Orphan (since 2014-03)
 F:	board/cm-bf533/
 F:	include/configs/cm-bf533.h
diff --git a/board/cm-bf537e/MAINTAINERS b/board/cm-bf537e/MAINTAINERS
index 44735fafdb..63d242893e 100644
--- a/board/cm-bf537e/MAINTAINERS
+++ b/board/cm-bf537e/MAINTAINERS
@@ -1,5 +1,5 @@
 CM-BF537E BOARD
-M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 S:	Orphan (since 2014-03)
 F:	board/cm-bf537e/
 F:	include/configs/cm-bf537e.h
diff --git a/board/cm-bf537u/MAINTAINERS b/board/cm-bf537u/MAINTAINERS
index da925f87d6..a89cfcae74 100644
--- a/board/cm-bf537u/MAINTAINERS
+++ b/board/cm-bf537u/MAINTAINERS
@@ -1,5 +1,5 @@
 CM-BF537U BOARD
-M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 S:	Orphan (since 2014-03)
 F:	board/cm-bf537u/
 F:	include/configs/cm-bf537u.h
diff --git a/board/cm-bf548/MAINTAINERS b/board/cm-bf548/MAINTAINERS
index 4cd83df8bc..b7f5779cef 100644
--- a/board/cm-bf548/MAINTAINERS
+++ b/board/cm-bf548/MAINTAINERS
@@ -1,5 +1,5 @@
 CM-BF548 BOARD
-M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 S:	Orphan (since 2014-03)
 F:	board/cm-bf548/
 F:	include/configs/cm-bf548.h
diff --git a/board/cm-bf561/MAINTAINERS b/board/cm-bf561/MAINTAINERS
index a4606fff62..9c86c8d39a 100644
--- a/board/cm-bf561/MAINTAINERS
+++ b/board/cm-bf561/MAINTAINERS
@@ -1,5 +1,5 @@
 CM-BF561 BOARD
-M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 S:	Orphan (since 2014-03)
 F:	board/cm-bf561/
 F:	include/configs/cm-bf561.h
diff --git a/board/cm41xx/MAINTAINERS b/board/cm41xx/MAINTAINERS
index f308b0fb29..f10eeb58f3 100644
--- a/board/cm41xx/MAINTAINERS
+++ b/board/cm41xx/MAINTAINERS
@@ -1,5 +1,5 @@
 CM41XX BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/cm41xx/
 F:	include/configs/cm41xx.h
diff --git a/board/cm5200/MAINTAINERS b/board/cm5200/MAINTAINERS
index 9fc5365148..1e1df3f6dc 100644
--- a/board/cm5200/MAINTAINERS
+++ b/board/cm5200/MAINTAINERS
@@ -1,5 +1,5 @@
 CM5200 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/cm5200/
 F:	include/configs/cm5200.h
diff --git a/board/cmi/MAINTAINERS b/board/cmi/MAINTAINERS
index ab33d5d02d..60701bfd99 100644
--- a/board/cmi/MAINTAINERS
+++ b/board/cmi/MAINTAINERS
@@ -1,5 +1,5 @@
 CMI BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/cmi/
 F:	include/configs/cmi_mpc5xx.h
diff --git a/board/cobra5272/MAINTAINERS b/board/cobra5272/MAINTAINERS
index 00942fc2fc..a064da2f15 100644
--- a/board/cobra5272/MAINTAINERS
+++ b/board/cobra5272/MAINTAINERS
@@ -1,5 +1,5 @@
 COBRA5272 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/cobra5272/
 F:	include/configs/cobra5272.h
diff --git a/board/compulab/cm_fx6/Kconfig b/board/compulab/cm_fx6/Kconfig
new file mode 100644
index 0000000000..42a84380f2
--- /dev/null
+++ b/board/compulab/cm_fx6/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_CM_FX6
+
+config SYS_CPU
+	string
+	default "armv7"
+
+config SYS_BOARD
+	string
+	default "cm_fx6"
+
+config SYS_VENDOR
+	string
+	default "compulab"
+
+config SYS_SOC
+	string
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	string
+	default "cm_fx6"
+
+endif
diff --git a/board/compulab/cm_fx6/MAINTAINERS b/board/compulab/cm_fx6/MAINTAINERS
new file mode 100644
index 0000000000..5b2623a664
--- /dev/null
+++ b/board/compulab/cm_fx6/MAINTAINERS
@@ -0,0 +1,6 @@
+CM_FX6 BOARD
+M:	Nikita Kiryanov <nikita@compulab.co.il>
+S:	Maintained
+F:	board/compulab/cm_fx6/
+F:	include/configs/cm_fx6.h
+F:	configs/cm_fx6_defconfig
diff --git a/board/compulab/cm_fx6/Makefile b/board/compulab/cm_fx6/Makefile
new file mode 100644
index 0000000000..3e5c9034df
--- /dev/null
+++ b/board/compulab/cm_fx6/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Authors: Nikita Kiryanov <nikita@compulab.co.il>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+ifdef CONFIG_SPL_BUILD
+obj-y = common.o spl.o
+else
+obj-y = common.o cm_fx6.o
+endif
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
new file mode 100644
index 0000000000..fdb8ebf9e7
--- /dev/null
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -0,0 +1,483 @@
+/*
+ * Board functions for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <fdt_support.h>
+#include <sata.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/iomux.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/sata.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include "common.h"
+#include "../common/eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DWC_AHSATA
+static int cm_fx6_issd_gpios[] = {
+	/* The order of the GPIOs in the array is important! */
+	CM_FX6_SATA_PHY_SLP,
+	CM_FX6_SATA_NRSTDLY,
+	CM_FX6_SATA_PWREN,
+	CM_FX6_SATA_NSTANDBY1,
+	CM_FX6_SATA_NSTANDBY2,
+	CM_FX6_SATA_LDO_EN,
+};
+
+static void cm_fx6_sata_power(int on)
+{
+	int i;
+
+	if (!on) { /* tell the iSSD that the power will be removed */
+		gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
+		mdelay(10);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
+		gpio_direction_output(cm_fx6_issd_gpios[i], on);
+		udelay(100);
+	}
+
+	if (!on) /* for compatibility lower the power loss interrupt */
+		gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
+}
+
+static iomux_v3_cfg_t const sata_pads[] = {
+	/* SATA PWR */
+	IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* SATA CTRL */
+	IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void cm_fx6_setup_issd(void)
+{
+	SETUP_IOMUX_PADS(sata_pads);
+	/* Make sure this gpio has logical 0 value */
+	gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
+	udelay(100);
+
+	cm_fx6_sata_power(0);
+	mdelay(250);
+	cm_fx6_sata_power(1);
+}
+
+#define CM_FX6_SATA_INIT_RETRIES	10
+int sata_initialize(void)
+{
+	int err, i;
+
+	cm_fx6_setup_issd();
+	for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
+		err = setup_sata();
+		if (err) {
+			printf("SATA setup failed: %d\n", err);
+			return err;
+		}
+
+		udelay(100);
+
+		err = __sata_initialize();
+		if (!err)
+			break;
+
+		/* There is no device on the SATA port */
+		if (sata_port_status(0, 0) == 0)
+			break;
+
+		/* There's a device, but link not established. Retry */
+	}
+
+	return err;
+}
+#endif
+
+#ifdef CONFIG_SYS_I2C_MXC
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+			PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+			PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+I2C_PADS(i2c0_pads,
+	 PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 IMX_GPIO_NR(3, 21),
+	 PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 IMX_GPIO_NR(3, 28));
+
+I2C_PADS(i2c1_pads,
+	 PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 IMX_GPIO_NR(4, 12),
+	 PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 IMX_GPIO_NR(4, 13));
+
+I2C_PADS(i2c2_pads,
+	 PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 IMX_GPIO_NR(1, 3),
+	 PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	 IMX_GPIO_NR(1, 6));
+
+
+static void cm_fx6_setup_i2c(void)
+{
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c0_pads));
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c1_pads));
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, I2C_PADS_INFO(i2c2_pads));
+}
+#else
+static void cm_fx6_setup_i2c(void) { }
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define WEAK_PULLDOWN	(PAD_CTL_PUS_100K_DOWN |		\
+			PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+			PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
+
+static int cm_fx6_usb_hub_reset(void)
+{
+	int err;
+
+	err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
+	if (err) {
+		printf("USB hub rst gpio request failed: %d\n", err);
+		return -1;
+	}
+
+	SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
+	gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
+	udelay(10);
+	gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
+	mdelay(1);
+
+	return 0;
+}
+
+static int cm_fx6_init_usb_otg(void)
+{
+	int ret;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	ret = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
+	if (ret) {
+		printf("USB OTG pwr gpio request failed: %d\n", ret);
+		return ret;
+	}
+
+	SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
+	SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
+						MUX_PAD_CTRL(WEAK_PULLDOWN));
+	clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
+	/* disable ext. charger detect, or it'll affect signal quality at dp. */
+	return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
+}
+
+#define MX6_USBNC_BASEADDR	0x2184800
+#define USBNC_USB_H1_PWR_POL	(1 << 9)
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
+
+	switch (port) {
+	case 0:
+		return cm_fx6_init_usb_otg();
+	case 1:
+		SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR |
+				MUX_PAD_CTRL(NO_PAD_CTRL));
+
+		/* Set PWR polarity to match power switch's enable polarity */
+		setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
+		return cm_fx6_usb_hub_reset();
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+	if (port == 0)
+		return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+#define ENET_PAD_CTRL		(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+				 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+static int mx6_rgmii_rework(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* Ar8031 phy SmartEEE feature cause link status generates glitch,
+	 * which cause ethernet link down/up issue, so disable SmartEEE
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= ~(0x1 << 8);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	mx6_rgmii_rework(phydev);
+
+	if (phydev->drv->config)
+		return phydev->drv->config(phydev);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const enet_pads[] = {
+	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
+	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
+						MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
+						MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
+						MUX_PAD_CTRL(ENET_PAD_CTRL)),
+};
+
+static int handle_mac_address(void)
+{
+	unsigned char enetaddr[6];
+	int rc;
+
+	rc = eth_getenv_enetaddr("ethaddr", enetaddr);
+	if (rc)
+		return 0;
+
+	rc = cl_eeprom_read_mac_addr(enetaddr);
+	if (rc)
+		return rc;
+
+	if (!is_valid_ether_addr(enetaddr))
+		return -1;
+
+	return eth_setenv_enetaddr("ethaddr", enetaddr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int res = handle_mac_address();
+	if (res)
+		puts("No MAC address found\n");
+
+	SETUP_IOMUX_PADS(enet_pads);
+	/* phy reset */
+	gpio_direction_output(CM_FX6_ENET_NRST, 0);
+	udelay(500);
+	gpio_set_value(CM_FX6_ENET_NRST, 1);
+	enable_enet_clk(1);
+	return cpu_eth_init(bis);
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const nand_pads[] = {
+	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void cm_fx6_setup_gpmi_nand(void)
+{
+	SETUP_IOMUX_PADS(nand_pads);
+	/* Enable clock roots */
+	enable_usdhc_clk(1, 3);
+	enable_usdhc_clk(1, 4);
+
+	setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
+			  MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
+			  MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
+}
+#else
+static void cm_fx6_setup_gpmi_nand(void) {}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+	{USDHC1_BASE_ADDR},
+	{USDHC2_BASE_ADDR},
+	{USDHC3_BASE_ADDR},
+};
+
+static enum mxc_clock usdhc_clk[3] = {
+	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_ESDHC3_CLK,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	int i;
+
+	cm_fx6_set_usdhc_iomux();
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
+		usdhc_cfg[i].max_bus_width = 4;
+		fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		enable_usdhc_clk(1, i);
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	uint8_t enetaddr[6];
+
+	/* MAC addr */
+	if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
+		fdt_find_and_setprop(blob, "/fec", "local-mac-address",
+				     enetaddr, 6, 1);
+	}
+}
+#endif
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+	cm_fx6_setup_gpmi_nand();
+	cm_fx6_setup_i2c();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: CM-FX6\n");
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+
+	switch (gd->ram_size) {
+	case 0x10000000: /* DDR_16BIT_256MB */
+		gd->bd->bi_dram[0].size = 0x10000000;
+		gd->bd->bi_dram[1].size = 0;
+		break;
+	case 0x20000000: /* DDR_32BIT_512MB */
+		gd->bd->bi_dram[0].size = 0x20000000;
+		gd->bd->bi_dram[1].size = 0;
+		break;
+	case 0x40000000:
+		if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
+			gd->bd->bi_dram[0].size = 0x20000000;
+			gd->bd->bi_dram[1].size = 0x20000000;
+		} else { /* DDR_64BIT_1GB */
+			gd->bd->bi_dram[0].size = 0x40000000;
+			gd->bd->bi_dram[1].size = 0;
+		}
+		break;
+	case 0x80000000: /* DDR_64BIT_2GB */
+		gd->bd->bi_dram[0].size = 0x40000000;
+		gd->bd->bi_dram[1].size = 0x40000000;
+		break;
+	case 0xEFF00000: /* DDR_64BIT_4GB */
+		gd->bd->bi_dram[0].size = 0x70000000;
+		gd->bd->bi_dram[1].size = 0x7FF00000;
+		break;
+	}
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	switch (gd->ram_size) {
+	case 0x10000000:
+	case 0x20000000:
+	case 0x40000000:
+	case 0x80000000:
+		break;
+	case 0xF0000000:
+		gd->ram_size -= 0x100000;
+		break;
+	default:
+		printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
+		return -1;
+	}
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return cl_eeprom_get_board_rev();
+}
+
diff --git a/board/compulab/cm_fx6/common.c b/board/compulab/cm_fx6/common.c
new file mode 100644
index 0000000000..1f3967995f
--- /dev/null
+++ b/board/compulab/cm_fx6/common.c
@@ -0,0 +1,84 @@
+/*
+ * Code used by both U-Boot and SPL for Compulab CM-FX6
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <fsl_esdhc.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_FSL_ESDHC
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc_pads[] = {
+	IOMUX_PADS(PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+void cm_fx6_set_usdhc_iomux(void)
+{
+	SETUP_IOMUX_PADS(usdhc_pads);
+}
+
+/* CINS bit doesn't work, so always try to access the MMC card */
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#define ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+		PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const ecspi_pads[] = {
+	IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30  | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D19__ECSPI1_SS1  | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+};
+
+void cm_fx6_set_ecspi_iomux(void)
+{
+	SETUP_IOMUX_PADS(ecspi_pads);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (CM_FX6_ECSPI_BUS0_CS0) : -1;
+}
+#endif
diff --git a/board/compulab/cm_fx6/common.h b/board/compulab/cm_fx6/common.h
new file mode 100644
index 0000000000..76097f80af
--- /dev/null
+++ b/board/compulab/cm_fx6/common.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/clock.h>
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |	\
+			PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+			PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define CM_FX6_ECSPI_BUS0_CS0	IMX_GPIO_NR(2, 30)
+#define CM_FX6_GREEN_LED	IMX_GPIO_NR(2, 31)
+#define CM_FX6_ENET_NRST	IMX_GPIO_NR(2, 8)
+#define CM_FX6_ENET_NRST	IMX_GPIO_NR(2, 8)
+#define CM_FX6_USB_HUB_RST	IMX_GPIO_NR(7, 8)
+#define SB_FX6_USB_OTG_PWR	IMX_GPIO_NR(3, 22)
+#define CM_FX6_ENET_NRST	IMX_GPIO_NR(2, 8)
+#define CM_FX6_USB_HUB_RST	IMX_GPIO_NR(7, 8)
+#define SB_FX6_USB_OTG_PWR	IMX_GPIO_NR(3, 22)
+#define CM_FX6_SATA_PWREN	IMX_GPIO_NR(1, 28)
+#define CM_FX6_SATA_VDDC_CTRL	IMX_GPIO_NR(1, 30)
+#define CM_FX6_SATA_LDO_EN	IMX_GPIO_NR(2, 16)
+#define CM_FX6_SATA_NSTANDBY1	IMX_GPIO_NR(3, 20)
+#define CM_FX6_SATA_PHY_SLP	IMX_GPIO_NR(3, 23)
+#define CM_FX6_SATA_STBY_REQ	IMX_GPIO_NR(3, 29)
+#define CM_FX6_SATA_NSTANDBY2	IMX_GPIO_NR(5, 2)
+#define CM_FX6_SATA_NRSTDLY	IMX_GPIO_NR(6, 6)
+#define CM_FX6_SATA_PWLOSS_INT	IMX_GPIO_NR(6, 31)
+
+
+void cm_fx6_set_usdhc_iomux(void);
+void cm_fx6_set_ecspi_iomux(void);
diff --git a/board/compulab/cm_fx6/imximage.cfg b/board/compulab/cm_fx6/imximage.cfg
new file mode 100644
index 0000000000..420947e9ca
--- /dev/null
+++ b/board/compulab/cm_fx6/imximage.cfg
@@ -0,0 +1,8 @@
+/*
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+IMAGE_VERSION 2
+BOOT_FROM	sd
diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c
new file mode 100644
index 0000000000..3948ba23ae
--- /dev/null
+++ b/board/compulab/cm_fx6/spl.c
@@ -0,0 +1,366 @@
+/*
+ * SPL specific code for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <fsl_esdhc.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum ddr_config {
+	DDR_16BIT_256MB,
+	DDR_32BIT_512MB,
+	DDR_32BIT_1GB,
+	DDR_64BIT_1GB,
+	DDR_64BIT_2GB,
+	DDR_64BIT_4GB,
+	DDR_UNKNOWN,
+};
+
+/*
+ * Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to
+ * Freescale QRM, but this is exactly the value used by the automatic
+ * calibration script and it works also in all our tests, so we leave
+ * it as is at this point.
+ */
+#define CM_FX6_DDR_IOMUX_CFG \
+	.dram_sdqs0	= 0x00000038, \
+	.dram_sdqs1	= 0x00000038, \
+	.dram_sdqs2	= 0x00000038, \
+	.dram_sdqs3	= 0x00000038, \
+	.dram_sdqs4	= 0x00000038, \
+	.dram_sdqs5	= 0x00000038, \
+	.dram_sdqs6	= 0x00000038, \
+	.dram_sdqs7	= 0x00000038, \
+	.dram_dqm0	= 0x00000038, \
+	.dram_dqm1	= 0x00000038, \
+	.dram_dqm2	= 0x00000038, \
+	.dram_dqm3	= 0x00000038, \
+	.dram_dqm4	= 0x00000038, \
+	.dram_dqm5	= 0x00000038, \
+	.dram_dqm6	= 0x00000038, \
+	.dram_dqm7	= 0x00000038, \
+	.dram_cas	= 0x00000038, \
+	.dram_ras	= 0x00000038, \
+	.dram_sdclk_0	= 0x00000038, \
+	.dram_sdclk_1	= 0x00000038, \
+	.dram_sdcke0	= 0x00003000, \
+	.dram_sdcke1	= 0x00003000, \
+	.dram_reset	= 0x00000038, \
+	.dram_sdba2	= 0x00000000, \
+	.dram_sdodt0	= 0x00000038, \
+	.dram_sdodt1	= 0x00000038,
+
+#define CM_FX6_GPR_IOMUX_CFG \
+	.grp_b0ds	= 0x00000038, \
+	.grp_b1ds	= 0x00000038, \
+	.grp_b2ds	= 0x00000038, \
+	.grp_b3ds	= 0x00000038, \
+	.grp_b4ds	= 0x00000038, \
+	.grp_b5ds	= 0x00000038, \
+	.grp_b6ds	= 0x00000038, \
+	.grp_b7ds	= 0x00000038, \
+	.grp_addds	= 0x00000038, \
+	.grp_ddrmode_ctl = 0x00020000, \
+	.grp_ddrpke	= 0x00000000, \
+	.grp_ddrmode	= 0x00020000, \
+	.grp_ctlds	= 0x00000038, \
+	.grp_ddr_type	= 0x000C0000,
+
+static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG };
+static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG };
+static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG };
+static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG };
+
+static struct mx6_mmdc_calibration cm_fx6_calib_s = {
+	.p0_mpwldectrl0	= 0x005B0061,
+	.p0_mpwldectrl1	= 0x004F0055,
+	.p0_mpdgctrl0	= 0x0314030C,
+	.p0_mpdgctrl1	= 0x025C0268,
+	.p0_mprddlctl	= 0x42464646,
+	.p0_mpwrdlctl	= 0x36322C34,
+};
+
+static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = {
+	.cs1_mirror	= 1,
+	.cs_density	= 16,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 1,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = {
+	.mem_speed	= 800,
+	.density	= 4,
+	.rowaddr	= 14,
+	.coladdr	= 10,
+	.pagesz		= 2,
+	.trcd		= 1800,
+	.trcmin		= 5200,
+	.trasmin	= 3600,
+	.SRT		= 0,
+};
+
+static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset)
+{
+	if (reset)
+		((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
+
+	switch (dram_config) {
+	case DDR_16BIT_256MB:
+		cm_fx6_sysinfo_s.dsize = 0;
+		cm_fx6_sysinfo_s.ncs = 1;
+		break;
+	case DDR_32BIT_512MB:
+		cm_fx6_sysinfo_s.dsize = 1;
+		cm_fx6_sysinfo_s.ncs = 1;
+		break;
+	case DDR_32BIT_1GB:
+		cm_fx6_sysinfo_s.dsize = 1;
+		cm_fx6_sysinfo_s.ncs = 2;
+		break;
+	default:
+		puts("Tried to setup invalid DDR configuration\n");
+		hang();
+	}
+
+	mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s);
+	udelay(100);
+}
+
+static struct mx6_mmdc_calibration cm_fx6_calib_q = {
+	.p0_mpwldectrl0	= 0x00630068,
+	.p0_mpwldectrl1	= 0x0068005D,
+	.p0_mpdgctrl0	= 0x04140428,
+	.p0_mpdgctrl1	= 0x037C037C,
+	.p0_mprddlctl	= 0x3C30303A,
+	.p0_mpwrdlctl	= 0x3A344038,
+	.p1_mpwldectrl0	= 0x0035004C,
+	.p1_mpwldectrl1	= 0x00170026,
+	.p1_mpdgctrl0	= 0x0374037C,
+	.p1_mpdgctrl1	= 0x0350032C,
+	.p1_mprddlctl	= 0x30322A3C,
+	.p1_mpwrdlctl	= 0x48304A3E,
+};
+
+static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = {
+	.cs_density	= 16,
+	.cs1_mirror	= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 1,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = {
+	.mem_speed	= 1066,
+	.density	= 4,
+	.rowaddr	= 14,
+	.coladdr	= 10,
+	.pagesz		= 2,
+	.trcd		= 1324,
+	.trcmin		= 59500,
+	.trasmin	= 9750,
+	.SRT		= 0,
+};
+
+static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset)
+{
+	if (reset)
+		((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
+
+	cm_fx6_ddr3_cfg_q.rowaddr = 14;
+	switch (dram_config) {
+	case DDR_16BIT_256MB:
+		cm_fx6_sysinfo_q.dsize = 0;
+		cm_fx6_sysinfo_q.ncs = 1;
+		break;
+	case DDR_32BIT_512MB:
+		cm_fx6_sysinfo_q.dsize = 1;
+		cm_fx6_sysinfo_q.ncs = 1;
+		break;
+	case DDR_64BIT_1GB:
+		cm_fx6_sysinfo_q.dsize = 2;
+		cm_fx6_sysinfo_q.ncs = 1;
+		break;
+	case DDR_64BIT_2GB:
+		cm_fx6_sysinfo_q.dsize = 2;
+		cm_fx6_sysinfo_q.ncs = 2;
+		break;
+	case DDR_64BIT_4GB:
+		cm_fx6_sysinfo_q.dsize = 2;
+		cm_fx6_sysinfo_q.ncs = 2;
+		cm_fx6_ddr3_cfg_q.rowaddr = 15;
+		break;
+	default:
+		puts("Tried to setup invalid DDR configuration\n");
+		hang();
+	}
+
+	mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q);
+	udelay(100);
+}
+
+static int cm_fx6_spl_dram_init(void)
+{
+	unsigned long bank1_size, bank2_size;
+
+	switch (get_cpu_type()) {
+	case MXC_CPU_MX6SOLO:
+		mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s);
+
+		spl_mx6s_dram_init(DDR_32BIT_1GB, false);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x40000000)
+			return 0;
+
+		if (bank1_size == 0x20000000) {
+			spl_mx6s_dram_init(DDR_32BIT_512MB, true);
+			return 0;
+		}
+
+		spl_mx6s_dram_init(DDR_16BIT_256MB, true);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x10000000)
+			return 0;
+
+		break;
+	case MXC_CPU_MX6D:
+	case MXC_CPU_MX6Q:
+		mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q);
+
+		spl_mx6q_dram_init(DDR_64BIT_4GB, false);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x80000000)
+			return 0;
+
+		if (bank1_size == 0x40000000) {
+			bank2_size = get_ram_size((long int *)PHYS_SDRAM_2,
+								0x80000000);
+			if (bank2_size == 0x40000000) {
+				/* Don't do a full reset here */
+				spl_mx6q_dram_init(DDR_64BIT_2GB, false);
+			} else {
+				spl_mx6q_dram_init(DDR_64BIT_1GB, true);
+			}
+
+			return 0;
+		}
+
+		spl_mx6q_dram_init(DDR_32BIT_512MB, true);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x20000000)
+			return 0;
+
+		spl_mx6q_dram_init(DDR_16BIT_256MB, true);
+		bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+		if (bank1_size == 0x10000000)
+			return 0;
+
+		break;
+	}
+
+	return -1;
+}
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+	IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void cm_fx6_setup_uart(void)
+{
+	SETUP_IOMUX_PADS(uart4_pads);
+	enable_uart_clk(1);
+}
+
+#ifdef CONFIG_SPL_SPI_SUPPORT
+static void cm_fx6_setup_ecspi(void)
+{
+	cm_fx6_set_ecspi_iomux();
+	enable_cspi_clock(1, 0);
+}
+#else
+static void cm_fx6_setup_ecspi(void) { }
+#endif
+
+void board_init_f(ulong dummy)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	gd = &gdata;
+	/*
+	 * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
+	 * initializes DMA very early (before all board code), so the only
+	 * opportunity we have to initialize APBHDMA clocks is in SPL.
+	 */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+	enable_usdhc_clk(1, 2);
+
+	arch_cpu_init();
+	timer_init();
+	cm_fx6_setup_ecspi();
+	cm_fx6_setup_uart();
+	get_clocks();
+	preloader_console_init();
+	gpio_direction_output(CM_FX6_GREEN_LED, 1);
+	if (cm_fx6_spl_dram_init()) {
+		puts("!!!ERROR!!! DRAM detection failed!!!\n");
+		hang();
+	}
+
+	memset(__bss_start, 0, __bss_end - __bss_start);
+	board_init_r(NULL, 0);
+}
+
+void spl_board_init(void)
+{
+	u32 boot_device = spl_boot_device();
+
+	if (boot_device == BOOT_DEVICE_SPI)
+		puts("Booting from SPI flash\n");
+	else if (boot_device == BOOT_DEVICE_MMC1)
+		puts("Booting from MMC\n");
+	else
+		puts("Unknown boot device\n");
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+static struct fsl_esdhc_cfg usdhc_cfg = {
+	.esdhc_base = USDHC3_BASE_ADDR,
+	.max_bus_width = 4,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	cm_fx6_set_usdhc_iomux();
+
+	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+#endif
diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c
index 20fe3e1960..85442cd103 100644
--- a/board/compulab/common/eeprom.c
+++ b/board/compulab/common/eeprom.c
@@ -31,8 +31,19 @@ static int cl_eeprom_layout; /* Implicitly LAYOUT_INVALID */
 
 static int cl_eeprom_read(uint offset, uchar *buf, int len)
 {
-	return i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset,
+	int res;
+	unsigned int current_i2c_bus = i2c_get_bus_num();
+
+	res = i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
+	if (res < 0)
+		return res;
+
+	res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset,
 			CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len);
+
+	i2c_set_bus_num(current_i2c_bus);
+
+	return res;
 }
 
 static int cl_eeprom_setup_layout(void)
diff --git a/board/congatec/cgtqmx6eval/MAINTAINERS b/board/congatec/cgtqmx6eval/MAINTAINERS
index 53ad759c10..35f4a2a21a 100644
--- a/board/congatec/cgtqmx6eval/MAINTAINERS
+++ b/board/congatec/cgtqmx6eval/MAINTAINERS
@@ -1,5 +1,5 @@
 CGTQMX6EVAL BOARD
-M:	Leo Sartre <lsartre@adeneo-embedded.com>
+#M:	Leo Sartre <lsartre@adeneo-embedded.com>
 S:	Orphan (since 2014-06)
 F:	board/congatec/cgtqmx6eval/
 F:	include/configs/cgtqmx6eval.h
diff --git a/board/cpu87/MAINTAINERS b/board/cpu87/MAINTAINERS
index 6e84f601f5..32804ea53c 100644
--- a/board/cpu87/MAINTAINERS
+++ b/board/cpu87/MAINTAINERS
@@ -1,5 +1,5 @@
 CPU87 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/cpu87/
 F:	include/configs/CPU87.h
diff --git a/board/cray/L1/MAINTAINERS b/board/cray/L1/MAINTAINERS
index e93819ecfa..e43e91febe 100644
--- a/board/cray/L1/MAINTAINERS
+++ b/board/cray/L1/MAINTAINERS
@@ -1,5 +1,5 @@
 L1 BOARD
-M:	David Updegraff <dave@cray.com>
+#M:	David Updegraff <dave@cray.com>
 S:	Orphan (since 2014-03)
 F:	board/cray/L1/
 F:	include/configs/CRAYL1.h
diff --git a/board/dave/PPChameleonEVB/MAINTAINERS b/board/dave/PPChameleonEVB/MAINTAINERS
index 3af5b5704b..d43c6d03f2 100644
--- a/board/dave/PPChameleonEVB/MAINTAINERS
+++ b/board/dave/PPChameleonEVB/MAINTAINERS
@@ -1,5 +1,5 @@
 PPCHAMELEONEVB BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/dave/PPChameleonEVB/
 F:	include/configs/CATcenter.h
diff --git a/board/davinci/dm355evm/MAINTAINERS b/board/davinci/dm355evm/MAINTAINERS
index ef586b3884..c017e09717 100644
--- a/board/davinci/dm355evm/MAINTAINERS
+++ b/board/davinci/dm355evm/MAINTAINERS
@@ -1,5 +1,5 @@
 DM355EVM BOARD
-M:	Sandeep Paulraj <s-paulraj@ti.com>
+#M:	Sandeep Paulraj <s-paulraj@ti.com>
 S:	Orphan (since 2014-08)
 F:	board/davinci/dm355evm/
 F:	include/configs/davinci_dm355evm.h
diff --git a/board/davinci/dm355leopard/MAINTAINERS b/board/davinci/dm355leopard/MAINTAINERS
index 2fc1e00d5a..ed04d4354b 100644
--- a/board/davinci/dm355leopard/MAINTAINERS
+++ b/board/davinci/dm355leopard/MAINTAINERS
@@ -1,5 +1,5 @@
 DM355LEOPARD BOARD
-M:	Sandeep Paulraj <s-paulraj@ti.com>
+#M:	Sandeep Paulraj <s-paulraj@ti.com>
 S:	Orphan (since 2014-08)
 F:	board/davinci/dm355leopard/
 F:	include/configs/davinci_dm355leopard.h
diff --git a/board/davinci/dm365evm/MAINTAINERS b/board/davinci/dm365evm/MAINTAINERS
index 0bfe02d0ea..97c3ed3b69 100644
--- a/board/davinci/dm365evm/MAINTAINERS
+++ b/board/davinci/dm365evm/MAINTAINERS
@@ -1,5 +1,5 @@
 DM365EVM BOARD
-M:	Sandeep Paulraj <s-paulraj@ti.com>
+#M:	Sandeep Paulraj <s-paulraj@ti.com>
 S:	Orphan (since 2014-08)
 F:	board/davinci/dm365evm/
 F:	include/configs/davinci_dm365evm.h
diff --git a/board/davinci/dm6467evm/MAINTAINERS b/board/davinci/dm6467evm/MAINTAINERS
index bb4053626d..8ca53c43c8 100644
--- a/board/davinci/dm6467evm/MAINTAINERS
+++ b/board/davinci/dm6467evm/MAINTAINERS
@@ -1,5 +1,5 @@
 DM6467EVM BOARD
-M:	Sandeep Paulraj <s-paulraj@ti.com>
+#M:	Sandeep Paulraj <s-paulraj@ti.com>
 S:	Orphan (since 2014-08)
 F:	board/davinci/dm6467evm/
 F:	include/configs/davinci_dm6467evm.h
diff --git a/board/davinci/dvevm/MAINTAINERS b/board/davinci/dvevm/MAINTAINERS
index 4b3ce45d4f..a718b90050 100644
--- a/board/davinci/dvevm/MAINTAINERS
+++ b/board/davinci/dvevm/MAINTAINERS
@@ -1,5 +1,5 @@
 DVEVM BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/davinci/dvevm/
 F:	include/configs/davinci_dvevm.h
diff --git a/board/davinci/schmoogie/MAINTAINERS b/board/davinci/schmoogie/MAINTAINERS
index b1fc29c019..808e7fc046 100644
--- a/board/davinci/schmoogie/MAINTAINERS
+++ b/board/davinci/schmoogie/MAINTAINERS
@@ -1,5 +1,5 @@
 SCHMOOGIE BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/davinci/schmoogie/
 F:	include/configs/davinci_schmoogie.h
diff --git a/board/davinci/sffsdr/MAINTAINERS b/board/davinci/sffsdr/MAINTAINERS
index 428d003abc..5c7e1324a9 100644
--- a/board/davinci/sffsdr/MAINTAINERS
+++ b/board/davinci/sffsdr/MAINTAINERS
@@ -1,5 +1,5 @@
 SFFSDR BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/davinci/sffsdr/
 F:	include/configs/davinci_sffsdr.h
diff --git a/board/davinci/sonata/MAINTAINERS b/board/davinci/sonata/MAINTAINERS
index 625978ca62..40659e5210 100644
--- a/board/davinci/sonata/MAINTAINERS
+++ b/board/davinci/sonata/MAINTAINERS
@@ -1,5 +1,5 @@
 SONATA BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/davinci/sonata/
 F:	include/configs/davinci_sonata.h
diff --git a/board/earthlcd/favr-32-ezkit/MAINTAINERS b/board/earthlcd/favr-32-ezkit/MAINTAINERS
index 30453c6b16..89ba862149 100644
--- a/board/earthlcd/favr-32-ezkit/MAINTAINERS
+++ b/board/earthlcd/favr-32-ezkit/MAINTAINERS
@@ -1,5 +1,5 @@
 FAVR-32-EZKIT BOARD
-M:	Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
+#M:	Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
 S:	Orphan (since 2014-06)
 F:	board/earthlcd/favr-32-ezkit/
 F:	include/configs/favr-32-ezkit.h
diff --git a/board/eltec/elppc/MAINTAINERS b/board/eltec/elppc/MAINTAINERS
index 5258b3a7ca..e3b35f1101 100644
--- a/board/eltec/elppc/MAINTAINERS
+++ b/board/eltec/elppc/MAINTAINERS
@@ -1,5 +1,5 @@
 ELPPC BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/eltec/elppc/
 F:	include/configs/ELPPC.h
diff --git a/board/eltec/mhpc/u-boot.lds b/board/eltec/mhpc/u-boot.lds
deleted file mode 100644
index 7ae91ffb2e..0000000000
--- a/board/eltec/mhpc/u-boot.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2001-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c
index 530ea4f3c4..a725f15a2e 100644
--- a/board/embest/mx6boards/mx6boards.c
+++ b/board/embest/mx6boards/mx6boards.c
@@ -285,6 +285,11 @@ iomux_v3_cfg_t const ecspi1_pads[] = {
 	MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
+}
+
 static void setup_spi(void)
 {
 	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
diff --git a/board/emk/top860/u-boot.lds b/board/emk/top860/u-boot.lds
deleted file mode 100644
index 79fcbf4adc..0000000000
--- a/board/emk/top860/u-boot.lds
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/ep8260/MAINTAINERS b/board/ep8260/MAINTAINERS
index bb273df6d4..bfa923caf6 100644
--- a/board/ep8260/MAINTAINERS
+++ b/board/ep8260/MAINTAINERS
@@ -1,5 +1,5 @@
 EP8260 BOARD
-M:	Frank Panno <fpanno@delphintech.com>
+#M:	Frank Panno <fpanno@delphintech.com>
 S:	Orphan (since 2014-06)
 F:	board/ep8260/
 F:	include/configs/ep8260.h
diff --git a/board/ep82xxm/MAINTAINERS b/board/ep82xxm/MAINTAINERS
index 822261be78..c053df9160 100644
--- a/board/ep82xxm/MAINTAINERS
+++ b/board/ep82xxm/MAINTAINERS
@@ -1,5 +1,5 @@
 EP82XXM BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/ep82xxm/
 F:	include/configs/ep82xxm.h
diff --git a/board/esg/ima3-mx53/MAINTAINERS b/board/esg/ima3-mx53/MAINTAINERS
index c434eb93a3..96de0815c7 100644
--- a/board/esg/ima3-mx53/MAINTAINERS
+++ b/board/esg/ima3-mx53/MAINTAINERS
@@ -1,5 +1,5 @@
 IMA3-MX53 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/esg/ima3-mx53/
 F:	include/configs/ima3-mx53.h
diff --git a/board/espt/MAINTAINERS b/board/espt/MAINTAINERS
index ff6e20c067..fdbbc3eb45 100644
--- a/board/espt/MAINTAINERS
+++ b/board/espt/MAINTAINERS
@@ -1,5 +1,5 @@
 ESPT BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/espt/
 F:	include/configs/espt.h
diff --git a/board/evb64260/MAINTAINERS b/board/evb64260/MAINTAINERS
index f8307ccf51..d50dda523e 100644
--- a/board/evb64260/MAINTAINERS
+++ b/board/evb64260/MAINTAINERS
@@ -6,7 +6,7 @@ F:	include/configs/P3G4.h
 F:	configs/P3G4_defconfig
 
 ZUMA BOARD
-M:	Nye Liu <nyet@zumanetworks.com>
+#M:	Nye Liu <nyet@zumanetworks.com>
 S:	Orphan (since 2014-04)
 F:	include/configs/ZUMA.h
 F:	configs/ZUMA_defconfig
diff --git a/board/exmeritus/hww1u1a/MAINTAINERS b/board/exmeritus/hww1u1a/MAINTAINERS
index e2fe2a6b66..b37f10b17a 100644
--- a/board/exmeritus/hww1u1a/MAINTAINERS
+++ b/board/exmeritus/hww1u1a/MAINTAINERS
@@ -1,5 +1,5 @@
 HWW1U1A BOARD
-M:	Kyle Moffett <Kyle.D.Moffett@boeing.com>
+#M:	Kyle Moffett <Kyle.D.Moffett@boeing.com>
 S:	Orphan (since 2014-06)
 F:	board/exmeritus/hww1u1a/
 F:	include/configs/HWW1U1A.h
diff --git a/board/freescale/b4860qds/MAINTAINERS b/board/freescale/b4860qds/MAINTAINERS
index 9f9a612a61..ac02bb7e48 100644
--- a/board/freescale/b4860qds/MAINTAINERS
+++ b/board/freescale/b4860qds/MAINTAINERS
@@ -1,5 +1,5 @@
 B4860QDS BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/b4860qds/
 F:	include/configs/B4860QDS.h
diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c
index 6789efb9c3..e683be324a 100644
--- a/board/freescale/common/ics307_clk.c
+++ b/board/freescale/common/ics307_clk.c
@@ -67,7 +67,7 @@ unsigned long ics307_sysclk_calculator(unsigned long out_freq)
 				continue;
 			/* Calculate the temp out frequency */
 			tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);
-			diff = MAX(out_freq, tmp_out) - MIN(out_freq, tmp_out);
+			diff = max(out_freq, tmp_out) - min(out_freq, tmp_out);
 			/*
 			 * calculate the percent, the precision is 1/1000
 			 * If greater than 1/1000, continue
diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS
index 841d82fdd8..c8ca6746f1 100644
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ b/board/freescale/corenet_ds/MAINTAINERS
@@ -1,5 +1,5 @@
 CORENET_DS BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/corenet_ds/
 F:	include/configs/P3041DS.h
diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS
index 021d82b74d..ccf45131b8 100644
--- a/board/freescale/ls1021aqds/MAINTAINERS
+++ b/board/freescale/ls1021aqds/MAINTAINERS
@@ -4,3 +4,4 @@ S:	Maintained
 F:	board/freescale/ls1021aqds/
 F:	include/configs/ls1021aqds.h
 F:	configs/ls1021aqds_nor_defconfig
+F:	configs/ls1021aqds_ddr4_nor_defconfig
diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
index 679c654fb5..5898e33744 100644
--- a/board/freescale/ls1021aqds/ddr.c
+++ b/board/freescale/ls1021aqds/ddr.c
@@ -79,7 +79,6 @@ found:
 	 */
 	popts->wrlvl_override = 1;
 	popts->wrlvl_sample = 0xf;
-	popts->cswl_override = DDR_CSWL_CS0;
 
 	/*
 	 * Rtt and Rtt_WR override
@@ -89,9 +88,17 @@ found:
 	/* Enable ZQ calibration */
 	popts->zq_en = 1;
 
+#ifdef CONFIG_SYS_FSL_DDR4
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+			  DDR_CDR2_VREF_OVRD(70);	/* Vref = 70% */
+#else
+	popts->cswl_override = DDR_CSWL_CS0;
+
 	/* DHC_EN =1, ODT = 75 Ohm */
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
 }
 
 #ifdef CONFIG_SYS_DDR_RAW_TIMING
diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h
index 16d87cbe82..f819c99dba 100644
--- a/board/freescale/ls1021aqds/ddr.h
+++ b/board/freescale/ls1021aqds/ddr.h
@@ -30,6 +30,13 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
+#ifdef CONFIG_SYS_FSL_DDR4
+	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
+	{2,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
+	{1,  1666, 0, 4,     8, 0x090A0B0B, 0x0C0D0E0C,},
+	{1,  1900, 0, 4,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
+	{1,  2200, 0, 4,    10, 0x0B0C0D0C, 0x0E0F110E,},
+#elif defined(CONFIG_SYS_FSL_DDR3)
 	{1,  833,  1, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
 	{1,  1350, 1, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
 	{1,  833,  2, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
@@ -39,6 +46,9 @@ static const struct board_specific_parameters udimm0[] = {
 	{2,  1350, 0, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
 	{2,  1666, 4, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
 	{2,  1666, 0, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+#else
+#error DDR type not defined
+#endif
 	{}
 };
 
diff --git a/board/freescale/ls2085a/Kconfig b/board/freescale/ls2085a/Kconfig
index 798b491dcc..f51afc8234 100644
--- a/board/freescale/ls2085a/Kconfig
+++ b/board/freescale/ls2085a/Kconfig
@@ -1,8 +1,5 @@
 if TARGET_LS2085A_EMU
 
-config SYS_CPU
-	default "armv8"
-
 config SYS_BOARD
 	default "ls2085a"
 
@@ -19,9 +16,6 @@ endif
 
 if TARGET_LS2085A_SIMU
 
-config SYS_CPU
-	default "armv8"
-
 config SYS_BOARD
 	default "ls2085a"
 
diff --git a/board/freescale/ls2085a/ddr.c b/board/freescale/ls2085a/ddr.c
index 257bc162d0..b4a3fc9a9e 100644
--- a/board/freescale/ls2085a/ddr.c
+++ b/board/freescale/ls2085a/ddr.c
@@ -30,9 +30,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
 	 */
 	if (popts->registered_dimm_en)
-		pbsp = rdimms[0];
+		pbsp = rdimms[ctrl_num];
 	else
-		pbsp = udimms[0];
+		pbsp = udimms[ctrl_num];
 
 
 	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
@@ -72,6 +72,12 @@ found:
 		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
 		pbsp->wrlvl_ctl_3);
 
+	if (ctrl_num == CONFIG_DP_DDR_CTRL) {
+		/* force DDR bus width to 32 bits */
+		popts->data_bus_width = 1;
+		popts->otf_burst_chop_en = 0;
+		popts->burst_length = DDR_BL8;
+	}
 	/*
 	 * Factors to consider for half-strength driver enable:
 	 *	- number of DIMMs installed
@@ -163,6 +169,10 @@ phys_size_t initdram(int board_type)
 
 void dram_init_banksize(void)
 {
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+	phys_size_t dp_ddr_size;
+#endif
+
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
 		gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
@@ -172,4 +182,24 @@ void dram_init_banksize(void)
 	} else {
 		gd->bd->bi_dram[0].size = gd->ram_size;
 	}
+
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+	/* initialize DP-DDR here */
+	puts("DP-DDR:  ");
+	/*
+	 * DDR controller use 0 as the base address for binding.
+	 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+	 */
+	dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+					  CONFIG_DP_DDR_CTRL,
+					  CONFIG_DP_DDR_NUM_CTRLS,
+					  CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
+					  NULL, NULL, NULL);
+	if (dp_ddr_size) {
+		gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+		gd->bd->bi_dram[2].size = dp_ddr_size;
+	} else {
+		puts("Not detected");
+	}
+#endif
 }
diff --git a/board/freescale/ls2085a/ddr.h b/board/freescale/ls2085a/ddr.h
index 77f6aafe3d..9958a68e3e 100644
--- a/board/freescale/ls2085a/ddr.h
+++ b/board/freescale/ls2085a/ddr.h
@@ -33,6 +33,18 @@ static const struct board_specific_parameters udimm0[] = {
 	{}
 };
 
+/* DP-DDR DIMM */
+static const struct board_specific_parameters udimm2[] = {
+	/*
+	 * memory controller 2
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  2140, 0, 4,     4, 0x0, 0x0},
+	{1,  2140, 0, 4,     4, 0x0, 0x0},
+	{}
+};
+
 static const struct board_specific_parameters rdimm0[] = {
 	/*
 	 * memory controller 0
@@ -45,12 +57,29 @@ static const struct board_specific_parameters rdimm0[] = {
 	{}
 };
 
+/* DP-DDR DIMM */
+static const struct board_specific_parameters rdimm2[] = {
+	/*
+	 * memory controller 2
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{4,  2140, 0, 5,     4, 0x0, 0x0},
+	{2,  2140, 0, 5,     4, 0x0, 0x0},
+	{1,  2140, 0, 4,     4, 0x0, 0x0},
+	{}
+};
+
 static const struct board_specific_parameters *udimms[] = {
 	udimm0,
+	udimm0,
+	udimm2,
 };
 
 static const struct board_specific_parameters *rdimms[] = {
 	rdimm0,
+	rdimm0,
+	rdimm2,
 };
 
 
diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c
index a18db1d714..2c79a7181e 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -13,12 +13,18 @@
 #include <fdt_support.h>
 #include <libfdt.h>
 #include <fsl_mc.h>
+#include <environment.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
 	init_final_memctl_regs();
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+
 	return 0;
 }
 
@@ -29,9 +35,20 @@ int board_early_init_f(void)
 	return 0;
 }
 
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+	print_ddr_info(0);
+	if (gd->bd->bi_dram[2].size) {
+		puts("\nDP-DDR ");
+		print_size(gd->bd->bi_dram[2].size, "");
+		print_ddr_info(CONFIG_DP_DDR_CTRL);
+	}
+}
+
 int dram_init(void)
 {
-	printf("DRAM:  ");
 	gd->ram_size = initdram(0);
 
 	return 0;
@@ -88,6 +105,8 @@ void ft_board_setup(void *blob, bd_t *bd)
 	phys_addr_t base;
 	phys_size_t size;
 
+	ft_cpu_setup(blob, bd);
+
 	/* limit the memory size to bank 1 until Linux can handle 40-bit PA */
 	base = getenv_bootm_low();
 	size = getenv_bootm_size();
diff --git a/board/freescale/m5208evbe/MAINTAINERS b/board/freescale/m5208evbe/MAINTAINERS
index 65d04df250..c9c3c882e6 100644
--- a/board/freescale/m5208evbe/MAINTAINERS
+++ b/board/freescale/m5208evbe/MAINTAINERS
@@ -1,5 +1,5 @@
 M5208EVBE BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/m5208evbe/
 F:	include/configs/M5208EVBE.h
diff --git a/board/freescale/m5249evb/MAINTAINERS b/board/freescale/m5249evb/MAINTAINERS
index 22301b770e..c2273c35e1 100644
--- a/board/freescale/m5249evb/MAINTAINERS
+++ b/board/freescale/m5249evb/MAINTAINERS
@@ -1,5 +1,5 @@
 M5249EVB BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/m5249evb/
 F:	include/configs/M5249EVB.h
diff --git a/board/freescale/m5253evbe/MAINTAINERS b/board/freescale/m5253evbe/MAINTAINERS
index 1c21b03c38..74acd1eee5 100644
--- a/board/freescale/m5253evbe/MAINTAINERS
+++ b/board/freescale/m5253evbe/MAINTAINERS
@@ -1,5 +1,5 @@
 M5253EVBE BOARD
-M:	Hayden Fraser <Hayden.Fraser@freescale.com>
+#M:	Hayden Fraser <Hayden.Fraser@freescale.com>
 S:	Orphan (since 2014-06)
 F:	board/freescale/m5253evbe/
 F:	include/configs/M5253EVBE.h
diff --git a/board/freescale/m5272c3/MAINTAINERS b/board/freescale/m5272c3/MAINTAINERS
index aa4739f744..e58663096d 100644
--- a/board/freescale/m5272c3/MAINTAINERS
+++ b/board/freescale/m5272c3/MAINTAINERS
@@ -1,5 +1,5 @@
 M5272C3 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/m5272c3/
 F:	include/configs/M5272C3.h
diff --git a/board/freescale/m5275evb/MAINTAINERS b/board/freescale/m5275evb/MAINTAINERS
index b87d52c64f..4e6dbb12d9 100644
--- a/board/freescale/m5275evb/MAINTAINERS
+++ b/board/freescale/m5275evb/MAINTAINERS
@@ -1,5 +1,5 @@
 M5275EVB BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/m5275evb/
 F:	include/configs/M5275EVB.h
diff --git a/board/freescale/m5282evb/MAINTAINERS b/board/freescale/m5282evb/MAINTAINERS
index f945ab446b..305e748e74 100644
--- a/board/freescale/m5282evb/MAINTAINERS
+++ b/board/freescale/m5282evb/MAINTAINERS
@@ -1,5 +1,5 @@
 M5282EVB BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/m5282evb/
 F:	include/configs/M5282EVB.h
diff --git a/board/freescale/m54418twr/MAINTAINERS b/board/freescale/m54418twr/MAINTAINERS
index 37b24c7be8..f88aed99d6 100644
--- a/board/freescale/m54418twr/MAINTAINERS
+++ b/board/freescale/m54418twr/MAINTAINERS
@@ -1,5 +1,5 @@
 M54418TWR BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/m54418twr/
 F:	include/configs/M54418TWR.h
diff --git a/board/freescale/m54451evb/MAINTAINERS b/board/freescale/m54451evb/MAINTAINERS
index be145494cb..52a2681080 100644
--- a/board/freescale/m54451evb/MAINTAINERS
+++ b/board/freescale/m54451evb/MAINTAINERS
@@ -1,5 +1,5 @@
 M54451EVB BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/m54451evb/
 F:	include/configs/M54451EVB.h
diff --git a/board/freescale/mpc5121ads/MAINTAINERS b/board/freescale/mpc5121ads/MAINTAINERS
index 0c7f682f95..d4aab8fb51 100644
--- a/board/freescale/mpc5121ads/MAINTAINERS
+++ b/board/freescale/mpc5121ads/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC5121ADS BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/mpc5121ads/
 F:	include/configs/mpc5121ads.h
diff --git a/board/freescale/mpc8313erdb/MAINTAINERS b/board/freescale/mpc8313erdb/MAINTAINERS
index 923ba95404..807fb0b6e9 100644
--- a/board/freescale/mpc8313erdb/MAINTAINERS
+++ b/board/freescale/mpc8313erdb/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8313ERDB BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/mpc8313erdb/
 F:	include/configs/MPC8313ERDB.h
diff --git a/board/freescale/mpc8349itx/MAINTAINERS b/board/freescale/mpc8349itx/MAINTAINERS
index ed6e4e54dd..d0388ad6e5 100644
--- a/board/freescale/mpc8349itx/MAINTAINERS
+++ b/board/freescale/mpc8349itx/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8349ITX BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/mpc8349itx/
 F:	include/configs/MPC8349ITX.h
diff --git a/board/freescale/mpc8360erdk/MAINTAINERS b/board/freescale/mpc8360erdk/MAINTAINERS
index cb075d62a9..e5b5995f78 100644
--- a/board/freescale/mpc8360erdk/MAINTAINERS
+++ b/board/freescale/mpc8360erdk/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8360ERDK BOARD
-M:	Anton Vorontsov <avorontsov@ru.mvista.com>
+#M:	Anton Vorontsov <avorontsov@ru.mvista.com>
 S:	Orphan (since 2014-03)
 F:	board/freescale/mpc8360erdk/
 F:	include/configs/MPC8360ERDK.h
diff --git a/board/freescale/mpc837xerdb/MAINTAINERS b/board/freescale/mpc837xerdb/MAINTAINERS
index c216d8da06..8592a2c3c1 100644
--- a/board/freescale/mpc837xerdb/MAINTAINERS
+++ b/board/freescale/mpc837xerdb/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC837XERDB BOARD
-M:	Joe D'Abbraccio <ljd015@freescale.com>
+#M:	Joe D'Abbraccio <ljd015@freescale.com>
 S:	Orphan (since 2014-06)
 F:	board/freescale/mpc837xerdb/
 F:	include/configs/MPC837XERDB.h
diff --git a/board/freescale/mpc8536ds/MAINTAINERS b/board/freescale/mpc8536ds/MAINTAINERS
index 51d7cd7bac..953072cdd0 100644
--- a/board/freescale/mpc8536ds/MAINTAINERS
+++ b/board/freescale/mpc8536ds/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8536DS BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/mpc8536ds/
 F:	include/configs/MPC8536DS.h
diff --git a/board/freescale/mpc8540ads/MAINTAINERS b/board/freescale/mpc8540ads/MAINTAINERS
index 41a2191577..acc48218d4 100644
--- a/board/freescale/mpc8540ads/MAINTAINERS
+++ b/board/freescale/mpc8540ads/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8540ADS BOARD
-M:	Kumar Gala <kumar.gala@freescale.com>
+#M:	Kumar Gala <kumar.gala@freescale.com>
 S:	Orphan (since 2014-06)
 F:	board/freescale/mpc8540ads/
 F:	include/configs/MPC8540ADS.h
diff --git a/board/freescale/mpc8541cds/MAINTAINERS b/board/freescale/mpc8541cds/MAINTAINERS
index 073210d9ad..d421b1281b 100644
--- a/board/freescale/mpc8541cds/MAINTAINERS
+++ b/board/freescale/mpc8541cds/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8541CDS BOARD
-M:	Kumar Gala <kumar.gala@freescale.com>
+#M:	Kumar Gala <kumar.gala@freescale.com>
 S:	Orphan (since 2014-06)
 F:	board/freescale/mpc8541cds/
 F:	include/configs/MPC8541CDS.h
diff --git a/board/freescale/mpc8544ds/MAINTAINERS b/board/freescale/mpc8544ds/MAINTAINERS
index 81b664c732..328be7fecc 100644
--- a/board/freescale/mpc8544ds/MAINTAINERS
+++ b/board/freescale/mpc8544ds/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8544DS BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/mpc8544ds/
 F:	include/configs/MPC8544DS.h
diff --git a/board/freescale/mpc8548cds/MAINTAINERS b/board/freescale/mpc8548cds/MAINTAINERS
index 89b2425d0b..6f229227c0 100644
--- a/board/freescale/mpc8548cds/MAINTAINERS
+++ b/board/freescale/mpc8548cds/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8548CDS BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/mpc8548cds/
 F:	include/configs/MPC8548CDS.h
diff --git a/board/freescale/mpc8555cds/MAINTAINERS b/board/freescale/mpc8555cds/MAINTAINERS
index 14470d72ee..1ef669000f 100644
--- a/board/freescale/mpc8555cds/MAINTAINERS
+++ b/board/freescale/mpc8555cds/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8555CDS BOARD
-M:	Kumar Gala <kumar.gala@freescale.com>
+#M:	Kumar Gala <kumar.gala@freescale.com>
 S:	Orphan (since 2014-06)
 F:	board/freescale/mpc8555cds/
 F:	include/configs/MPC8555CDS.h
diff --git a/board/freescale/mpc8560ads/MAINTAINERS b/board/freescale/mpc8560ads/MAINTAINERS
index 836def2a27..96e6da2aad 100644
--- a/board/freescale/mpc8560ads/MAINTAINERS
+++ b/board/freescale/mpc8560ads/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8560ADS BOARD
-M:	Kumar Gala <kumar.gala@freescale.com>
+#M:	Kumar Gala <kumar.gala@freescale.com>
 S:	Orphan (since 2014-06)
 F:	board/freescale/mpc8560ads/
 F:	include/configs/MPC8560ADS.h
diff --git a/board/freescale/mpc8568mds/MAINTAINERS b/board/freescale/mpc8568mds/MAINTAINERS
index 72c25f5f8e..379d8cc1d5 100644
--- a/board/freescale/mpc8568mds/MAINTAINERS
+++ b/board/freescale/mpc8568mds/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8568MDS BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/mpc8568mds/
 F:	include/configs/MPC8568MDS.h
diff --git a/board/freescale/mpc8569mds/MAINTAINERS b/board/freescale/mpc8569mds/MAINTAINERS
index b5478dbc17..c181407f25 100644
--- a/board/freescale/mpc8569mds/MAINTAINERS
+++ b/board/freescale/mpc8569mds/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8569MDS BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/mpc8569mds/
 F:	include/configs/MPC8569MDS.h
diff --git a/board/freescale/mpc8610hpcd/MAINTAINERS b/board/freescale/mpc8610hpcd/MAINTAINERS
index 993c02a15e..de6ab89299 100644
--- a/board/freescale/mpc8610hpcd/MAINTAINERS
+++ b/board/freescale/mpc8610hpcd/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8610HPCD BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/mpc8610hpcd/
 F:	include/configs/MPC8610HPCD.h
diff --git a/board/freescale/mpc8641hpcn/MAINTAINERS b/board/freescale/mpc8641hpcn/MAINTAINERS
index 34bcc6cd0b..97902475ba 100644
--- a/board/freescale/mpc8641hpcn/MAINTAINERS
+++ b/board/freescale/mpc8641hpcn/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8641HPCN BOARD
-M:	Kumar Gala <kumar.gala@freescale.com>
+#M:	Kumar Gala <kumar.gala@freescale.com>
 S:	Orphan (since 2014-06)
 F:	board/freescale/mpc8641hpcn/
 F:	include/configs/MPC8641HPCN.h
diff --git a/board/freescale/mx31ads/MAINTAINERS b/board/freescale/mx31ads/MAINTAINERS
index e9c8fe78e0..5f6ec268c7 100644
--- a/board/freescale/mx31ads/MAINTAINERS
+++ b/board/freescale/mx31ads/MAINTAINERS
@@ -1,5 +1,5 @@
 MX31ADS BOARD
-M:	(resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+#M:	(resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 S:	Orphan (since 2013-09)
 F:	board/freescale/mx31ads/
 F:	include/configs/mx31ads.h
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 928dadf809..836d7221b0 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -259,6 +259,13 @@ int board_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
+}
+#endif
+
 #ifdef CONFIG_CMD_BMODE
 static const struct boot_mode board_boot_modes[] = {
 	/* 4 bit bus width */
diff --git a/board/freescale/mx6sabresd/mx6dlsabresd.cfg b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
new file mode 100644
index 0000000000..f35f22ea82
--- /dev/null
+++ b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4	0x020e0774 0x000C0000
+DATA 4	0x020e0754 0x00000000
+DATA 4	0x020e04ac 0x00000030
+DATA 4	0x020e04b0 0x00000030
+DATA 4	0x020e0464 0x00000030
+DATA 4	0x020e0490 0x00000030
+DATA 4	0x020e074c 0x00000030
+DATA 4	0x020e0494 0x00000030
+DATA 4	0x020e04a0 0x00000000
+DATA 4	0x020e04b4 0x00000030
+DATA 4	0x020e04b8 0x00000030
+DATA 4	0x020e076c 0x00000030
+DATA 4	0x020e0750 0x00020000
+DATA 4	0x020e04bc 0x00000030
+DATA 4	0x020e04c0 0x00000030
+DATA 4	0x020e04c4 0x00000030
+DATA 4	0x020e04c8 0x00000030
+DATA 4	0x020e04cc 0x00000030
+DATA 4	0x020e04d0 0x00000030
+DATA 4	0x020e04d4 0x00000030
+DATA 4	0x020e04d8 0x00000030
+DATA 4	0x020e0760 0x00020000
+DATA 4	0x020e0764 0x00000030
+DATA 4	0x020e0770 0x00000030
+DATA 4	0x020e0778 0x00000030
+DATA 4	0x020e077c 0x00000030
+DATA 4	0x020e0780 0x00000030
+DATA 4	0x020e0784 0x00000030
+DATA 4	0x020e078c 0x00000030
+DATA 4	0x020e0748 0x00000030
+DATA 4	0x020e0470 0x00000030
+DATA 4	0x020e0474 0x00000030
+DATA 4	0x020e0478 0x00000030
+DATA 4	0x020e047c 0x00000030
+DATA 4	0x020e0480 0x00000030
+DATA 4	0x020e0484 0x00000030
+DATA 4	0x020e0488 0x00000030
+DATA 4	0x020e048c 0x00000030
+DATA 4	0x021b0800 0xa1390003
+DATA 4	0x021b080c 0x001F001F
+DATA 4	0x021b0810 0x001F001F
+DATA 4	0x021b480c 0x001F001F
+DATA 4	0x021b4810 0x001F001F
+DATA 4	0x021b083c 0x4220021F
+DATA 4	0x021b0840 0x0207017E
+DATA 4	0x021b483c 0x4201020C
+DATA 4	0x021b4840 0x01660172
+DATA 4	0x021b0848 0x4A4D4E4D
+DATA 4	0x021b4848 0x4A4F5049
+DATA 4	0x021b0850 0x3F3C3D31
+DATA 4	0x021b4850 0x3238372B
+DATA 4	0x021b081c 0x33333333
+DATA 4	0x021b0820 0x33333333
+DATA 4	0x021b0824 0x33333333
+DATA 4	0x021b0828 0x33333333
+DATA 4	0x021b481c 0x33333333
+DATA 4	0x021b4820 0x33333333
+DATA 4	0x021b4824 0x33333333
+DATA 4	0x021b4828 0x33333333
+DATA 4	0x021b08b8 0x00000800
+DATA 4	0x021b48b8 0x00000800
+DATA 4	0x021b0004 0x0002002D
+DATA 4	0x021b0008 0x00333030
+DATA 4	0x021b000c 0x3F435313
+DATA 4	0x021b0010 0xB66E8B63
+DATA 4	0x021b0014 0x01FF00DB
+DATA 4	0x021b0018 0x00001740
+DATA 4	0x021b001c 0x00008000
+DATA 4	0x021b002c 0x000026d2
+DATA 4	0x021b0030 0x00431023
+DATA 4	0x021b0040 0x00000027
+DATA 4	0x021b0000 0x831A0000
+DATA 4	0x021b001c 0x04008032
+DATA 4	0x021b001c 0x00008033
+DATA 4	0x021b001c 0x00048031
+DATA 4	0x021b001c 0x05208030
+DATA 4 0x021b001c 0x04008040
+DATA 4	0x021b0020 0x00005800
+DATA 4	0x021b0818 0x00011117
+DATA 4	0x021b4818 0x00011117
+DATA 4	0x021b0004 0x0002556D
+DATA 4	0x021b0404 0x00011006
+DATA 4	0x021b001c 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 80c8ebdafc..81dcd6e5dd 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -513,6 +513,13 @@ static int pfuze_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
+}
+#endif
+
 #ifdef CONFIG_CMD_BMODE
 static const struct boot_mode board_boot_modes[] = {
 	/* 4 bit bus width */
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index a990b4cea8..a0832f4a20 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -82,6 +82,11 @@ static iomux_v3_cfg_t ecspi1_pads[] = {
 	MX6_PAD_ECSPI1_SS0__GPIO4_IO11  | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
+}
+
 static void setup_spi(void)
 {
 	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
diff --git a/board/freescale/p1010rdb/MAINTAINERS b/board/freescale/p1010rdb/MAINTAINERS
index 579e775972..db001437b1 100644
--- a/board/freescale/p1010rdb/MAINTAINERS
+++ b/board/freescale/p1010rdb/MAINTAINERS
@@ -1,5 +1,5 @@
 P1010RDB BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/p1010rdb/
 F:	include/configs/P1010RDB.h
diff --git a/board/freescale/p1023rdb/MAINTAINERS b/board/freescale/p1023rdb/MAINTAINERS
index 81501aa5fc..c06bac6d0d 100644
--- a/board/freescale/p1023rdb/MAINTAINERS
+++ b/board/freescale/p1023rdb/MAINTAINERS
@@ -1,5 +1,5 @@
 P1023RDB BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/p1023rdb/
 F:	include/configs/P1023RDB.h
diff --git a/board/freescale/p1_p2_rdb/MAINTAINERS b/board/freescale/p1_p2_rdb/MAINTAINERS
index ad0a8589f4..aabf587dd6 100644
--- a/board/freescale/p1_p2_rdb/MAINTAINERS
+++ b/board/freescale/p1_p2_rdb/MAINTAINERS
@@ -1,5 +1,5 @@
 P1_P2_RDB BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/p1_p2_rdb/
 F:	include/configs/P1_P2_RDB.h
diff --git a/board/freescale/p1_p2_rdb_pc/MAINTAINERS b/board/freescale/p1_p2_rdb_pc/MAINTAINERS
index 4d429fe9cf..c2e924798e 100644
--- a/board/freescale/p1_p2_rdb_pc/MAINTAINERS
+++ b/board/freescale/p1_p2_rdb_pc/MAINTAINERS
@@ -1,5 +1,5 @@
 P1_P2_RDB_PC BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/p1_p2_rdb_pc/
 F:	include/configs/p1_p2_rdb_pc.h
diff --git a/board/freescale/p1_twr/MAINTAINERS b/board/freescale/p1_twr/MAINTAINERS
index 2d7d7e10c5..c19d43616b 100644
--- a/board/freescale/p1_twr/MAINTAINERS
+++ b/board/freescale/p1_twr/MAINTAINERS
@@ -1,5 +1,5 @@
 P1_TWR BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/p1_twr/
 F:	include/configs/p1_twr.h
diff --git a/board/freescale/p2020ds/MAINTAINERS b/board/freescale/p2020ds/MAINTAINERS
index 42cb18dc8b..cb61fc51fb 100644
--- a/board/freescale/p2020ds/MAINTAINERS
+++ b/board/freescale/p2020ds/MAINTAINERS
@@ -1,5 +1,5 @@
 P2020DS BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/p2020ds/
 F:	include/configs/P2020DS.h
diff --git a/board/freescale/p2041rdb/MAINTAINERS b/board/freescale/p2041rdb/MAINTAINERS
index bb5bb83f30..d93cb0bebb 100644
--- a/board/freescale/p2041rdb/MAINTAINERS
+++ b/board/freescale/p2041rdb/MAINTAINERS
@@ -1,5 +1,5 @@
 P2041RDB BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/p2041rdb/
 F:	include/configs/P2041RDB.h
diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
index 1929bba20b..06d908658d 100644
--- a/board/freescale/t1040qds/eth.c
+++ b/board/freescale/t1040qds/eth.c
@@ -241,6 +241,8 @@ static void initialize_lane_to_slot(void)
 		break;
 	case 0xA7:
 		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 6;
+		lane_to_slot[3] = 5;
 		lane_to_slot[7] = 7;
 		break;
 	case 0xAA:
@@ -410,6 +412,8 @@ void t1040_handle_phy_interface_sgmii(int i)
 			fm_info_set_phy_address(i, riser_phy_addr[1]);
 		if (FM1_DTSEC3 == i)
 			fm_info_set_phy_address(i, riser_phy_addr[2]);
+		if (FM1_DTSEC5 == i)
+			fm_info_set_phy_address(i, riser_phy_addr[3]);
 
 		mdio_mux[i] = EMI1_SLOT7;
 		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS
index 364b0a961e..b61e1c0254 100644
--- a/board/freescale/t104xrdb/MAINTAINERS
+++ b/board/freescale/t104xrdb/MAINTAINERS
@@ -6,12 +6,13 @@ F:	include/configs/T104xRDB.h
 F:	configs/T1040RDB_defconfig
 F:	configs/T1040RDB_NAND_defconfig
 F:	configs/T1040RDB_SPIFLASH_defconfig
+F:	configs/T1042RDB_defconfig
 F:	configs/T1042RDB_PI_defconfig
 F:	configs/T1042RDB_PI_NAND_defconfig
 F:	configs/T1042RDB_PI_SPIFLASH_defconfig
 
 T1040RDB_SDCARD BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	configs/T1040RDB_SDCARD_defconfig
 F:	configs/T1042RDB_PI_SDCARD_defconfig
diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README
index cdbe1fafd9..ac95b5e509 100644
--- a/board/freescale/t104xrdb/README
+++ b/board/freescale/t104xrdb/README
@@ -4,10 +4,23 @@ The T1040RDB is a Freescale reference board that hosts the T1040 SoC
 (and variants). Variants inclued T1042 presonality of T1040, in which
 case T1040RDB can also be called T1042RDB.
 
+The T1042RDB is a Freescale reference board that hosts the T1042 SoC
+(and variants). The board is similar to T1040RDB, T1040 is a reduced
+personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
+
 The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC.
 (a personality of T1040 SoC). The board is similar to T1040RDB but is
 designed specially with low power features targeted for Printing Image Market.
 
+Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB
+-------------------------------------------------------------------------
+Board		Si		Protocol		Targeted Market
+-------------------------------------------------------------------------
+T1040RDB	T1040		0x66                    Networking
+T1040RDB	T1042		0x86                    Networking
+T1042RDB_PI	T1042		0x06                    Printing & Imaging
+
+
 T1040 SoC Overview
 ------------------
 The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
@@ -194,10 +207,10 @@ The below commands apply to the board
    Commands for switching to alternate bank.
 
 	1. To change from vbank0 to vbank4
-		=> qixis_reset altbank (it will boot using vbank4)
+		=> cpld reset altbank (it will boot using vbank4)
 
 	2.To change from vbank4 to vbank0
-		=> qixis reset (it will boot using vbank0)
+		=> cpld reset (it will boot using vbank0)
 
 NAND boot with 2 Stage boot loader
 ----------------------------------
@@ -259,15 +272,15 @@ Switch Settings: (ON is 0, OFF is 1)
 ===============
 NAND boot SW setting:
 SW1: 10001000
-SW2: 00111001
+SW2: 00111011
 SW3: 11110001
 
 SPI boot SW setting:
 SW1: 00100010
-SW2: 10111001
+SW2: 10111011
 SW3: 11100001
 
 SD boot SW setting:
 SW1: 00100000
-SW2: 00111001
+SW2: 00111011
 SW3: 11100001
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index 34c9224adb..2c331eebf9 100644
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c
@@ -105,8 +105,8 @@ found:
 	popts->zq_en = 1;
 
 	/* DHC_EN =1, ODT = 75 Ohm */
-	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
-	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 }
 
 phys_size_t initdram(int board_type)
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index 63e5f900da..c8b6c672a6 100644
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -42,6 +42,16 @@ int board_eth_init(bd_t *bis)
 			fm_info_set_phy_address(FM1_DTSEC3,
 						CONFIG_SYS_SGMII1_PHY_ADDR);
 			break;
+#endif
+#ifdef CONFIG_T1042RDB
+		case PHY_INTERFACE_MODE_SGMII:
+			/* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
+			if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
+				fm_info_set_phy_address(i, 0);
+			/* T1042RDB only supports SGMII on DTSEC3 */
+			fm_info_set_phy_address(FM1_DTSEC3,
+						CONFIG_SYS_SGMII1_PHY_ADDR);
+			break;
 #endif
 		case PHY_INTERFACE_MODE_RGMII:
 			if (FM1_DTSEC4 == i)
diff --git a/board/freescale/t104xrdb/t1042_pi_rcw.cfg b/board/freescale/t104xrdb/t1042_pi_rcw.cfg
new file mode 100644
index 0000000000..57de89ad0e
--- /dev/null
+++ b/board/freescale/t104xrdb/t1042_pi_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x06
+0c18000e 0e000000 00000000 00000000
+06000002 00400002 e8106000 01000000
+00000000 00000000 00000000 00030810
+00000000 01fe0a06 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042_rcw.cfg b/board/freescale/t104xrdb/t1042_rcw.cfg
index a3ea8ada56..db4d52f397 100644
--- a/board/freescale/t104xrdb/t1042_rcw.cfg
+++ b/board/freescale/t104xrdb/t1042_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
-# serdes protocol 0x66
+# serdes protocol 0x86
 0c18000e 0e000000 00000000 00000000
-06000002 00400002 e8106000 01000000
-00000000 00000000 00000000 00030810
-00000000 01fe0a06 00000000 00000000
+86000002 80000002 ec027000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t208xqds/MAINTAINERS b/board/freescale/t208xqds/MAINTAINERS
index 643926f4b0..deda092a6a 100644
--- a/board/freescale/t208xqds/MAINTAINERS
+++ b/board/freescale/t208xqds/MAINTAINERS
@@ -1,5 +1,5 @@
 T208XQDS BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/t208xqds/
 F:	include/configs/T208xQDS.h
diff --git a/board/freescale/t208xrdb/MAINTAINERS b/board/freescale/t208xrdb/MAINTAINERS
index 598714356c..16428798cd 100644
--- a/board/freescale/t208xrdb/MAINTAINERS
+++ b/board/freescale/t208xrdb/MAINTAINERS
@@ -1,5 +1,5 @@
 T208XRDB BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/t208xrdb/
 F:	include/configs/T208xRDB.h
diff --git a/board/freescale/t4qds/MAINTAINERS b/board/freescale/t4qds/MAINTAINERS
index da796bd5b6..f88ee7df9e 100644
--- a/board/freescale/t4qds/MAINTAINERS
+++ b/board/freescale/t4qds/MAINTAINERS
@@ -1,5 +1,5 @@
 T4QDS BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/freescale/t4qds/
 F:	include/configs/T4240QDS.h
diff --git a/board/funkwerk/vovpn-gw/MAINTAINERS b/board/funkwerk/vovpn-gw/MAINTAINERS
index 9af5f7871b..34d1cc12ff 100644
--- a/board/funkwerk/vovpn-gw/MAINTAINERS
+++ b/board/funkwerk/vovpn-gw/MAINTAINERS
@@ -1,5 +1,5 @@
 VOVPN-GW BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/funkwerk/vovpn-gw/
 F:	include/configs/VoVPN-GW.h
diff --git a/board/gaisler/gr_cpci_ax2000/MAINTAINERS b/board/gaisler/gr_cpci_ax2000/MAINTAINERS
index 493c31ecab..df55a4cc41 100644
--- a/board/gaisler/gr_cpci_ax2000/MAINTAINERS
+++ b/board/gaisler/gr_cpci_ax2000/MAINTAINERS
@@ -1,5 +1,5 @@
 GR_CPCI_AX2000 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/gaisler/gr_cpci_ax2000/
 F:	include/configs/gr_cpci_ax2000.h
diff --git a/board/gaisler/gr_ep2s60/MAINTAINERS b/board/gaisler/gr_ep2s60/MAINTAINERS
index 151bef1329..7acd5f44c6 100644
--- a/board/gaisler/gr_ep2s60/MAINTAINERS
+++ b/board/gaisler/gr_ep2s60/MAINTAINERS
@@ -1,5 +1,5 @@
 GR_EP2S60 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/gaisler/gr_ep2s60/
 F:	include/configs/gr_ep2s60.h
diff --git a/board/gaisler/gr_xc3s_1500/MAINTAINERS b/board/gaisler/gr_xc3s_1500/MAINTAINERS
index 187f32334d..c4179d29c0 100644
--- a/board/gaisler/gr_xc3s_1500/MAINTAINERS
+++ b/board/gaisler/gr_xc3s_1500/MAINTAINERS
@@ -1,5 +1,5 @@
 GR_XC3S_1500 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/gaisler/gr_xc3s_1500/
 F:	include/configs/gr_xc3s_1500.h
diff --git a/board/gaisler/grsim/MAINTAINERS b/board/gaisler/grsim/MAINTAINERS
index acb863c2f7..4b3312ef72 100644
--- a/board/gaisler/grsim/MAINTAINERS
+++ b/board/gaisler/grsim/MAINTAINERS
@@ -1,5 +1,5 @@
 GRSIM BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/gaisler/grsim/
 F:	include/configs/grsim.h
diff --git a/board/gaisler/grsim_leon2/MAINTAINERS b/board/gaisler/grsim_leon2/MAINTAINERS
index 6da9b784cf..bf4a95001b 100644
--- a/board/gaisler/grsim_leon2/MAINTAINERS
+++ b/board/gaisler/grsim_leon2/MAINTAINERS
@@ -1,5 +1,5 @@
 GRSIM_LEON2 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/gaisler/grsim_leon2/
 F:	include/configs/grsim_leon2.h
diff --git a/board/galaxy5200/MAINTAINERS b/board/galaxy5200/MAINTAINERS
index f070132f37..614625d33f 100644
--- a/board/galaxy5200/MAINTAINERS
+++ b/board/galaxy5200/MAINTAINERS
@@ -1,5 +1,5 @@
 GALAXY5200 BOARD
-M:	Eric Millbrandt <emillbrandt@dekaresearch.com>
+#M:	Eric Millbrandt <emillbrandt@dekaresearch.com>
 S:	Orphan (since 2014-06)
 F:	board/galaxy5200/
 F:	include/configs/galaxy5200.h
diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c
index 3edc9151d9..ab3bab847a 100644
--- a/board/gateworks/gw_ventana/eeprom.c
+++ b/board/gateworks/gw_ventana/eeprom.c
@@ -80,6 +80,9 @@ read_eeprom(int bus, struct ventana_board_info *info)
 	case '4':
 		type = GW54xx;
 		break;
+	case '5':
+		type = GW552x;
+		break;
 	default:
 		printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
 		type = GW_UNKNOWN;
diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
index 1cf38d4046..a34a9a84c8 100644
--- a/board/gateworks/gw_ventana/gsc.c
+++ b/board/gateworks/gw_ventana/gsc.c
@@ -117,6 +117,10 @@ int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		read_hwmon("VDD_SOC",  GSC_HWMON_VDD_SOC, 3, MINMAX(1375, 10));
 		read_hwmon("VDD_1P0",  GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10));
 		break;
+	case '5': /* GW55xx */
+		read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
+		read_hwmon("VDD_SOC",  GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
+		break;
 	}
 	return 0;
 }
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index a222921978..1038d9d975 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -31,6 +31,7 @@
 #include <mmc.h>
 #include <mtd_node.h>
 #include <netdev.h>
+#include <pci.h>
 #include <power/pmic.h>
 #include <power/ltc3676_pmic.h>
 #include <power/pfuze100_pmic.h>
@@ -299,6 +300,7 @@ int board_ehci_hcd_init(int port)
 	/* Reset USB HUB (present on GW54xx/GW53xx) */
 	switch (info->model[3]) {
 	case '3': /* GW53xx */
+	case '5': /* GW552x */
 		SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
 		gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
 		mdelay(2);
@@ -354,9 +356,14 @@ iomux_v3_cfg_t const ecspi1_pads[] = {
 	IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 };
 
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
+}
+
 static void setup_spi(void)
 {
-	gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
+	gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
 	SETUP_IOMUX_PADS(ecspi1_pads);
 }
 #endif
@@ -392,7 +399,8 @@ int board_eth_init(bd_t *bis)
 	setup_iomux_enet();
 
 #ifdef CONFIG_FEC_MXC
-	cpu_eth_init(bis);
+	if (board_type != GW552x)
+		cpu_eth_init(bis);
 #endif
 
 #ifdef CONFIG_CI_UDC
@@ -614,15 +622,14 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
 	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 	/* PANLEDR# */
 	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+	/* MX6_LOCLED# */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 	/* IOEXP_PWREN# */
 	IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 	/* IOEXP_IRQ# */
 	IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 	/* DIOI2C_DIS# */
 	IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
-
-	/* MX6_LOCLED# */
-	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 	/* GPS_SHDN */
 	IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 	/* VID_EN */
@@ -660,6 +667,30 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
 	IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
 };
 
+static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
+	/* PANLEDG# */
+	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+	/* PANLEDR# */
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+	/* MX6_LOCLED# */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* PCI_RST# */
+	IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
+	/* MX6_DIO[4:9] */
+	IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
+	IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
+	IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG),
+	IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG),
+	IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG),
+	IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG),
+	/* PCIEGBE1_OFF# */
+	IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
+	/* PCIEGBE2_OFF# */
+	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
+	/* PCIESKT_WDIS# */
+	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+};
+
 /*
  * each baseboard has 4 user configurable Digital IO lines which can
  * be pinmuxed as a GPIO or in some cases a PWM
@@ -908,6 +939,44 @@ struct ventana gpio_cfg[] = {
 		.pcie_sson = IMX_GPIO_NR(1, 20),
 		.wdis = IMX_GPIO_NR(5, 17),
 	},
+
+	/* GW552x */
+	{
+		.gpio_pads = gw552x_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
+		.dio_cfg = {
+			{
+				{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+				IMX_GPIO_NR(1, 16),
+				{ 0, 0 },
+				0
+			},
+			{
+				{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+				IMX_GPIO_NR(1, 19),
+				{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+				2
+			},
+			{
+				{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+				IMX_GPIO_NR(1, 17),
+				{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+				3
+			},
+			{
+				{ IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+				IMX_GPIO_NR(2, 10),
+				{ 0, 0 },
+				0
+			},
+		},
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 7),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 29),
+	},
 };
 
 /* setup board specific PMIC */
@@ -997,14 +1066,16 @@ static void setup_board_gpio(int board)
 #endif
 
 	/* turn off (active-high) user LED's */
-	for (i = 0; i < 4; i++) {
+	for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) {
 		if (gpio_cfg[board].leds[i])
 			gpio_direction_output(gpio_cfg[board].leds[i], 1);
 	}
 
 	/* Expansion Mezzanine IO */
-	gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
-	gpio_direction_input(gpio_cfg[board].mezz_irq);
+	if (gpio_cfg[board].mezz_pwren)
+		gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
+	if (gpio_cfg[board].mezz_irq)
+		gpio_direction_input(gpio_cfg[board].mezz_irq);
 
 	/* RS485 Transmit Enable */
 	if (gpio_cfg[board].rs485en)
@@ -1092,6 +1163,35 @@ int imx6_pcie_toggle_reset(void)
 	}
 	return 0;
 }
+
+/*
+ * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
+ * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
+ * properly and assert reset for 100ms.
+ */
+void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
+			 unsigned short vendor, unsigned short device,
+			 unsigned short class)
+{
+	u32 dw;
+
+	debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
+	      PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
+	if (vendor == PCI_VENDOR_ID_PLX &&
+	    (device & 0xfff0) == 0x8600 &&
+	    PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
+		debug("configuring PLX 860X downstream PERST#\n");
+		pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
+		dw |= 0xaaa8; /* GPIO1-7 outputs */
+		pci_hose_write_config_dword(hose, dev, 0x62c, dw);
+
+		pci_hose_read_config_dword(hose, dev, 0x644, &dw);
+		dw |= 0xfe;   /* GPIO1-7 output high */
+		pci_hose_write_config_dword(hose, dev, 0x644, dw);
+
+		mdelay(100);
+	}
+}
 #endif /* CONFIG_CMD_PCI */
 
 #ifdef CONFIG_SERIAL_TAG
@@ -1283,6 +1383,7 @@ int misc_init_r(void)
 		else if (is_cpu_type(MXC_CPU_MX6DL) ||
 			 is_cpu_type(MXC_CPU_MX6SOLO))
 			cputype = "imx6dl";
+		setenv("soctype", cputype);
 		if (8 << (ventana_info.nand_flash_size-1) >= 2048)
 			setenv("flash_layout", "large");
 		else
@@ -1305,7 +1406,8 @@ int misc_init_r(void)
 				sprintf(fdt, "%s-%s.dtb", cputype, str);
 				setenv("fdt_file1", fdt);
 			}
-			str[4] = 'x';
+			if (board_type != GW552x)
+				str[4] = 'x';
 			str[5] = 'x';
 			str[6] = 0;
 			if (!getenv("fdt_file2")) {
@@ -1341,10 +1443,11 @@ int misc_init_r(void)
 	 *  The Gateworks System Controller implements a boot
 	 *  watchdog (always enabled) as a workaround for IMX6 boot related
 	 *  errata such as:
-	 *    ERR005768 - no fix
-	 *    ERR006282 - fixed in silicon r1.3
+	 *    ERR005768 - no fix scheduled
+	 *    ERR006282 - fixed in silicon r1.2
 	 *    ERR007117 - fixed in silicon r1.3
 	 *    ERR007220 - fixed in silicon r1.3
+	 *    ERR007926 - no fix scheduled
 	 *  see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
 	 *
 	 * Disable the boot watchdog and display/clear the timeout flag if set
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index e943879303..9fc253bb82 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -201,55 +201,79 @@ static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
 	.trasmin = 3500,
 };
 
-/* GW54xx specific calibration */
-static struct mx6_mmdc_calibration gw54xxq_mmdc_calib = {
-	/* write leveling calibration determine */
-	.p0_mpwldectrl0 = 0x00190018,
-	.p0_mpwldectrl1 = 0x0021001D,
-	.p1_mpwldectrl0 = 0x00160027,
-	.p1_mpwldectrl1 = 0x0012001E,
-	/* Read DQS Gating calibration */
-	.p0_mpdgctrl0 = 0x43370346,
-	.p0_mpdgctrl1 = 0x032A0321,
-	.p1_mpdgctrl0 = 0x433A034D,
-	.p1_mpdgctrl1 = 0x032F0235,
-	/* Read Calibration: DQS delay relative to DQ read access */
-	.p0_mprddlctl = 0x3C313539,
-	.p1_mprddlctl = 0x37333140,
-	/* Write Calibration: DQ/DM delay relative to DQS write access */
-	.p0_mpwrdlctl = 0x37393C38,
-	.p1_mpwrdlctl = 0x42334538,
+/* MT41K256M16HA-125 */
+static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
 };
 
-/* GW53xx specific calibration */
-static struct mx6_mmdc_calibration gw53xxq_mmdc_calib = {
+/*
+ * calibration - these are the various CPU/DDR3 combinations we support
+ */
+
+static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
 	/* write leveling calibration determine */
-	.p0_mpwldectrl0 = 0x00160013,
-	.p0_mpwldectrl1 = 0x00090024,
-	.p1_mpwldectrl0 = 0x001F0018,
-	.p1_mpwldectrl1 = 0x000C001C,
+	.p0_mpwldectrl0 = 0x00190017,
+	.p0_mpwldectrl1 = 0x00140026,
 	/* Read DQS Gating calibration */
-	.p0_mpdgctrl0 = 0x433A034C,
-	.p0_mpdgctrl1 = 0x0336032F,
-	.p1_mpdgctrl0 = 0x4343034A,
-	.p1_mpdgctrl1 = 0x03370222,
+	.p0_mpdgctrl0 = 0x43380347,
+	.p0_mpdgctrl1 = 0x433C034D,
 	/* Read Calibration: DQS delay relative to DQ read access */
-	.p0_mprddlctl = 0x3F343638,
-	.p1_mprddlctl = 0x38373442,
+	.p0_mprddlctl = 0x3C313539,
 	/* Write Calibration: DQ/DM delay relative to DQS write access */
-	.p0_mpwrdlctl = 0x343A3E39,
-	.p1_mpwrdlctl = 0x44344239,
+	.p0_mpwrdlctl = 0x36393C39,
 };
-static struct mx6_mmdc_calibration gw53xxdl_mmdc_calib = {
+
+static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
 	/* write leveling calibration determine */
 	.p0_mpwldectrl0 = 0x003C003C,
-	.p0_mpwldectrl1 = 0x00330038,
-	.p1_mpwldectrl0 = 0x001F002A,
+	.p0_mpwldectrl1 = 0x001F002A,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x42410244,
+	.p0_mpdgctrl1 = 0x4234023A,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0x484A4C4B,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0x33342B32,
+};
+
+static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x00190017,
+	.p0_mpwldectrl1 = 0x00140026,
+	.p1_mpwldectrl0 = 0x0021001C,
+	.p1_mpwldectrl1 = 0x0011001D,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x43380347,
+	.p0_mpdgctrl1 = 0x433C034D,
+	.p1_mpdgctrl0 = 0x032C0324,
+	.p1_mpdgctrl1 = 0x03310232,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0x3C313539,
+	.p1_mprddlctl = 0x37343141,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0x36393C39,
+	.p1_mpwrdlctl = 0x42344438,
+};
+
+static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x003C003C,
+	.p0_mpwldectrl1 = 0x001F002A,
+	.p1_mpwldectrl0 = 0x00330038,
 	.p1_mpwldectrl1 = 0x0022003F,
 	/* Read DQS Gating calibration */
 	.p0_mpdgctrl0 = 0x42410244,
-	.p0_mpdgctrl1 = 0x022D022D,
-	.p1_mpdgctrl0 = 0x4234023A,
+	.p0_mpdgctrl1 = 0x4234023A,
+	.p1_mpdgctrl0 = 0x022D022D,
 	.p1_mpdgctrl1 = 0x021C0228,
 	/* Read Calibration: DQS delay relative to DQ read access */
 	.p0_mprddlctl = 0x484A4C4B,
@@ -259,51 +283,42 @@ static struct mx6_mmdc_calibration gw53xxdl_mmdc_calib = {
 	.p1_mpwrdlctl = 0x3933332B,
 };
 
-/* GW52xx specific calibration */
-static struct mx6_mmdc_calibration gw52xxdl_mmdc_calib = {
+static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
 	/* write leveling calibration determine */
-	.p0_mpwldectrl0 = 0x0040003F,
-	.p0_mpwldectrl1 = 0x00370037,
+	.p0_mpwldectrl0 = 0x001E001A,
+	.p0_mpwldectrl1 = 0x0026001F,
 	/* Read DQS Gating calibration */
-	.p0_mpdgctrl0 = 0x42420244,
-	.p0_mpdgctrl1 = 0x022F022F,
+	.p0_mpdgctrl0 = 0x43370349,
+	.p0_mpdgctrl1 = 0x032D0327,
 	/* Read Calibration: DQS delay relative to DQ read access */
-	.p0_mprddlctl = 0x49464B4A,
+	.p0_mprddlctl = 0x3D303639,
 	/* Write Calibration: DQ/DM delay relative to DQS write access */
-	.p0_mpwrdlctl = 0x32362C32,
+	.p0_mpwrdlctl = 0x32363934,
 };
 
-/* GW51xx specific calibration */
-static struct mx6_mmdc_calibration gw51xxq_mmdc_calib = {
+static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
 	/* write leveling calibration determine */
-	.p0_mpwldectrl0 = 0x00150016,
-	.p0_mpwldectrl1 = 0x001F0017,
+	.p0_mpwldectrl0 = 0X00220021,
+	.p0_mpwldectrl1 = 0X00200030,
+	.p1_mpwldectrl0 = 0X002D0027,
+	.p1_mpwldectrl1 = 0X00150026,
 	/* Read DQS Gating calibration */
-	.p0_mpdgctrl0 = 0x433D034D,
-	.p0_mpdgctrl1 = 0x033D032F,
+	.p0_mpdgctrl0 = 0x43330342,
+	.p0_mpdgctrl1 = 0x0339034A,
+	.p1_mpdgctrl0 = 0x032F0325,
+	.p1_mpdgctrl1 = 0x032F022E,
 	/* Read Calibration: DQS delay relative to DQ read access */
-	.p0_mprddlctl = 0x3F313639,
+	.p0_mprddlctl = 0X3A2E3437,
+	.p1_mprddlctl = 0X35312F3F,
 	/* Write Calibration: DQ/DM delay relative to DQS write access */
-	.p0_mpwrdlctl = 0x33393F36,
+	.p0_mpwrdlctl = 0X33363B37,
+	.p1_mpwrdlctl = 0X40304239,
 };
 
-static struct mx6_mmdc_calibration gw51xxdl_mmdc_calib = {
-	/* write leveling calibration determine */
-	.p0_mpwldectrl0 = 0x003D003F,
-	.p0_mpwldectrl1 = 0x002F0038,
-	/* Read DQS Gating calibration */
-	.p0_mpdgctrl0 = 0x423A023A,
-	.p0_mpdgctrl1 = 0x022A0228,
-	/* Read Calibration: DQS delay relative to DQ read access */
-	.p0_mprddlctl = 0x48494C4C,
-	/* Write Calibration: DQ/DM delay relative to DQS write access */
-	.p0_mpwrdlctl = 0x34352D31,
-};
-
-static void spl_dram_init(int width, int size, int board_model)
+static void spl_dram_init(int width, int size_mb, int board_model)
 {
-	struct mx6_ddr3_cfg *mem = &mt41k128m16jt_125;
-	struct mx6_mmdc_calibration *calib;
+	struct mx6_ddr3_cfg *mem = NULL;
+	struct mx6_mmdc_calibration *calib = NULL;
 	struct mx6_ddr_sysinfo sysinfo = {
 		/* width of data bus:0=16,1=32,2=64 */
 		.dsize = width/32,
@@ -329,29 +344,43 @@ static void spl_dram_init(int width, int size, int board_model)
 	/*
 	 * MMDC Calibration requires the following data:
 	 *   mx6_mmdc_calibration - board-specific calibration (routing delays)
+	 *      these calibration values depend on board routing, SoC, and DDR
 	 *   mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
 	 *   mx6_ddr_cfg - chip specific timing/layout details
 	 */
-	switch (board_model) {
-	default:
-	case GW51xx:
+	if (width == 32 && size_mb == 512) {
+		mem = &mt41k128m16jt_125;
 		if (is_cpu_type(MXC_CPU_MX6Q))
-			calib = &gw51xxq_mmdc_calib;
+			calib = &mx6dq_128x32_mmdc_calib;
 		else
-			calib = &gw51xxdl_mmdc_calib;
-		break;
-	case GW52xx:
-		calib = &gw52xxdl_mmdc_calib;
-		break;
-	case GW53xx:
+			calib = &mx6sdl_128x32_mmdc_calib;
+		debug("2gB density\n");
+	} else if (width == 64 && size_mb == 1024) {
+		mem = &mt41k128m16jt_125;
 		if (is_cpu_type(MXC_CPU_MX6Q))
-			calib = &gw53xxq_mmdc_calib;
+			calib = &mx6dq_128x64_mmdc_calib;
 		else
-			calib = &gw53xxdl_mmdc_calib;
-		break;
-	case GW54xx:
-		calib = &gw54xxq_mmdc_calib;
-		break;
+			calib = &mx6sdl_128x64_mmdc_calib;
+		debug("2gB density\n");
+	} else if (width == 32 && size_mb == 1024) {
+		mem = &mt41k256m16ha_125;
+		if (is_cpu_type(MXC_CPU_MX6Q))
+			calib = &mx6dq_256x32_mmdc_calib;
+		debug("4gB density\n");
+	} else if (width == 64 && size_mb == 2048) {
+		mem = &mt41k256m16ha_125;
+		if (is_cpu_type(MXC_CPU_MX6Q))
+			calib = &mx6dq_256x64_mmdc_calib;
+		debug("4gB density\n");
+	}
+
+	if (!mem) {
+		puts("Error: Invalid Memory Configuration\n");
+		hang();
+	}
+	if (!calib) {
+		puts("Error: Invalid Board Calibration Configuration\n");
+		hang();
 	}
 
 	if (is_cpu_type(MXC_CPU_MX6Q))
diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h
index d64b9107c6..af12711ac2 100644
--- a/board/gateworks/gw_ventana/ventana_eeprom.h
+++ b/board/gateworks/gw_ventana/ventana_eeprom.h
@@ -109,6 +109,7 @@ enum {
 	GW52xx,
 	GW53xx,
 	GW54xx,
+	GW552x,
 	GW_UNKNOWN,
 	GW_BADCRC,
 };
diff --git a/board/genesi/mx51_efikamx/MAINTAINERS b/board/genesi/mx51_efikamx/MAINTAINERS
index a85df77982..f1398c4926 100644
--- a/board/genesi/mx51_efikamx/MAINTAINERS
+++ b/board/genesi/mx51_efikamx/MAINTAINERS
@@ -1,5 +1,5 @@
 MX51_EFIKAMX BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/genesi/mx51_efikamx/
 F:	include/configs/mx51_efikamx.h
diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c
index 16769e5332..137e4ed661 100644
--- a/board/genesi/mx51_efikamx/efikamx.c
+++ b/board/genesi/mx51_efikamx/efikamx.c
@@ -152,6 +152,11 @@ static iomux_v3_cfg_t const efikamx_spi_pads[] = {
  * PMIC configuration
  */
 #ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 1) ? 121 : -1;
+}
+
 static void power_init(void)
 {
 	unsigned int val;
diff --git a/board/icecube/MAINTAINERS b/board/icecube/MAINTAINERS
index 02e6c049d4..8a24eb4699 100644
--- a/board/icecube/MAINTAINERS
+++ b/board/icecube/MAINTAINERS
@@ -6,7 +6,7 @@ F:	include/configs/IceCube.h
 F:	configs/icecube_5200_defconfig
 
 ICECUBE_5200_DDR BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	configs/icecube_5200_DDR_defconfig
 F:	configs/icecube_5200_DDR_LOWBOOT_defconfig
diff --git a/board/imx31_phycore/MAINTAINERS b/board/imx31_phycore/MAINTAINERS
index efd5e77c81..41f6cae81b 100644
--- a/board/imx31_phycore/MAINTAINERS
+++ b/board/imx31_phycore/MAINTAINERS
@@ -1,11 +1,11 @@
 IMX31_PHYCORE BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/imx31_phycore/
 F:	include/configs/imx31_phycore.h
 F:	configs/imx31_phycore_defconfig
 
 IMX31_PHYCORE_EET BOARD
-M:	(resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+#M:	(resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 S:	Orphan (since 2013-09)
 F:	configs/imx31_phycore_eet_defconfig
diff --git a/board/ip04/MAINTAINERS b/board/ip04/MAINTAINERS
index 278072bcd9..c37b0110f2 100644
--- a/board/ip04/MAINTAINERS
+++ b/board/ip04/MAINTAINERS
@@ -1,5 +1,5 @@
 IP04 BOARD
-M:	Brent Kandetzki <brentk@teleco.com>
+#M:	Brent Kandetzki <brentk@teleco.com>
 S:	Orphan (since 2014-06)
 F:	board/ip04/
 F:	include/configs/ip04.h
diff --git a/board/isee/igep00x0/MAINTAINERS b/board/isee/igep00x0/MAINTAINERS
index fe4a8cd445..3fc2c6cb9a 100644
--- a/board/isee/igep00x0/MAINTAINERS
+++ b/board/isee/igep00x0/MAINTAINERS
@@ -8,7 +8,7 @@ F:	configs/igep0030_defconfig
 F:	configs/igep0032_defconfig
 
 IGEP0020_NAND BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	configs/igep0020_nand_defconfig
 F:	configs/igep0030_nand_defconfig
diff --git a/board/ivm/u-boot.lds b/board/ivm/u-boot.lds
deleted file mode 100644
index 3d4fc8a2f5..0000000000
--- a/board/ivm/u-boot.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/karo/tk71/MAINTAINERS b/board/karo/tk71/MAINTAINERS
index 39b2b1db35..ac85d6b44c 100644
--- a/board/karo/tk71/MAINTAINERS
+++ b/board/karo/tk71/MAINTAINERS
@@ -1,5 +1,5 @@
 TK71 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/karo/tk71/
 F:	include/configs/tk71.h
diff --git a/board/kup/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds
deleted file mode 100644
index 0eb2fba00c..0000000000
--- a/board/kup/kup4k/u-boot.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/logicpd/imx31_litekit/MAINTAINERS b/board/logicpd/imx31_litekit/MAINTAINERS
index 98cc7bd15c..8e3608e0af 100644
--- a/board/logicpd/imx31_litekit/MAINTAINERS
+++ b/board/logicpd/imx31_litekit/MAINTAINERS
@@ -1,5 +1,5 @@
 IMX31_LITEKIT BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/logicpd/imx31_litekit/
 F:	include/configs/imx31_litekit.h
diff --git a/board/lwmon/u-boot.lds b/board/lwmon/u-boot.lds
deleted file mode 100644
index 90e2e2ed0c..0000000000
--- a/board/lwmon/u-boot.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2001-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/manroland/hmi1001/MAINTAINERS b/board/manroland/hmi1001/MAINTAINERS
index bdfdc01861..a66a98178c 100644
--- a/board/manroland/hmi1001/MAINTAINERS
+++ b/board/manroland/hmi1001/MAINTAINERS
@@ -1,5 +1,5 @@
 HMI1001 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/manroland/hmi1001/
 F:	include/configs/hmi1001.h
diff --git a/board/manroland/uc100/u-boot.lds b/board/manroland/uc100/u-boot.lds
deleted file mode 100644
index 47f2de8e64..0000000000
--- a/board/manroland/uc100/u-boot.lds
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/matrix_vision/mergerbox/MAINTAINERS b/board/matrix_vision/mergerbox/MAINTAINERS
index 22be98186b..20bd073b90 100644
--- a/board/matrix_vision/mergerbox/MAINTAINERS
+++ b/board/matrix_vision/mergerbox/MAINTAINERS
@@ -1,5 +1,5 @@
 MERGERBOX BOARD
-M:	Andre Schwarz <andre.schwarz@matrix-vision.de>
+#M:	Andre Schwarz <andre.schwarz@matrix-vision.de>
 S:	Orphan (since 2014-03)
 F:	board/matrix_vision/mergerbox/
 F:	include/configs/MERGERBOX.h
diff --git a/board/matrix_vision/mvbc_p/MAINTAINERS b/board/matrix_vision/mvbc_p/MAINTAINERS
index 9e76b579fc..aad14ed079 100644
--- a/board/matrix_vision/mvbc_p/MAINTAINERS
+++ b/board/matrix_vision/mvbc_p/MAINTAINERS
@@ -1,5 +1,5 @@
 MVBC_P BOARD
-M:	Andre Schwarz <andre.schwarz@matrix-vision.de>
+#M:	Andre Schwarz <andre.schwarz@matrix-vision.de>
 S:	Orphan (since 2014-03)
 F:	board/matrix_vision/mvbc_p/
 F:	include/configs/MVBC_P.h
diff --git a/board/matrix_vision/mvblm7/MAINTAINERS b/board/matrix_vision/mvblm7/MAINTAINERS
index 4f7ca503fc..947a14ed50 100644
--- a/board/matrix_vision/mvblm7/MAINTAINERS
+++ b/board/matrix_vision/mvblm7/MAINTAINERS
@@ -1,5 +1,5 @@
 MVBLM7 BOARD
-M:	Andre Schwarz <andre.schwarz@matrix-vision.de>
+#M:	Andre Schwarz <andre.schwarz@matrix-vision.de>
 S:	Orphan (since 2014-03)
 F:	board/matrix_vision/mvblm7/
 F:	include/configs/MVBLM7.h
diff --git a/board/matrix_vision/mvsmr/MAINTAINERS b/board/matrix_vision/mvsmr/MAINTAINERS
index 9659730fb4..ae3cf9c0b2 100644
--- a/board/matrix_vision/mvsmr/MAINTAINERS
+++ b/board/matrix_vision/mvsmr/MAINTAINERS
@@ -1,5 +1,5 @@
 MVSMR BOARD
-M:	Andre Schwarz <andre.schwarz@matrix-vision.de>
+#M:	Andre Schwarz <andre.schwarz@matrix-vision.de>
 S:	Orphan (since 2014-03)
 F:	board/matrix_vision/mvsmr/
 F:	include/configs/MVSMR.h
diff --git a/board/mcc200/MAINTAINERS b/board/mcc200/MAINTAINERS
index 3d02bc64bf..a59a498795 100644
--- a/board/mcc200/MAINTAINERS
+++ b/board/mcc200/MAINTAINERS
@@ -1,5 +1,5 @@
 MCC200 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/mcc200/
 F:	include/configs/mcc200.h
diff --git a/board/micronas/vct/MAINTAINERS b/board/micronas/vct/MAINTAINERS
index 4b825d3285..cbaa585134 100644
--- a/board/micronas/vct/MAINTAINERS
+++ b/board/micronas/vct/MAINTAINERS
@@ -1,5 +1,5 @@
 VCT BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/micronas/vct/
 F:	include/configs/vct.h
diff --git a/board/motionpro/MAINTAINERS b/board/motionpro/MAINTAINERS
index 10a97cc4eb..2f8b5cb580 100644
--- a/board/motionpro/MAINTAINERS
+++ b/board/motionpro/MAINTAINERS
@@ -1,5 +1,5 @@
 MOTIONPRO BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/motionpro/
 F:	include/configs/motionpro.h
diff --git a/board/mpl/pati/MAINTAINERS b/board/mpl/pati/MAINTAINERS
index f7c1bd800b..19ad05d274 100644
--- a/board/mpl/pati/MAINTAINERS
+++ b/board/mpl/pati/MAINTAINERS
@@ -1,5 +1,5 @@
 PATI BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/mpl/pati/
 F:	include/configs/PATI.h
diff --git a/board/munices/MAINTAINERS b/board/munices/MAINTAINERS
index b8f57614bb..50d3e7ebda 100644
--- a/board/munices/MAINTAINERS
+++ b/board/munices/MAINTAINERS
@@ -1,5 +1,5 @@
 MUNICES BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/munices/
 F:	include/configs/munices.h
diff --git a/board/musenki/MAINTAINERS b/board/musenki/MAINTAINERS
index 03a1fe7f04..4196c805cb 100644
--- a/board/musenki/MAINTAINERS
+++ b/board/musenki/MAINTAINERS
@@ -1,5 +1,5 @@
 MUSENKI BOARD
-M:	Jim Thompson <jim@musenki.com>
+#M:	Jim Thompson <jim@musenki.com>
 S:	Orphan (since 2014-04)
 F:	board/musenki/
 F:	include/configs/MUSENKI.h
diff --git a/board/mvblue/MAINTAINERS b/board/mvblue/MAINTAINERS
index a809ba5a5c..5955f1a387 100644
--- a/board/mvblue/MAINTAINERS
+++ b/board/mvblue/MAINTAINERS
@@ -1,5 +1,5 @@
 MVBLUE BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/mvblue/
 F:	include/configs/MVBLUE.h
diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds
deleted file mode 100644
index 0dff5a4023..0000000000
--- a/board/netvia/u-boot.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text	:
-  {
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/palmtreo680/MAINTAINERS b/board/palmtreo680/MAINTAINERS
index bdc034ed79..b0ff9d0283 100644
--- a/board/palmtreo680/MAINTAINERS
+++ b/board/palmtreo680/MAINTAINERS
@@ -1,5 +1,5 @@
 PALMTREO680 BOARD
-M:	Mike Dunn <mikedunn@newsguy.com>
+#M:	Mike Dunn <mikedunn@newsguy.com>
 S:	Orphan (since 2014-06)
 F:	board/palmtreo680/
 F:	include/configs/palmtreo680.h
diff --git a/board/pb1x00/MAINTAINERS b/board/pb1x00/MAINTAINERS
index 6c5c2bb364..8326cc78cc 100644
--- a/board/pb1x00/MAINTAINERS
+++ b/board/pb1x00/MAINTAINERS
@@ -1,5 +1,5 @@
 PB1X00 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/pb1x00/
 F:	include/configs/pb1x00.h
diff --git a/board/pm828/MAINTAINERS b/board/pm828/MAINTAINERS
index 767a84da7a..97c1ccc595 100644
--- a/board/pm828/MAINTAINERS
+++ b/board/pm828/MAINTAINERS
@@ -1,5 +1,5 @@
 PM828 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/pm828/
 F:	include/configs/PM828.h
diff --git a/board/ppmc7xx/MAINTAINERS b/board/ppmc7xx/MAINTAINERS
index 5b21aa7042..a0c1f44e00 100644
--- a/board/ppmc7xx/MAINTAINERS
+++ b/board/ppmc7xx/MAINTAINERS
@@ -1,5 +1,5 @@
 PPMC7XX BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/ppmc7xx/
 F:	include/configs/ppmc7xx.h
diff --git a/board/ppmc8260/MAINTAINERS b/board/ppmc8260/MAINTAINERS
index 768d0921a7..8b896af2c4 100644
--- a/board/ppmc8260/MAINTAINERS
+++ b/board/ppmc8260/MAINTAINERS
@@ -1,5 +1,5 @@
 PPMC8260 BOARD
-M:	Brad Kemp <Brad.Kemp@seranoa.com>
+#M:	Brad Kemp <Brad.Kemp@seranoa.com>
 S:	Orphan (since 2014-04)
 F:	board/ppmc8260/
 F:	include/configs/ppmc8260.h
diff --git a/board/qemu-mips/MAINTAINERS b/board/qemu-mips/MAINTAINERS
index 079949a92a..334f9d8ee9 100644
--- a/board/qemu-mips/MAINTAINERS
+++ b/board/qemu-mips/MAINTAINERS
@@ -6,7 +6,7 @@ F:	include/configs/qemu-mips.h
 F:	configs/qemu_mips_defconfig
 
 QEMU_MIPSEL BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	configs/qemu_mipsel_defconfig
 F:	include/configs/qemu-mips64.h
diff --git a/board/renesas/MigoR/MAINTAINERS b/board/renesas/MigoR/MAINTAINERS
index 9368b0525e..21ee5e2754 100644
--- a/board/renesas/MigoR/MAINTAINERS
+++ b/board/renesas/MigoR/MAINTAINERS
@@ -1,5 +1,5 @@
 MIGOR BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/renesas/MigoR/
 F:	include/configs/MigoR.h
diff --git a/board/renesas/rsk7269/MAINTAINERS b/board/renesas/rsk7269/MAINTAINERS
index d3c77c3c14..698fbdb1df 100644
--- a/board/renesas/rsk7269/MAINTAINERS
+++ b/board/renesas/rsk7269/MAINTAINERS
@@ -1,5 +1,5 @@
 RSK7269 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/renesas/rsk7269/
 F:	include/configs/rsk7269.h
diff --git a/board/renesas/sh7752evb/MAINTAINERS b/board/renesas/sh7752evb/MAINTAINERS
index 8910669002..9840477d7d 100644
--- a/board/renesas/sh7752evb/MAINTAINERS
+++ b/board/renesas/sh7752evb/MAINTAINERS
@@ -1,5 +1,5 @@
 SH7752EVB BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/renesas/sh7752evb/
 F:	include/configs/sh7752evb.h
diff --git a/board/renesas/sh7753evb/MAINTAINERS b/board/renesas/sh7753evb/MAINTAINERS
index 03e6c8cdc4..b6c85eedab 100644
--- a/board/renesas/sh7753evb/MAINTAINERS
+++ b/board/renesas/sh7753evb/MAINTAINERS
@@ -1,5 +1,5 @@
 SH7753EVB BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/renesas/sh7753evb/
 F:	include/configs/sh7753evb.h
diff --git a/board/renesas/sh7757lcr/MAINTAINERS b/board/renesas/sh7757lcr/MAINTAINERS
index bbdd6d0812..20aca678a6 100644
--- a/board/renesas/sh7757lcr/MAINTAINERS
+++ b/board/renesas/sh7757lcr/MAINTAINERS
@@ -1,5 +1,5 @@
 SH7757LCR BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/renesas/sh7757lcr/
 F:	include/configs/sh7757lcr.h
diff --git a/board/renesas/sh7785lcr/MAINTAINERS b/board/renesas/sh7785lcr/MAINTAINERS
index 0d99de68d7..17578e036a 100644
--- a/board/renesas/sh7785lcr/MAINTAINERS
+++ b/board/renesas/sh7785lcr/MAINTAINERS
@@ -1,5 +1,5 @@
 SH7785LCR BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/renesas/sh7785lcr/
 F:	include/configs/sh7785lcr.h
diff --git a/board/sacsng/MAINTAINERS b/board/sacsng/MAINTAINERS
index c2c8ee30e7..b76e462fd4 100644
--- a/board/sacsng/MAINTAINERS
+++ b/board/sacsng/MAINTAINERS
@@ -1,5 +1,5 @@
 SACSNG BOARD
-M:	Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
+#M:	Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
 S:	Orphan (since 2014-06)
 F:	board/sacsng/
 F:	include/configs/sacsng.h
diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox
index 529c447a5b..5f879f5506 100644
--- a/board/sandbox/README.sandbox
+++ b/board/sandbox/README.sandbox
@@ -19,7 +19,7 @@ create unit tests which we can run to test this upper level code.
 CONFIG_SANDBOX is defined when building a native board.
 
 The chosen vendor and board names are also 'sandbox', so there is a single
-board in board/sandbox/sandbox.
+board in board/sandbox.
 
 CONFIG_SANDBOX_BIG_ENDIAN should be defined when running on big-endian
 machines.
@@ -32,7 +32,7 @@ Basic Operation
 
 To run sandbox U-Boot use something like:
 
-   make sandbox_config all
+   make sandbox_defconfig all
    ./u-boot
 
 Note:
@@ -41,7 +41,7 @@ Note:
    build sandbox without SDL (i.e. no display/keyboard support) by removing
    the CONFIG_SANDBOX_SDL line in include/configs/sandbox.h or using:
 
-      make sandbox_config all NO_SDL=1
+      make sandbox_defconfig all NO_SDL=1
       ./u-boot
 
 
diff --git a/board/sandburst/karef/MAINTAINERS b/board/sandburst/karef/MAINTAINERS
index 4c29ae7b59..21510e85c0 100644
--- a/board/sandburst/karef/MAINTAINERS
+++ b/board/sandburst/karef/MAINTAINERS
@@ -1,5 +1,5 @@
 KAREF BOARD
-M:	Travis Sawyer <travis.sawyer@sandburst.com>
+#M:	Travis Sawyer <travis.sawyer@sandburst.com>
 S:	Orphan (since 2014-03)
 F:	board/sandburst/karef/
 F:	include/configs/KAREF.h
diff --git a/board/sandburst/metrobox/MAINTAINERS b/board/sandburst/metrobox/MAINTAINERS
index f5734ba218..71d18f9186 100644
--- a/board/sandburst/metrobox/MAINTAINERS
+++ b/board/sandburst/metrobox/MAINTAINERS
@@ -1,5 +1,5 @@
 METROBOX BOARD
-M:	Travis Sawyer <travis.sawyer@sandburst.com>
+#M:	Travis Sawyer <travis.sawyer@sandburst.com>
 S:	Orphan (since 2014-03)
 F:	board/sandburst/metrobox/
 F:	include/configs/METROBOX.h
diff --git a/board/sandpoint/MAINTAINERS b/board/sandpoint/MAINTAINERS
index f28c309e0d..569cf42e10 100644
--- a/board/sandpoint/MAINTAINERS
+++ b/board/sandpoint/MAINTAINERS
@@ -6,7 +6,7 @@ F:	include/configs/Sandpoint8240.h
 F:	configs/Sandpoint8240_defconfig
 
 SANDPOINT8245 BOARD
-M:	Jim Thompson <jim@musenki.com>
+#M:	Jim Thompson <jim@musenki.com>
 S:	Orphan (since 2014-04)
 F:	include/configs/Sandpoint8245.h
 F:	configs/Sandpoint8245_defconfig
diff --git a/board/sbc405/MAINTAINERS b/board/sbc405/MAINTAINERS
index dbb4451ceb..2abad25997 100644
--- a/board/sbc405/MAINTAINERS
+++ b/board/sbc405/MAINTAINERS
@@ -1,5 +1,5 @@
 SBC405 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/sbc405/
 F:	include/configs/sbc405.h
diff --git a/board/socrates/MAINTAINERS b/board/socrates/MAINTAINERS
index fc3e11dff0..293b8e6d01 100644
--- a/board/socrates/MAINTAINERS
+++ b/board/socrates/MAINTAINERS
@@ -1,5 +1,5 @@
 SOCRATES BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/socrates/
 F:	include/configs/socrates.h
diff --git a/board/spear/spear300/MAINTAINERS b/board/spear/spear300/MAINTAINERS
index 15164fe3a3..07152aefba 100644
--- a/board/spear/spear300/MAINTAINERS
+++ b/board/spear/spear300/MAINTAINERS
@@ -6,7 +6,7 @@ F:	include/configs/spear3xx_evb.h
 F:	configs/spear300_defconfig
 
 SPEAR300_NAND BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	configs/spear300_nand_defconfig
 F:	configs/spear300_usbtty_defconfig
diff --git a/board/spear/spear310/MAINTAINERS b/board/spear/spear310/MAINTAINERS
index 3a7e610cb5..4f9aa15b83 100644
--- a/board/spear/spear310/MAINTAINERS
+++ b/board/spear/spear310/MAINTAINERS
@@ -6,7 +6,7 @@ F:	include/configs/spear3xx_evb.h
 F:	configs/spear310_defconfig
 
 SPEAR310_NAND BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	configs/spear310_nand_defconfig
 F:	configs/spear310_pnor_defconfig
diff --git a/board/spear/spear320/MAINTAINERS b/board/spear/spear320/MAINTAINERS
index 414becacc1..bf7809230f 100644
--- a/board/spear/spear320/MAINTAINERS
+++ b/board/spear/spear320/MAINTAINERS
@@ -6,7 +6,7 @@ F:	include/configs/spear3xx_evb.h
 F:	configs/spear320_defconfig
 
 SPEAR320_NAND BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	configs/spear320_nand_defconfig
 F:	configs/spear320_pnor_defconfig
diff --git a/board/spear/spear600/MAINTAINERS b/board/spear/spear600/MAINTAINERS
index a978fdd9f7..ddcd11a873 100644
--- a/board/spear/spear600/MAINTAINERS
+++ b/board/spear/spear600/MAINTAINERS
@@ -6,7 +6,7 @@ F:	include/configs/spear6xx_evb.h
 F:	configs/spear600_defconfig
 
 SPEAR600_NAND BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	configs/spear600_nand_defconfig
 F:	configs/spear600_usbtty_defconfig
diff --git a/board/st-ericsson/u8500/MAINTAINERS b/board/st-ericsson/u8500/MAINTAINERS
index 54e7921ae1..e2581eb2e4 100644
--- a/board/st-ericsson/u8500/MAINTAINERS
+++ b/board/st-ericsson/u8500/MAINTAINERS
@@ -1,5 +1,5 @@
 U8500 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/st-ericsson/u8500/
 F:	include/configs/u8500_href.h
diff --git a/board/stx/stxgp3/MAINTAINERS b/board/stx/stxgp3/MAINTAINERS
index 6f485d465d..bd5743c7de 100644
--- a/board/stx/stxgp3/MAINTAINERS
+++ b/board/stx/stxgp3/MAINTAINERS
@@ -1,5 +1,5 @@
 STXGP3 BOARD
-M:	Dan Malek <dan@embeddedalley.com>
+#M:	Dan Malek <dan@embeddedalley.com>
 S:	Orphan (since 2014-06)
 F:	board/stx/stxgp3/
 F:	include/configs/stxgp3.h
diff --git a/board/stx/stxssa/MAINTAINERS b/board/stx/stxssa/MAINTAINERS
index f56adf0cf5..b7cc89bf73 100644
--- a/board/stx/stxssa/MAINTAINERS
+++ b/board/stx/stxssa/MAINTAINERS
@@ -1,5 +1,5 @@
 STXSSA BOARD
-M:	Dan Malek <dan@embeddedalley.com>
+#M:	Dan Malek <dan@embeddedalley.com>
 S:	Orphan (since 2014-06)
 F:	board/stx/stxssa/
 F:	include/configs/stxssa.h
diff --git a/board/tcm-bf518/MAINTAINERS b/board/tcm-bf518/MAINTAINERS
index f649b06155..169012269f 100644
--- a/board/tcm-bf518/MAINTAINERS
+++ b/board/tcm-bf518/MAINTAINERS
@@ -1,5 +1,5 @@
 TCM-BF518 BOARD
-M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 S:	Orphan (since 2014-03)
 F:	board/tcm-bf518/
 F:	include/configs/tcm-bf518.h
diff --git a/board/tcm-bf537/MAINTAINERS b/board/tcm-bf537/MAINTAINERS
index 9ee557da45..1cd48451df 100644
--- a/board/tcm-bf537/MAINTAINERS
+++ b/board/tcm-bf537/MAINTAINERS
@@ -1,5 +1,5 @@
 TCM-BF537 BOARD
-M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 S:	Orphan (since 2014-03)
 F:	board/tcm-bf537/
 F:	include/configs/tcm-bf537.h
diff --git a/board/ti/evm/MAINTAINERS b/board/ti/evm/MAINTAINERS
index b2ebadcb40..d0b27882bc 100644
--- a/board/ti/evm/MAINTAINERS
+++ b/board/ti/evm/MAINTAINERS
@@ -6,7 +6,7 @@ F:	include/configs/omap3_evm.h
 F:	configs/omap3_evm_defconfig
 
 OMAP3_EVM_QUICK_MMC BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	include/configs/omap3_evm_quick_mmc.h
 F:	configs/omap3_evm_quick_mmc_defconfig
diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c
index 21a5a0a252..6070a99770 100644
--- a/board/ti/ks2_evm/ddr3_k2hk.c
+++ b/board/ti/ks2_evm/ddr3_k2hk.c
@@ -81,4 +81,8 @@ void ddr3_init(void)
 		while (1)
 			;
 	}
+
+	/* Apply the workaround for PG 1.0 and 1.1 Silicons */
+	if (cpu_revision() <= 1)
+		ddr3_err_reset_workaround();
 }
diff --git a/board/ti/ti816x/MAINTAINERS b/board/ti/ti816x/MAINTAINERS
index 8bf6122908..d3de144bc2 100644
--- a/board/ti/ti816x/MAINTAINERS
+++ b/board/ti/ti816x/MAINTAINERS
@@ -1,5 +1,5 @@
 TI816X BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/ti/ti816x/
 F:	include/configs/ti816x_evm.h
diff --git a/board/ti/tnetv107xevm/MAINTAINERS b/board/ti/tnetv107xevm/MAINTAINERS
index 76ccfdc1e1..8a92c6bf87 100644
--- a/board/ti/tnetv107xevm/MAINTAINERS
+++ b/board/ti/tnetv107xevm/MAINTAINERS
@@ -1,5 +1,5 @@
 TNETV107XEVM BOARD
-M:	Chan-Taek Park <c-park@ti.com>
+#M:	Chan-Taek Park <c-park@ti.com>
 S:	Orphan (since 2014-06)
 F:	board/ti/tnetv107xevm/
 F:	include/configs/tnetv107x_evm.h
diff --git a/board/total5200/MAINTAINERS b/board/total5200/MAINTAINERS
index 983b96d12c..afb0058d08 100644
--- a/board/total5200/MAINTAINERS
+++ b/board/total5200/MAINTAINERS
@@ -1,5 +1,5 @@
 TOTAL5200 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/total5200/
 F:	include/configs/Total5200.h
diff --git a/board/tqc/tqm5200/MAINTAINERS b/board/tqc/tqm5200/MAINTAINERS
index 581ef95453..d3eb543140 100644
--- a/board/tqc/tqm5200/MAINTAINERS
+++ b/board/tqc/tqm5200/MAINTAINERS
@@ -1,5 +1,5 @@
 TQM5200 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/tqc/tqm5200/
 F:	include/configs/aev.h
diff --git a/board/tqc/tqm8272/MAINTAINERS b/board/tqc/tqm8272/MAINTAINERS
index a660de19bc..988d2b189b 100644
--- a/board/tqc/tqm8272/MAINTAINERS
+++ b/board/tqc/tqm8272/MAINTAINERS
@@ -1,5 +1,5 @@
 TQM8272 BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/tqc/tqm8272/
 F:	include/configs/TQM8272.h
diff --git a/board/tqc/tqm834x/MAINTAINERS b/board/tqc/tqm834x/MAINTAINERS
index 10c14f3e0b..543ab1b552 100644
--- a/board/tqc/tqm834x/MAINTAINERS
+++ b/board/tqc/tqm834x/MAINTAINERS
@@ -1,5 +1,5 @@
 TQM834X BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/tqc/tqm834x/
 F:	include/configs/TQM834x.h
diff --git a/board/tqc/tqm8xx/MAINTAINERS b/board/tqc/tqm8xx/MAINTAINERS
index 161fa68e5b..fe4a212029 100644
--- a/board/tqc/tqm8xx/MAINTAINERS
+++ b/board/tqc/tqm8xx/MAINTAINERS
@@ -39,7 +39,7 @@ F:	configs/virtlab2_defconfig
 F:	configs/wtk_defconfig
 
 NSCU BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	include/configs/NSCU.h
 F:	configs/NSCU_defconfig
diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c
index b4d3994158..b5249e74a7 100644
--- a/board/ttcontrol/vision2/vision2.c
+++ b/board/ttcontrol/vision2/vision2.c
@@ -144,6 +144,11 @@ static void setup_uart(void)
 }
 
 #ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 1) ? 121 : -1;
+}
+
 void spi_io_init(void)
 {
 	static const iomux_v3_cfg_t spi_pads[] = {
diff --git a/board/v38b/MAINTAINERS b/board/v38b/MAINTAINERS
index 1b12d0bdad..d1a6ae6b2f 100644
--- a/board/v38b/MAINTAINERS
+++ b/board/v38b/MAINTAINERS
@@ -1,5 +1,5 @@
 V38B BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/v38b/
 F:	include/configs/v38b.h
diff --git a/board/woodburn/MAINTAINERS b/board/woodburn/MAINTAINERS
index 715f2caa11..4fbf6bb88b 100644
--- a/board/woodburn/MAINTAINERS
+++ b/board/woodburn/MAINTAINERS
@@ -6,7 +6,7 @@ F:	include/configs/woodburn.h
 F:	configs/woodburn_defconfig
 
 WOODBURN_SD BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	include/configs/woodburn_sd.h
 F:	configs/woodburn_sd_defconfig
diff --git a/board/xaeniax/MAINTAINERS b/board/xaeniax/MAINTAINERS
index f2fa4bf905..44bb5883f2 100644
--- a/board/xaeniax/MAINTAINERS
+++ b/board/xaeniax/MAINTAINERS
@@ -1,5 +1,5 @@
 XAENIAX BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/xaeniax/
 F:	include/configs/xaeniax.h
diff --git a/board/xes/xpedite517x/MAINTAINERS b/board/xes/xpedite517x/MAINTAINERS
index c74fdf4874..035cb1499a 100644
--- a/board/xes/xpedite517x/MAINTAINERS
+++ b/board/xes/xpedite517x/MAINTAINERS
@@ -1,5 +1,5 @@
 XPEDITE517X BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/xes/xpedite517x/
 F:	include/configs/xpedite517x.h
diff --git a/board/xes/xpedite520x/MAINTAINERS b/board/xes/xpedite520x/MAINTAINERS
index 7f9bf9ae76..2fd4ac072d 100644
--- a/board/xes/xpedite520x/MAINTAINERS
+++ b/board/xes/xpedite520x/MAINTAINERS
@@ -1,5 +1,5 @@
 XPEDITE520X BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/xes/xpedite520x/
 F:	include/configs/xpedite520x.h
diff --git a/board/xes/xpedite537x/MAINTAINERS b/board/xes/xpedite537x/MAINTAINERS
index a13dcf196c..45a420d11a 100644
--- a/board/xes/xpedite537x/MAINTAINERS
+++ b/board/xes/xpedite537x/MAINTAINERS
@@ -1,5 +1,5 @@
 XPEDITE537X BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/xes/xpedite537x/
 F:	include/configs/xpedite537x.h
diff --git a/board/xes/xpedite550x/MAINTAINERS b/board/xes/xpedite550x/MAINTAINERS
index 12d321eddd..b22f0e6173 100644
--- a/board/xes/xpedite550x/MAINTAINERS
+++ b/board/xes/xpedite550x/MAINTAINERS
@@ -1,5 +1,5 @@
 XPEDITE550X BOARD
-M:	-
+#M:	-
 S:	Maintained
 F:	board/xes/xpedite550x/
 F:	include/configs/xpedite550x.h
diff --git a/common/Kconfig b/common/Kconfig
new file mode 100644
index 0000000000..216a8debd9
--- /dev/null
+++ b/common/Kconfig
@@ -0,0 +1,34 @@
+menu "Command line interface"
+	depends on !SPL_BUILD
+
+config CMD_BOOTM
+	bool "Enable bootm command"
+	default y
+	help
+	  Boot an application image from the memory.
+
+config CMD_CRC32
+	bool "Enable crc32 command"
+	default y
+	help
+	  Compute CRC32.
+
+config CMD_EXPORTENV
+	bool "Enable env export command"
+	default y
+	help
+	  Export environments.
+
+config CMD_IMPORTENV
+	bool "Enable env import command"
+	default y
+	help
+	  Import environments.
+
+config CMD_GO
+	bool "Enable go command"
+	default y
+	help
+	  Start an application at a given address.
+
+endmenu
diff --git a/common/Makefile b/common/Makefile
index aca0f7faf9..b19d3793b4 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -243,13 +243,8 @@ obj-y += cmd_nvedit.o
 #environment
 obj-y += env_common.o
 #others
-ifdef CONFIG_DDR_SPD
-SPD := y
-endif
-ifdef CONFIG_SPD_EEPROM
-SPD := y
-endif
-obj-$(SPD) += ddr_spd.o
+obj-$(CONFIG_DDR_SPD) += ddr_spd.o
+obj-$(CONFIG_SPD_EEPROM) += ddr_spd.o
 obj-$(CONFIG_HWCONFIG) += hwconfig.o
 obj-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o
 obj-y += console.o
@@ -264,4 +259,10 @@ obj-$(CONFIG_IO_TRACE) += iotrace.o
 obj-y += memsize.o
 obj-y += stdio.o
 
+# This option is not just y/n - it can have a numeric value
+ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
+obj-y += aboot.o
+obj-y += fb_mmc.o
+endif
+
 CFLAGS_env_embedded.o := -Wa,--no-warn -DENV_CRC=$(shell tools/envcrc 2>/dev/null)
diff --git a/common/board_f.c b/common/board_f.c
index ea33eadc16..e6aa298d5a 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -34,7 +34,7 @@
 #ifdef CONFIG_MPC5xxx
 #include <mpc5xxx.h>
 #endif
-#if (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
+#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
 #include <asm/mp.h>
 #endif
 
@@ -341,21 +341,23 @@ static int setup_ram_buf(void)
 
 static int setup_fdt(void)
 {
-#ifdef CONFIG_OF_EMBED
+#ifdef CONFIG_OF_CONTROL
+# ifdef CONFIG_OF_EMBED
 	/* Get a pointer to the FDT */
 	gd->fdt_blob = __dtb_dt_begin;
-#elif defined CONFIG_OF_SEPARATE
+# elif defined CONFIG_OF_SEPARATE
 	/* FDT is at end of image */
 	gd->fdt_blob = (ulong *)&_end;
-#elif defined(CONFIG_OF_HOSTFILE)
+# elif defined(CONFIG_OF_HOSTFILE)
 	if (read_fdt_from_file()) {
 		puts("Failed to read control FDT\n");
 		return -1;
 	}
-#endif
+# endif
 	/* Allow the early environment to override the fdt address */
 	gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
 						(uintptr_t)gd->fdt_blob);
+#endif
 	return 0;
 }
 
@@ -392,7 +394,7 @@ static int setup_dest_addr(void)
 	gd->ram_top = board_get_usable_ram_top(gd->mon_len);
 	gd->relocaddr = gd->ram_top;
 	debug("Ram top: %08lX\n", (ulong)gd->ram_top);
-#if (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
+#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
 	/*
 	 * We need to make sure the location we intend to put secondary core
 	 * boot code is reserved and not used by any part of u-boot
diff --git a/common/cmd_fastboot.c b/common/cmd_fastboot.c
index 83fa7bdded..909616dcb7 100644
--- a/common/cmd_fastboot.c
+++ b/common/cmd_fastboot.c
@@ -30,7 +30,8 @@ static int do_fastboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 }
 
 U_BOOT_CMD(
-	fastboot,	1,	1,	do_fastboot,
-	"fastboot - enter USB Fastboot protocol",
-	""
+	fastboot,	1,	0,	do_fastboot,
+	"use USB Fastboot protocol",
+	"\n"
+	"    - run as a fastboot usb device"
 );
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index f9ced9d74c..7f962dcb25 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -647,8 +647,6 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
 		printf("\nNAND %s: ", read ? "read" : "write");
 
-		nand = &nand_info[dev];
-
 		s = strchr(cmd, '.');
 
 		if (s && !strcmp(s, ".raw")) {
@@ -657,6 +655,8 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			if (arg_off(argv[3], &dev, &off, &size, &maxsize))
 				return 1;
 
+			nand = &nand_info[dev];
+
 			if (argc > 4 && !str2long(argv[4], &pagecount)) {
 				printf("'%s' is not a number\n", argv[4]);
 				return 1;
@@ -679,6 +679,8 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			rwsize = size;
 		}
 
+		nand = &nand_info[dev];
+
 		if (!s || !strcmp(s, ".jffs2") ||
 		    !strcmp(s, ".e") || !strcmp(s, ".i")) {
 			if (read)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index b4ceb71466..c60e8d10df 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -13,19 +13,6 @@
 
 #include <asm/io.h>
 
-#ifndef CONFIG_SF_DEFAULT_SPEED
-# define CONFIG_SF_DEFAULT_SPEED	1000000
-#endif
-#ifndef CONFIG_SF_DEFAULT_MODE
-# define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
-#endif
-#ifndef CONFIG_SF_DEFAULT_CS
-# define CONFIG_SF_DEFAULT_CS		0
-#endif
-#ifndef CONFIG_SF_DEFAULT_BUS
-# define CONFIG_SF_DEFAULT_BUS		0
-#endif
-
 static struct spi_flash *flash;
 
 
diff --git a/common/cmd_spi.c b/common/cmd_spi.c
index 3c8e913be5..be5709c617 100644
--- a/common/cmd_spi.c
+++ b/common/cmd_spi.c
@@ -11,6 +11,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <errno.h>
 #include <spi.h>
 
 /*-----------------------------------------------------------------------
@@ -38,6 +39,35 @@ static int   		bitlen;
 static uchar 		dout[MAX_SPI_BYTES];
 static uchar 		din[MAX_SPI_BYTES];
 
+static int do_spi_xfer(int bus, int cs)
+{
+	struct spi_slave *slave;
+	int rcode = 0;
+
+	slave = spi_setup_slave(bus, cs, 1000000, mode);
+	if (!slave) {
+		printf("Invalid device %d:%d\n", bus, cs);
+		return -EINVAL;
+	}
+
+	spi_claim_bus(slave);
+	if (spi_xfer(slave, bitlen, dout, din,
+		     SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+		printf("Error during SPI transaction\n");
+		rcode = -EIO;
+	} else {
+		int j;
+
+		for (j = 0; j < ((bitlen + 7) / 8); j++)
+			printf("%02X", din[j]);
+		printf("\n");
+	}
+	spi_release_bus(slave);
+	spi_free_slave(slave);
+
+	return rcode;
+}
+
 /*
  * SPI read/write
  *
@@ -51,11 +81,9 @@ static uchar 		din[MAX_SPI_BYTES];
 
 int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	struct spi_slave *slave;
 	char  *cp = 0;
 	uchar tmp;
 	int   j;
-	int   rcode = 0;
 
 	/*
 	 * We use the last specified parameters, unless new ones are
@@ -103,27 +131,10 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		return 1;
 	}
 
-	slave = spi_setup_slave(bus, cs, 1000000, mode);
-	if (!slave) {
-		printf("Invalid device %d:%d\n", bus, cs);
+	if (do_spi_xfer(bus, cs))
 		return 1;
-	}
 
-	spi_claim_bus(slave);
-	if(spi_xfer(slave, bitlen, dout, din,
-				SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
-		printf("Error during SPI transaction\n");
-		rcode = 1;
-	} else {
-		for(j = 0; j < ((bitlen + 7) / 8); j++) {
-			printf("%02X", din[j]);
-		}
-		printf("\n");
-	}
-	spi_release_bus(slave);
-	spi_free_slave(slave);
-
-	return rcode;
+	return 0;
 }
 
 /***************************************************/
diff --git a/common/console.c b/common/console.c
index 898da3935e..5a2f411600 100644
--- a/common/console.c
+++ b/common/console.c
@@ -524,6 +524,7 @@ static int ctrlc_disabled = 0;	/* see disable_ctrl() */
 static int ctrlc_was_pressed = 0;
 int ctrlc(void)
 {
+#ifndef CONFIG_SANDBOX
 	if (!ctrlc_disabled && gd->have_console) {
 		if (tstc()) {
 			switch (getc()) {
@@ -535,6 +536,8 @@ int ctrlc(void)
 			}
 		}
 	}
+#endif
+
 	return 0;
 }
 /* Reads user's confirmation.
diff --git a/common/fb_mmc.c b/common/fb_mmc.c
new file mode 100644
index 0000000000..fb06d8a557
--- /dev/null
+++ b/common/fb_mmc.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fb_mmc.h>
+#include <part.h>
+#include <aboot.h>
+#include <sparse_format.h>
+
+/* The 64 defined bytes plus the '\0' */
+#define RESPONSE_LEN	(64 + 1)
+
+static char *response_str;
+
+void fastboot_fail(const char *s)
+{
+	strncpy(response_str, "FAIL", 4);
+	strncat(response_str, s, RESPONSE_LEN - 4 - 1);
+}
+
+void fastboot_okay(const char *s)
+{
+	strncpy(response_str, "OKAY", 4);
+	strncat(response_str, s, RESPONSE_LEN - 4 - 1);
+}
+
+static void write_raw_image(block_dev_desc_t *dev_desc, disk_partition_t *info,
+		const char *part_name, void *buffer,
+		unsigned int download_bytes)
+{
+	lbaint_t blkcnt;
+	lbaint_t blks;
+
+	/* determine number of blocks to write */
+	blkcnt = ((download_bytes + (info->blksz - 1)) & ~(info->blksz - 1));
+	blkcnt = blkcnt / info->blksz;
+
+	if (blkcnt > info->size) {
+		error("too large for partition: '%s'\n", part_name);
+		fastboot_fail("too large for partition");
+		return;
+	}
+
+	puts("Flashing Raw Image\n");
+
+	blks = dev_desc->block_write(dev_desc->dev, info->start, blkcnt,
+				     buffer);
+	if (blks != blkcnt) {
+		error("failed writing to device %d\n", dev_desc->dev);
+		fastboot_fail("failed writing to device");
+		return;
+	}
+
+	printf("........ wrote " LBAFU " bytes to '%s'\n", blkcnt * info->blksz,
+	       part_name);
+	fastboot_okay("");
+}
+
+void fb_mmc_flash_write(const char *cmd, void *download_buffer,
+			unsigned int download_bytes, char *response)
+{
+	int ret;
+	block_dev_desc_t *dev_desc;
+	disk_partition_t info;
+
+	/* initialize the response buffer */
+	response_str = response;
+
+	dev_desc = get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+	if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+		error("invalid mmc device\n");
+		fastboot_fail("invalid mmc device");
+		return;
+	}
+
+	ret = get_partition_info_efi_by_name(dev_desc, cmd, &info);
+	if (ret) {
+		error("cannot find partition: '%s'\n", cmd);
+		fastboot_fail("cannot find partition");
+		return;
+	}
+
+	if (is_sparse_image(download_buffer))
+		write_sparse_image(dev_desc, &info, cmd, download_buffer,
+				   download_bytes);
+	else
+		write_raw_image(dev_desc, &info, cmd, download_buffer,
+				download_bytes);
+}
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 784a570a81..3f641566b9 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -930,15 +930,6 @@ void fdt_del_node_and_alias(void *blob, const char *alias)
 	fdt_delprop(blob, off, alias);
 }
 
-/* Helper to read a big number; size is in cells (not bytes) */
-static inline u64 of_read_number(const fdt32_t *cell, int size)
-{
-	u64 r = 0;
-	while (size--)
-		r = (r << 32) | fdt32_to_cpu(*(cell++));
-	return r;
-}
-
 #define PRu64	"%llx"
 
 /* Max address size we deal with */
@@ -972,7 +963,7 @@ struct of_bus {
 };
 
 /* Default translator (generic bus) */
-static void of_bus_default_count_cells(void *blob, int parentoffset,
+void of_bus_default_count_cells(void *blob, int parentoffset,
 					int *addrc, int *sizec)
 {
 	const fdt32_t *prop;
diff --git a/config.mk b/config.mk
index b4bf6f95d3..2157537c82 100644
--- a/config.mk
+++ b/config.mk
@@ -53,6 +53,10 @@ ifdef	BOARD
 sinclude $(srctree)/board/$(BOARDDIR)/config.mk	# include board specific rules
 endif
 
+ifdef FTRACE
+PLATFORM_CPPFLAGS += -finstrument-functions -DFTRACE
+endif
+
 #########################################################################
 
 RELFLAGS := $(PLATFORM_RELFLAGS)
diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig
new file mode 100644
index 0000000000..85eceb9120
--- /dev/null
+++ b/configs/T1042RDB_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index 00317c44dc..e25714366b 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -2,3 +2,5 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT,ENABLE_VBOOT"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_AM335X_EVM=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig
index 7ea5c0da2c..fc30508170 100644
--- a/configs/arndale_defconfig
+++ b/configs/arndale_defconfig
@@ -2,3 +2,4 @@ CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_EXYNOS=y
 +S:CONFIG_TARGET_ARNDALE=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale"
diff --git a/configs/bct-brettl2_defconfig b/configs/bct-brettl2_defconfig
index 367630647e..26b145d30a 100644
--- a/configs/bct-brettl2_defconfig
+++ b/configs/bct-brettl2_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BCT_BRETTL2=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index 7c9d94bbcc..ab615a83d7 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -2,3 +2,4 @@
 +S:CONFIG_TEGRA=y
 +S:CONFIG_TEGRA30=y
 +S:CONFIG_TARGET_BEAVER=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-beaver"
diff --git a/configs/bf506f-ezkit_defconfig b/configs/bf506f-ezkit_defconfig
index f81f412f56..f164e06b54 100644
--- a/configs/bf506f-ezkit_defconfig
+++ b/configs/bf506f-ezkit_defconfig
@@ -1,2 +1,5 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF506F_EZKIT=y
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
diff --git a/configs/bf518f-ezbrd_defconfig b/configs/bf518f-ezbrd_defconfig
index a93eed0882..fb35ad023d 100644
--- a/configs/bf518f-ezbrd_defconfig
+++ b/configs/bf518f-ezbrd_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF518F_EZBRD=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf526-ezbrd_defconfig b/configs/bf526-ezbrd_defconfig
index 4a452235ac..da06d3ad6e 100644
--- a/configs/bf526-ezbrd_defconfig
+++ b/configs/bf526-ezbrd_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF526_EZBRD=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf527-ad7160-eval_defconfig b/configs/bf527-ad7160-eval_defconfig
index d9db715f14..47f53c9d81 100644
--- a/configs/bf527-ad7160-eval_defconfig
+++ b/configs/bf527-ad7160-eval_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF527_AD7160_EVAL=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf527-ezkit-v2_defconfig b/configs/bf527-ezkit-v2_defconfig
index aedbb9649a..e250e10354 100644
--- a/configs/bf527-ezkit-v2_defconfig
+++ b/configs/bf527-ezkit-v2_defconfig
@@ -1,3 +1,4 @@
 CONFIG_SYS_EXTRA_OPTIONS="BF527_EZKIT_REV_2_1"
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF527_EZKIT=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf527-ezkit_defconfig b/configs/bf527-ezkit_defconfig
index 3ed77a66b0..69f6ef781b 100644
--- a/configs/bf527-ezkit_defconfig
+++ b/configs/bf527-ezkit_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF527_EZKIT=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf527-sdp_defconfig b/configs/bf527-sdp_defconfig
index 0f8c28c339..57f47e9fc8 100644
--- a/configs/bf527-sdp_defconfig
+++ b/configs/bf527-sdp_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF527_SDP=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf533-ezkit_defconfig b/configs/bf533-ezkit_defconfig
index 217d4c30a0..57f8da1475 100644
--- a/configs/bf533-ezkit_defconfig
+++ b/configs/bf533-ezkit_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF533_EZKIT=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf533-stamp_defconfig b/configs/bf533-stamp_defconfig
index a99b3c75ff..1bcf3d319a 100644
--- a/configs/bf533-stamp_defconfig
+++ b/configs/bf533-stamp_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF533_STAMP=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf537-stamp_defconfig b/configs/bf537-stamp_defconfig
index d9daf7e309..9b9a92f13f 100644
--- a/configs/bf537-stamp_defconfig
+++ b/configs/bf537-stamp_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF537_STAMP=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf538f-ezkit_defconfig b/configs/bf538f-ezkit_defconfig
index 0507cb2b91..1892151db0 100644
--- a/configs/bf538f-ezkit_defconfig
+++ b/configs/bf538f-ezkit_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF538F_EZKIT=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf548-ezkit_defconfig b/configs/bf548-ezkit_defconfig
index 7bb4064ad7..52369849aa 100644
--- a/configs/bf548-ezkit_defconfig
+++ b/configs/bf548-ezkit_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF548_EZKIT=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf561-acvilon_defconfig b/configs/bf561-acvilon_defconfig
index ba8a418928..098f31fb55 100644
--- a/configs/bf561-acvilon_defconfig
+++ b/configs/bf561-acvilon_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF561_ACVILON=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf561-ezkit_defconfig b/configs/bf561-ezkit_defconfig
index 7ceb1d9f4a..5665288316 100644
--- a/configs/bf561-ezkit_defconfig
+++ b/configs/bf561-ezkit_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF561_EZKIT=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/br4_defconfig b/configs/br4_defconfig
index 9d91933218..5655d54b04 100644
--- a/configs/br4_defconfig
+++ b/configs/br4_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BR4=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index bb042b4648..4466e98ac8 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -2,3 +2,4 @@
 +S:CONFIG_TEGRA=y
 +S:CONFIG_TEGRA30=y
 +S:CONFIG_TARGET_CARDHU=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-cardhu"
diff --git a/configs/cm-bf527_defconfig b/configs/cm-bf527_defconfig
index cb5110c7b1..a6830b54fd 100644
--- a/configs/cm-bf527_defconfig
+++ b/configs/cm-bf527_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF527=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cm-bf533_defconfig b/configs/cm-bf533_defconfig
index aa38d0ed69..b9508ae297 100644
--- a/configs/cm-bf533_defconfig
+++ b/configs/cm-bf533_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF533=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cm-bf537e_defconfig b/configs/cm-bf537e_defconfig
index b9deaae3bf..a44eab7f0d 100644
--- a/configs/cm-bf537e_defconfig
+++ b/configs/cm-bf537e_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF537E=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cm-bf537u_defconfig b/configs/cm-bf537u_defconfig
index 16f7ae17a2..29c33b9514 100644
--- a/configs/cm-bf537u_defconfig
+++ b/configs/cm-bf537u_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF537U=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cm-bf548_defconfig b/configs/cm-bf548_defconfig
index e60306a1ea..525f2e7f37 100644
--- a/configs/cm-bf548_defconfig
+++ b/configs/cm-bf548_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF548=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cm-bf561_defconfig b/configs/cm-bf561_defconfig
index 1b9301cb9e..062bfeb6dc 100644
--- a/configs/cm-bf561_defconfig
+++ b/configs/cm-bf561_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF561=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
new file mode 100644
index 0000000000..50c06f7feb
--- /dev/null
+++ b/configs/cm_fx6_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/cm_fx6/imximage.cfg,MX6QDL,SPL"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_CM_FX6=y
diff --git a/configs/colibri_t20_iris_defconfig b/configs/colibri_t20_iris_defconfig
index b2a21e186a..b76f78bba5 100644
--- a/configs/colibri_t20_iris_defconfig
+++ b/configs/colibri_t20_iris_defconfig
@@ -2,3 +2,4 @@
 +S:CONFIG_TEGRA=y
 +S:CONFIG_TEGRA20=y
 +S:CONFIG_TARGET_COLIBRI_T20_IRIS=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri_t20_iris"
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index abb41f3f22..b955303070 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -2,3 +2,4 @@
 +S:CONFIG_TEGRA=y
 +S:CONFIG_TEGRA30=y
 +S:CONFIG_TARGET_COLIBRI_T30=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri"
diff --git a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
index be1a371144..c8695abfec 100644
--- a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
+++ b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
@@ -2,3 +2,4 @@ CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH,DEVELOP"
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_CONTROLCENTERD=y
+# CONFIG_CMD_BOOTM is not set
diff --git a/configs/controlcenterd_TRAILBLAZER_defconfig b/configs/controlcenterd_TRAILBLAZER_defconfig
index ab548a6fec..730b96e551 100644
--- a/configs/controlcenterd_TRAILBLAZER_defconfig
+++ b/configs/controlcenterd_TRAILBLAZER_defconfig
@@ -2,3 +2,4 @@ CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH"
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_CONTROLCENTERD=y
+# CONFIG_CMD_BOOTM is not set
diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index a06c527c8b..6249db7cb0 100644
--- a/configs/coreboot-x86_defconfig
+++ b/configs/coreboot-x86_defconfig
@@ -1,3 +1,5 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x01110000"
 CONFIG_X86=y
 CONFIG_TARGET_COREBOOT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="link"
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index 70677aac41..f704c75afa 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -2,3 +2,4 @@
 +S:CONFIG_TEGRA=y
 +S:CONFIG_TEGRA114=y
 +S:CONFIG_TARGET_DALMORE=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore"
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index a52231b655..d99b42955a 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -2,3 +2,4 @@
 +S:CONFIG_TEGRA=y
 +S:CONFIG_TEGRA20=y
 +S:CONFIG_TARGET_HARMONY=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-harmony"
diff --git a/configs/ip04_defconfig b/configs/ip04_defconfig
index 4f9895aa77..ba737aedfb 100644
--- a/configs/ip04_defconfig
+++ b/configs/ip04_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_IP04=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index 00eac92319..ef1d41c20b 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -2,3 +2,4 @@
 +S:CONFIG_TEGRA=y
 +S:CONFIG_TEGRA124=y
 +S:CONFIG_TARGET_JETSON_TK1=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1"
diff --git a/configs/kwb_defconfig b/configs/kwb_defconfig
index 5082ff750b..106a24f199 100644
--- a/configs/kwb_defconfig
+++ b/configs/kwb_defconfig
@@ -2,3 +2,4 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_KWB=y
+# CONFIG_CMD_CRC32 is not set
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
new file mode 100644
index 0000000000..3c574810ef
--- /dev/null
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021AQDS=y
diff --git a/configs/ls2085a_emu_D4_defconfig b/configs/ls2085a_emu_D4_defconfig
index f2f6882c99..0bc36ed0b0 100644
--- a/configs/ls2085a_emu_D4_defconfig
+++ b/configs/ls2085a_emu_D4_defconfig
@@ -1,3 +1,3 @@
-CONFIG_SYS_EXTRA_OPTIONS="ARM64,EMU,SYS_FSL_DDR4"
+CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4"
 CONFIG_ARM=y
 CONFIG_TARGET_LS2085A_EMU=y
diff --git a/configs/ls2085a_emu_defconfig b/configs/ls2085a_emu_defconfig
index 51ffa56a4c..a2efec3ccf 100644
--- a/configs/ls2085a_emu_defconfig
+++ b/configs/ls2085a_emu_defconfig
@@ -1,3 +1,3 @@
-CONFIG_SYS_EXTRA_OPTIONS="ARM64,EMU"
+CONFIG_SYS_EXTRA_OPTIONS="EMU"
 CONFIG_ARM=y
 CONFIG_TARGET_LS2085A_EMU=y
diff --git a/configs/ls2085a_simu_defconfig b/configs/ls2085a_simu_defconfig
index efa8e74548..7563a7546e 100644
--- a/configs/ls2085a_simu_defconfig
+++ b/configs/ls2085a_simu_defconfig
@@ -1,3 +1,3 @@
-CONFIG_SYS_EXTRA_OPTIONS="ARM64,SIMU"
+CONFIG_SYS_EXTRA_OPTIONS="SIMU"
 CONFIG_ARM=y
 CONFIG_TARGET_LS2085A_SIMU=y
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index e9a3930910..35963e9302 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -2,3 +2,4 @@
 +S:CONFIG_TEGRA=y
 +S:CONFIG_TEGRA20=y
 +S:CONFIG_TARGET_MEDCOM_WIDE=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-medcom-wide"
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 7f23786781..5cfd596761 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -1,3 +1,6 @@
 CONFIG_SPL=y
 +S:CONFIG_MICROBLAZE=y
 +S:CONFIG_TARGET_MICROBLAZE_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig
index 9ce960e0d5..7f6cdff384 100644
--- a/configs/mx6dlsabresd_defconfig
+++ b/configs/mx6dlsabresd_defconfig
@@ -1,3 +1,3 @@
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL"
 CONFIG_ARM=y
 CONFIG_TARGET_MX6SABRESD=y
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index a1c7ac58b6..a8428373ac 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -1,3 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
 CONFIG_TARGET_ODROID=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid"
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index aa9238142a..2a7f83bf89 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -2,3 +2,5 @@ CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_EXYNOS=y
 +S:CONFIG_TARGET_ORIGEN=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index 05974eb10c..d2d36a5848 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -2,3 +2,4 @@
 +S:CONFIG_TEGRA=y
 +S:CONFIG_TEGRA20=y
 +S:CONFIG_TARGET_PAZ00=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-paz00"
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index 797d5e0790..b944b3bb50 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -2,3 +2,4 @@ CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_EXYNOS=y
 +S:CONFIG_TARGET_PEACH_PIT=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit"
diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig
new file mode 100644
index 0000000000..53f3126e71
--- /dev/null
+++ b/configs/ph1_ld4_defconfig
@@ -0,0 +1,8 @@
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_UNIPHIER=y
++S:CONFIG_MACH_PH1_LD4=y
+CONFIG_NAND_DENALI=y
+CONFIG_SYS_NAND_DENALI_64BIT=y
+CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+S:CONFIG_SPL_NAND_DENALI=y
diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig
new file mode 100644
index 0000000000..209466ebcb
--- /dev/null
+++ b/configs/ph1_pro4_defconfig
@@ -0,0 +1,8 @@
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_UNIPHIER=y
++S:CONFIG_MACH_PH1_PRO4=y
+CONFIG_NAND_DENALI=y
+CONFIG_SYS_NAND_DENALI_64BIT=y
+CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+S:CONFIG_SPL_NAND_DENALI=y
diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig
new file mode 100644
index 0000000000..658977bcf6
--- /dev/null
+++ b/configs/ph1_sld8_defconfig
@@ -0,0 +1,8 @@
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_UNIPHIER=y
++S:CONFIG_MACH_PH1_SLD8=y
+CONFIG_NAND_DENALI=y
+CONFIG_SYS_NAND_DENALI_64BIT=y
+CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+S:CONFIG_SPL_NAND_DENALI=y
diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig
index 60e80ffa61..d2743b8ef6 100644
--- a/configs/plutux_defconfig
+++ b/configs/plutux_defconfig
@@ -2,3 +2,4 @@
 +S:CONFIG_TEGRA=y
 +S:CONFIG_TEGRA20=y
 +S:CONFIG_TARGET_PLUTUX=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-plutux"
diff --git a/configs/pr1_defconfig b/configs/pr1_defconfig
index a8784c11df..793a4e8376 100644
--- a/configs/pr1_defconfig
+++ b/configs/pr1_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_PR1=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index a9a3446fe5..cdce39f892 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -1,3 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
 CONFIG_TARGET_S5PC210_UNIVERSAL=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210"
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index e69de29bb2..47d8400ace 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -0,0 +1,3 @@
+CONFIG_OF_CONTROL=y
+CONFIG_OF_HOSTFILE=y
+CONFIG_DEFAULT_DEVICE_TREE="sandbox"
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 516e760dfa..ddf2cd6995 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -2,3 +2,4 @@
 +S:CONFIG_TEGRA=y
 +S:CONFIG_TEGRA20=y
 +S:CONFIG_TARGET_SEABOARD=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-seaboard"
diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig
index 465a75a6e3..9b76d0d124 100644
--- a/configs/smdk5250_defconfig
+++ b/configs/smdk5250_defconfig
@@ -2,3 +2,4 @@ CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_EXYNOS=y
 +S:CONFIG_TARGET_SMDK5250=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250"
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index 9dc43f27a6..8cf673d093 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -2,3 +2,4 @@ CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_EXYNOS=y
 +S:CONFIG_TARGET_SMDK5420=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420"
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index 2d59046f34..14ed793f6d 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -2,3 +2,4 @@ CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_EXYNOS=y
 +S:CONFIG_TARGET_SNOW=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow"
diff --git a/configs/tcm-bf518_defconfig b/configs/tcm-bf518_defconfig
index a9d5da01fa..0c9ae4d57e 100644
--- a/configs/tcm-bf518_defconfig
+++ b/configs/tcm-bf518_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_TCM_BF518=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/tcm-bf537_defconfig b/configs/tcm-bf537_defconfig
index fe9de13f36..6d604b6c9e 100644
--- a/configs/tcm-bf537_defconfig
+++ b/configs/tcm-bf537_defconfig
@@ -1,2 +1,3 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_TCM_BF537=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index e4a31cc054..fabd34a3f3 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -2,3 +2,4 @@
 +S:CONFIG_TEGRA=y
 +S:CONFIG_TEGRA30=y
 +S:CONFIG_TARGET_TEC_NG=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-tec-ng"
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index 62a9542d94..d3cafa7e4b 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -2,3 +2,4 @@
 +S:CONFIG_TEGRA=y
 +S:CONFIG_TEGRA20=y
 +S:CONFIG_TARGET_TEC=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-tec"
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index fa82724102..1b98b739da 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -1,3 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
 CONFIG_TARGET_TRATS2=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2"
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index f888a514c1..901a014734 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -1,3 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
 CONFIG_TARGET_TRATS=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats"
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index 94f23e3ea4..0b2a6d0292 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -2,3 +2,4 @@
 +S:CONFIG_TEGRA=y
 +S:CONFIG_TEGRA20=y
 +S:CONFIG_TARGET_TRIMSLICE=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-trimslice"
diff --git a/configs/tseries_mmc_defconfig b/configs/tseries_mmc_defconfig
index ea70705a53..6eda869fbe 100644
--- a/configs/tseries_mmc_defconfig
+++ b/configs/tseries_mmc_defconfig
@@ -2,3 +2,4 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_TSERIES=y
+# CONFIG_CMD_CRC32 is not set
diff --git a/configs/tseries_nand_defconfig b/configs/tseries_nand_defconfig
index 599d52c2ec..bd06d83efd 100644
--- a/configs/tseries_nand_defconfig
+++ b/configs/tseries_nand_defconfig
@@ -2,3 +2,4 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_TSERIES=y
+# CONFIG_CMD_CRC32 is not set
diff --git a/configs/tseries_spi_defconfig b/configs/tseries_spi_defconfig
index 7e5702080e..32ccc4e007 100644
--- a/configs/tseries_spi_defconfig
+++ b/configs/tseries_spi_defconfig
@@ -2,3 +2,4 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_TSERIES=y
+# CONFIG_CMD_CRC32 is not set
diff --git a/configs/vct_platinum_onenand_small_defconfig b/configs/vct_platinum_onenand_small_defconfig
index f7b3a916e6..58c79955ab 100644
--- a/configs/vct_platinum_onenand_small_defconfig
+++ b/configs/vct_platinum_onenand_small_defconfig
@@ -1,3 +1,4 @@
 CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE"
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
+# CONFIG_CMD_CRC32 is not set
diff --git a/configs/vct_platinum_small_defconfig b/configs/vct_platinum_small_defconfig
index 15eef483de..f4f56c4f4c 100644
--- a/configs/vct_platinum_small_defconfig
+++ b/configs/vct_platinum_small_defconfig
@@ -1,3 +1,4 @@
 CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM,VCT_SMALL_IMAGE"
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
+# CONFIG_CMD_CRC32 is not set
diff --git a/configs/vct_platinumavc_onenand_small_defconfig b/configs/vct_platinumavc_onenand_small_defconfig
index e0e8e445a3..31b4c9a8d6 100644
--- a/configs/vct_platinumavc_onenand_small_defconfig
+++ b/configs/vct_platinumavc_onenand_small_defconfig
@@ -1,3 +1,4 @@
 CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE"
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
+# CONFIG_CMD_CRC32 is not set
diff --git a/configs/vct_platinumavc_small_defconfig b/configs/vct_platinumavc_small_defconfig
index d8209d1e1a..23f6561b34 100644
--- a/configs/vct_platinumavc_small_defconfig
+++ b/configs/vct_platinumavc_small_defconfig
@@ -1,3 +1,4 @@
 CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC,VCT_SMALL_IMAGE"
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
+# CONFIG_CMD_CRC32 is not set
diff --git a/configs/vct_premium_onenand_small_defconfig b/configs/vct_premium_onenand_small_defconfig
index 220f87586c..354793edc8 100644
--- a/configs/vct_premium_onenand_small_defconfig
+++ b/configs/vct_premium_onenand_small_defconfig
@@ -1,3 +1,4 @@
 CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE"
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
+# CONFIG_CMD_CRC32 is not set
diff --git a/configs/vct_premium_small_defconfig b/configs/vct_premium_small_defconfig
index 5335472e5e..a23ddb7e21 100644
--- a/configs/vct_premium_small_defconfig
+++ b/configs/vct_premium_small_defconfig
@@ -1,3 +1,4 @@
 CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM,VCT_SMALL_IMAGE"
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
+# CONFIG_CMD_CRC32 is not set
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index dfc54078ed..c12dae933f 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -2,3 +2,4 @@
 +S:CONFIG_TEGRA=y
 +S:CONFIG_TEGRA124=y
 +S:CONFIG_TARGET_VENICE2=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2"
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index 845e24173c..f62ab6b17a 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -2,3 +2,4 @@
 +S:CONFIG_TEGRA=y
 +S:CONFIG_TEGRA20=y
 +S:CONFIG_TARGET_VENTANA=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-ventana"
diff --git a/configs/vexpress_aemv8a_defconfig b/configs/vexpress_aemv8a_defconfig
index a335abcf78..b463a333bc 100644
--- a/configs/vexpress_aemv8a_defconfig
+++ b/configs/vexpress_aemv8a_defconfig
@@ -1,3 +1,3 @@
-CONFIG_SYS_EXTRA_OPTIONS="ARM64"
 CONFIG_ARM=y
 CONFIG_TARGET_VEXPRESS_AEMV8A=y
+CONFIG_DEFAULT_DEVICE_TREE="vexpress64"
diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig
index e6dd8e7224..0035ccdaec 100644
--- a/configs/vexpress_aemv8a_semi_defconfig
+++ b/configs/vexpress_aemv8a_semi_defconfig
@@ -1,3 +1,4 @@
-CONFIG_SYS_EXTRA_OPTIONS="ARM64,SEMIHOSTING,BASE_FVP"
+CONFIG_SYS_EXTRA_OPTIONS="SEMIHOSTING,BASE_FVP"
 CONFIG_ARM=y
-CONFIG_TARGET_VEXPRESS_AEMV8A_SEMI=y
+CONFIG_TARGET_VEXPRESS_AEMV8A=y
+CONFIG_DEFAULT_DEVICE_TREE="vexpress64"
diff --git a/configs/whistler_defconfig b/configs/whistler_defconfig
index 8c07c184a9..9553eb8664 100644
--- a/configs/whistler_defconfig
+++ b/configs/whistler_defconfig
@@ -2,3 +2,4 @@
 +S:CONFIG_TEGRA=y
 +S:CONFIG_TEGRA20=y
 +S:CONFIG_TARGET_WHISTLER=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-whistler"
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index 3aedb350f6..9588849bb5 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -2,3 +2,5 @@ CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ZYNQ=y
 +S:CONFIG_TARGET_ZYNQ_MICROZED=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
diff --git a/configs/zynq_zc70x_defconfig b/configs/zynq_zc70x_defconfig
index 04c8defaef..cf507308e9 100644
--- a/configs/zynq_zc70x_defconfig
+++ b/configs/zynq_zc70x_defconfig
@@ -2,3 +2,5 @@ CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ZYNQ=y
 +S:CONFIG_TARGET_ZYNQ_ZC70X=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 1178b40bad..8bb405d180 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -3,3 +3,5 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
 +S:CONFIG_ARM=y
 +S:CONFIG_ZYNQ=y
 +S:CONFIG_TARGET_ZYNQ_ZC770=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index 52c21219d9..0ba5da589e 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -3,3 +3,5 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
 +S:CONFIG_ARM=y
 +S:CONFIG_ZYNQ=y
 +S:CONFIG_TARGET_ZYNQ_ZC770=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index 836809a17c..13f8112a1b 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -3,3 +3,5 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
 +S:CONFIG_ARM=y
 +S:CONFIG_ZYNQ=y
 +S:CONFIG_TARGET_ZYNQ_ZC770=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 233790664e..eb057fae35 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -2,3 +2,5 @@ CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ZYNQ=y
 +S:CONFIG_TARGET_ZYNQ_ZED=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
diff --git a/disk/part.c b/disk/part.c
index ecc5e7e0bf..cfd77b0ff5 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -133,7 +133,7 @@ typedef lbaint_t lba512_t;
  * Overflowless variant of (block_count * mul_by / div_by)
  * when div_by > mul_by
  */
-static lba512_t lba512_muldiv (lba512_t block_count, lba512_t mul_by, lba512_t div_by)
+static lba512_t lba512_muldiv(lba512_t block_count, lba512_t mul_by, lba512_t div_by)
 {
 	lba512_t bc_quot, bc_rem;
 
@@ -215,7 +215,8 @@ void dev_print (block_dev_desc_t *dev_desc)
 
 		lba512 = (lba * (dev_desc->blksz/512));
 		/* round to 1 digit */
-		mb = lba512_muldiv(lba512, 10, 2048);	/* 2048 = (1024 * 1024) / 512 MB */
+		/* 2048 = (1024 * 1024) / 512 MB */
+		mb = lba512_muldiv(lba512, 10, 2048);
 
 		mb_quot	= mb / 10;
 		mb_rem	= mb - (10 * mb_quot);
@@ -248,7 +249,7 @@ void dev_print (block_dev_desc_t *dev_desc)
 
 #ifdef HAVE_BLOCK_DEVICE
 
-void init_part (block_dev_desc_t * dev_desc)
+void init_part(block_dev_desc_t *dev_desc)
 {
 #ifdef CONFIG_ISO_PARTITION
 	if (test_part_iso(dev_desc) == 0) {
@@ -295,7 +296,7 @@ void init_part (block_dev_desc_t * dev_desc)
 	defined(CONFIG_AMIGA_PARTITION) || \
 	defined(CONFIG_EFI_PARTITION)
 
-static void print_part_header (const char *type, block_dev_desc_t * dev_desc)
+static void print_part_header(const char *type, block_dev_desc_t *dev_desc)
 {
 	puts ("\nPartition Map for ");
 	switch (dev_desc->if_type) {
diff --git a/doc/README.android-fastboot b/doc/README.android-fastboot
index 404572729a..167760968f 100644
--- a/doc/README.android-fastboot
+++ b/doc/README.android-fastboot
@@ -6,8 +6,9 @@ Overview
 The protocol that is used over USB is described in
 README.android-fastboot-protocol in same directory.
 
-The current implementation does not yet support the flash and erase
-commands.
+The current implementation does not yet support the erase command or the
+"oem format" command, and there is minimal support for the flash command;
+it only supports eMMC devices.
 
 Client installation
 ===================
diff --git a/doc/README.clang b/doc/README.clang
index 9ad689f071..52495d3116 100644
--- a/doc/README.clang
+++ b/doc/README.clang
@@ -34,21 +34,21 @@ make HOSTCC=clang CC="clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrat
 FreeBSD 11 (Current):
 --------------------
 Since llvm 3.4 is currently in the base system, the integrated as is
-incapable of building U-Boot. Therefore gas from devel/arm-eabi-binutils
+incapable of building U-Boot. Therefore gas from devel/arm-gnueabi-binutils
 is used instead. It needs a symlinks to be picked up correctly though:
 
-ln -s /usr/local/bin/arm-eabi-as /usr/bin/arm-freebsd-eabi-as
+ln -s /usr/local/bin/arm-gnueabi-freebsd-as /usr/bin/arm-freebsd-eabi-as
 
 # The following commands compile U-Boot using the clang xdev toolchain.
 # NOTE: CROSS_COMPILE and target differ on purpose!
-export CROSS_COMPILE=arm-eabi-
+export CROSS_COMPILE=arm-gnueabi-freebsd-
 gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" rpi_b_defconfig
 gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0" -j8
 
 Given that u-boot will default to gcc, above commands can be
 simplified with a simple wrapper script, listed below.
 
-/usr/local/bin/arm-eabi-gcc
+/usr/local/bin/arm-gnueabi-freebsd-gcc
 ---
 #!/bin/sh
 
diff --git a/doc/README.imximage b/doc/README.imximage
index dcda2005af..27d3354569 100644
--- a/doc/README.imximage
+++ b/doc/README.imximage
@@ -120,7 +120,7 @@ Configuration command line syntax:
 				DATA 4 0x73FA88a0 0x200
 
 The processor support up to 60 register programming commands for IMXIMAGE_VERSION 1
-and 121 register programming commands for IMXIMAGE_VERSION 2.
+and 220 register programming commands for IMXIMAGE_VERSION 2.
 An error is generated if more commands are found in the configuration file.
 
 3. All commands are optional to program.
diff --git a/doc/git-mailrc b/doc/git-mailrc
index 0fba1003c4..35f2eb2fc1 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -63,6 +63,7 @@ alias sunxi          uboot, ijc, jwrdegoede
 alias tegra          uboot, sjg, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com>
 alias tegra2         tegra
 alias ti             uboot, trini
+alias uniphier       uboot, masahiro
 alias zynq           uboot, monstr
 
 alias avr32          uboot, abiessmann
diff --git a/drivers/Kconfig b/drivers/Kconfig
new file mode 100644
index 0000000000..128736dae3
--- /dev/null
+++ b/drivers/Kconfig
@@ -0,0 +1,51 @@
+menu "Device Drivers"
+
+source "drivers/core/Kconfig"
+
+source "drivers/pci/Kconfig"
+
+source "drivers/pcmcia/Kconfig"
+
+source "drivers/mtd/Kconfig"
+
+source "drivers/block/Kconfig"
+
+source "drivers/misc/Kconfig"
+
+source "drivers/net/Kconfig"
+
+source "drivers/input/Kconfig"
+
+source "drivers/serial/Kconfig"
+
+source "drivers/tpm/Kconfig"
+
+source "drivers/i2c/Kconfig"
+
+source "drivers/spi/Kconfig"
+
+source "drivers/gpio/Kconfig"
+
+source "drivers/power/Kconfig"
+
+source "drivers/hwmon/Kconfig"
+
+source "drivers/watchdog/Kconfig"
+
+source "drivers/video/Kconfig"
+
+source "drivers/sound/Kconfig"
+
+source "drivers/usb/Kconfig"
+
+source "drivers/dfu/Kconfig"
+
+source "drivers/mmc/Kconfig"
+
+source "drivers/rtc/Kconfig"
+
+source "drivers/dma/Kconfig"
+
+source "drivers/crypto/Kconfig"
+
+endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index b22b109404..d8361d95fd 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -1,3 +1,5 @@
+obj-$(CONFIG_DM) += core/
+obj-$(CONFIG_DM_DEMO) += demo/
 obj-$(CONFIG_BIOSEMU) += bios_emulator/
 obj-y += block/
 obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
@@ -16,3 +18,4 @@ obj-y += watchdog/
 obj-$(CONFIG_QE) += qe/
 obj-y += memory/
 obj-y += pwm/
+obj-y += input/
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index 15d65d77f3..29f478bfbe 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -864,6 +864,23 @@ u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt,
 	return blkcnt;
 }
 
+int sata_port_status(int dev, int port)
+{
+	struct sata_port_regs *port_mmio;
+	struct ahci_probe_ent *probe_ent = NULL;
+
+	if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
+		return -EINVAL;
+
+	if (sata_dev_desc[dev].priv == NULL)
+		return -ENODEV;
+
+	probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+	port_mmio = (struct sata_port_regs *)probe_ent->port[port].port_mmio;
+
+	return readl(&(port_mmio->ssts)) && SATA_PORT_SSTS_DET_MASK;
+}
+
 /*
  * SATA interface between low level driver and command layer
  */
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/core/Makefile b/drivers/core/Makefile
index 90b2a7f068..c7905b1440 100644
--- a/drivers/core/Makefile
+++ b/drivers/core/Makefile
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_DM)	:= device.o lists.o root.o uclass.o util.o
+obj-y := device.o lists.o root.o uclass.o util.o
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 166b0732ab..32e80e82b5 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -106,13 +106,18 @@ int device_bind(struct udevice *parent, struct driver *drv, const char *name,
 	 * a 'requested' sequence, and will be resolved (and ->seq updated)
 	 * when the device is probed.
 	 */
-	dev->req_seq = fdtdec_get_int(gd->fdt_blob, of_offset, "reg", -1);
 	dev->seq = -1;
+#ifdef CONFIG_OF_CONTROL
+	dev->req_seq = fdtdec_get_int(gd->fdt_blob, of_offset, "reg", -1);
+	if (!IS_ERR_VALUE(dev->req_seq))
+		dev->req_seq &= INT_MAX;
 	if (uc->uc_drv->name && of_offset != -1) {
 		fdtdec_get_alias_seq(gd->fdt_blob, uc->uc_drv->name, of_offset,
 				     &dev->req_seq);
 	}
-
+#else
+	dev->req_seq = -1;
+#endif
 	if (!dev->platdata && drv->platdata_auto_alloc_size)
 		dev->flags |= DM_FLAG_ALLOC_PDATA;
 
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index d9cac2296a..9a156bfd5e 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -297,10 +297,13 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 	unsigned char taxpd_mclk = 0;
 	/* Mode register set cycle time (tMRD). */
 	unsigned char tmrd_mclk;
+#if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
+	const unsigned int mclk_ps = get_memory_clk_period_ps();
+#endif
 
 #ifdef CONFIG_SYS_FSL_DDR4
 	/* tXP=max(4nCK, 6ns) */
-	int txp = max((get_memory_clk_period_ps() * 4), 6000); /* unit=ps */
+	int txp = max(mclk_ps * 4, 6000); /* unit=ps */
 	trwt_mclk = 2;
 	twrt_mclk = 1;
 	act_pd_exit_mclk = picos_to_mclk(txp);
@@ -311,16 +314,19 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 	 */
 	tmrd_mclk = max(24, picos_to_mclk(15000));
 #elif defined(CONFIG_SYS_FSL_DDR3)
+	unsigned int data_rate = get_ddr_freq(0);
+	int txp;
 	/*
 	 * (tXARD and tXARDS). Empirical?
 	 * The DDR3 spec has not tXARD,
 	 * we use the tXP instead of it.
-	 * tXP=max(3nCK, 7.5ns) for DDR3.
+	 * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
+	 *     max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
 	 * spec has not the tAXPD, we use
 	 * tAXPD=1, need design to confirm.
 	 */
-	int txp = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
-	unsigned int data_rate = get_ddr_freq(0);
+	txp = max(mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
+
 	tmrd_mclk = 4;
 	/* set the turnaround time */
 
@@ -578,6 +584,9 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	unsigned char cke_pls;
 	/* Window for four activates (tFAW) */
 	unsigned short four_act;
+#ifdef CONFIG_SYS_FSL_DDR3
+	const unsigned int mclk_ps = get_memory_clk_period_ps();
+#endif
 
 	/* FIXME add check that this must be less than acttorw_mclk */
 	add_lat_mclk = additive_latency;
@@ -619,10 +628,17 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 #ifdef CONFIG_SYS_FSL_DDR4
 	cpo = 0;
 	cke_pls = max(3, picos_to_mclk(5000));
+#elif defined(CONFIG_SYS_FSL_DDR3)
+	/*
+	 * cke pulse = max(3nCK, 7.5ns) for DDR3-800
+	 *             max(3nCK, 5.625ns) for DDR3-1066, 1333
+	 *             max(3nCK, 5ns) for DDR3-1600, 1866, 2133
+	 */
+	cke_pls = max(3, picos_to_mclk(mclk_ps > 1870 ? 7500 :
+				       (mclk_ps > 1245 ? 5625 : 5000)));
 #else
-	cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps);
+	cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
 #endif
-
 	four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
 
 	ddr->timing_cfg_2 = (0
@@ -1886,9 +1902,12 @@ static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
 	debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
 }
 
+/* This function needs to be called after set_ddr_sdram_cfg() is called */
 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
 			       const dimm_params_t *dimm_params)
 {
+	unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
+
 	ddr->dq_map_0 = ((dimm_params->dq_mapping[0] & 0x3F) << 26) |
 			((dimm_params->dq_mapping[1] & 0x3F) << 20) |
 			((dimm_params->dq_mapping[2] & 0x3F) << 14) |
@@ -1907,9 +1926,11 @@ static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
 			((dimm_params->dq_mapping[15] & 0x3F) << 8) |
 			((dimm_params->dq_mapping[16] & 0x3F) << 2);
 
+	/* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
 	ddr->dq_map_3 = ((dimm_params->dq_mapping[17] & 0x3F) << 26) |
 			((dimm_params->dq_mapping[8] & 0x3F) << 20) |
-			((dimm_params->dq_mapping[9] & 0x3F) << 14) |
+			(acc_ecc_en ? 0 :
+			 (dimm_params->dq_mapping[9] & 0x3F) << 14) |
 			dimm_params->dq_mapping_ors;
 
 	debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
@@ -2276,7 +2297,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	if (ip_rev > 0x40400)
 		unq_mrs_en = 1;
 
-	if (ip_rev > 0x40700)
+	if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
 		ddr->debug[18] = popts->cswl_override;
 
 	set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c
index 4745b7fb1b..2418dca6ab 100644
--- a/drivers/ddr/fsl/ddr4_dimm_params.c
+++ b/drivers/ddr/fsl/ddr4_dimm_params.c
@@ -113,7 +113,7 @@ compute_ranksize(const struct ddr4_spd_eeprom_s *spd)
 #define spd_to_ps(mtb, ftb)	\
 	(mtb * pdimm->mtb_ps + (ftb * pdimm->ftb_10th_ps) / 10)
 /*
- * ddr_compute_dimm_parameters for DDR3 SPD
+ * ddr_compute_dimm_parameters for DDR4 SPD
  *
  * Compute DIMM parameters based upon the SPD information in spd.
  * Writes the results to the dimm_params_t structure pointed by pdimm.
@@ -165,17 +165,17 @@ ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd,
 			  + pdimm->ec_sdram_width;
 	pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
 
-	/* These are the types defined by the JEDEC DDR3 SPD spec */
+	/* These are the types defined by the JEDEC SPD spec */
 	pdimm->mirrored_dimm = 0;
 	pdimm->registered_dimm = 0;
-	switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) {
-	case DDR3_SPD_MODULETYPE_RDIMM:
+	switch (spd->module_type & DDR4_SPD_MODULETYPE_MASK) {
+	case DDR4_SPD_MODULETYPE_RDIMM:
 		/* Registered/buffered DIMMs */
 		pdimm->registered_dimm = 1;
 		break;
 
-	case DDR3_SPD_MODULETYPE_UDIMM:
-	case DDR3_SPD_MODULETYPE_SO_DIMM:
+	case DDR4_SPD_MODULETYPE_UDIMM:
+	case DDR4_SPD_MODULETYPE_SO_DIMM:
 		/* Unbuffered DIMMs */
 		if (spd->mod_section.unbuffered.addr_mapping & 0x1)
 			pdimm->mirrored_dimm = 1;
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index bfc76b3485..e024db9ee2 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -216,7 +216,7 @@ step2:
 	 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 	 * Let's wait for 800ms
 	 */
-	bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+	bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 			>> SDRAM_CFG_DBW_SHIFT);
 	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 		(get_ddr_freq(0) >> 20)) << 2;
@@ -233,5 +233,4 @@ step2:
 
 	if (timeout <= 0)
 		printf("Waiting for D_INIT timeout. Memory may not work.\n");
-
 }
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index 6aa16b23dd..32ba6d820b 100644
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -517,7 +517,6 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
 		CTRL_OPTIONS(rcw_2),
 		CTRL_OPTIONS(ddr_cdr1),
 		CTRL_OPTIONS(ddr_cdr2),
-		CTRL_OPTIONS(tcke_clock_pulse_width_ps),
 		CTRL_OPTIONS(tfaw_window_four_activates_ps),
 		CTRL_OPTIONS(trwt_override),
 		CTRL_OPTIONS(trwt),
@@ -808,7 +807,6 @@ static void print_memctl_options(const memctl_options_t *popts)
 		CTRL_OPTIONS(rcw_2),
 		CTRL_OPTIONS_HEX(ddr_cdr1),
 		CTRL_OPTIONS_HEX(ddr_cdr2),
-		CTRL_OPTIONS(tcke_clock_pulse_width_ps),
 		CTRL_OPTIONS(tfaw_window_four_activates_ps),
 		CTRL_OPTIONS(trwt_override),
 		CTRL_OPTIONS(trwt),
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 5e001fcb99..b43b669e41 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -135,7 +135,7 @@ __attribute__((weak, alias("__get_spd")))
 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
 
 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
-		      unsigned int ctrl_num)
+		      unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
 {
 	unsigned int i;
 	unsigned int i2c_address = 0;
@@ -145,14 +145,14 @@ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 		return;
 	}
 
-	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+	for (i = 0; i < dimm_slots_per_ctrl; i++) {
 		i2c_address = spd_i2c_addr[ctrl_num][i];
 		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
 	}
 }
 #else
 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
-		      unsigned int ctrl_num)
+		      unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
 {
 }
 #endif /* SPD_EEPROM_ADDRESSx */
@@ -231,9 +231,11 @@ const char * step_to_string(unsigned int step) {
 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
 			  unsigned int dbw_cap_adj[])
 {
-	int i, j;
+	unsigned int i, j;
 	unsigned long long total_mem, current_mem_base, total_ctlr_mem;
 	unsigned long long rank_density, ctlr_density = 0;
+	unsigned int first_ctrl = pinfo->first_ctrl;
+	unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 
 	/*
 	 * If a reduced data width is requested, but the SPD
@@ -241,7 +243,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
 	 * computed dimm capacities accordingly before
 	 * assigning addresses.
 	 */
-	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+	for (i = first_ctrl; i <= last_ctrl; i++) {
 		unsigned int found = 0;
 
 		switch (pinfo->memctl_opts[i].data_bus_width) {
@@ -295,12 +297,12 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
 		debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
 	}
 
-	current_mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
+	current_mem_base = pinfo->mem_base;
 	total_mem = 0;
-	if (pinfo->memctl_opts[0].memctl_interleaving) {
-		rank_density = pinfo->dimm_params[0][0].rank_density >>
-					dbw_cap_adj[0];
-		switch (pinfo->memctl_opts[0].ba_intlv_ctl &
+	if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) {
+		rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >>
+					dbw_cap_adj[first_ctrl];
+		switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl &
 					FSL_DDR_CS0_CS1_CS2_CS3) {
 		case FSL_DDR_CS0_CS1_CS2_CS3:
 			ctlr_density = 4 * rank_density;
@@ -316,7 +318,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
 		}
 		debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
 			rank_density, ctlr_density);
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		for (i = first_ctrl; i <= last_ctrl; i++) {
 			if (pinfo->memctl_opts[i].memctl_interleaving) {
 				switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
 				case FSL_DDR_256B_INTERLEAVING:
@@ -372,7 +374,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
 		 * Simple linear assignment if memory
 		 * controllers are not interleaved.
 		 */
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		for (i = first_ctrl; i <= last_ctrl; i++) {
 			total_ctlr_mem = 0;
 			pinfo->common_timing_params[i].base_address =
 						current_mem_base;
@@ -408,18 +410,23 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 {
 	unsigned int i, j;
 	unsigned long long total_mem = 0;
-	int assert_reset;
+	int assert_reset = 0;
+	unsigned int first_ctrl =  pinfo->first_ctrl;
+	unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
+	__maybe_unused int retval;
+	__maybe_unused bool goodspd = false;
+	__maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl;
 
 	fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
 	common_timing_params_t *timing_params = pinfo->common_timing_params;
-	assert_reset = board_need_mem_reset();
+	if (pinfo->board_need_mem_reset)
+		assert_reset = pinfo->board_need_mem_reset();
 
 	/* data bus width capacity adjust shift amount */
 	unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
 
-	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+	for (i = first_ctrl; i <= last_ctrl; i++)
 		dbw_capacity_adjust[i] = 0;
-	}
 
 	debug("starting at step %u (%s)\n",
 	      start_step, step_to_string(start_step));
@@ -428,28 +435,28 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 	case STEP_GET_SPD:
 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 		/* STEP 1:  Gather all DIMM SPD data */
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-			fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
+		for (i = first_ctrl; i <= last_ctrl; i++) {
+			fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i,
+					dimm_slots_per_ctrl);
 		}
 
 	case STEP_COMPUTE_DIMM_PARMS:
 		/* STEP 2:  Compute DIMM parameters from SPD data */
 
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		for (i = first_ctrl; i <= last_ctrl; i++) {
 			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
-				unsigned int retval;
 				generic_spd_eeprom_t *spd =
 					&(pinfo->spd_installed_dimms[i][j]);
 				dimm_params_t *pdimm =
 					&(pinfo->dimm_params[i][j]);
-
 				retval = compute_dimm_parameters(spd, pdimm, i);
 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 				if (!i && !j && retval) {
 					printf("SPD error on controller %d! "
 					"Trying fallback to raw timing "
 					"calculation\n", i);
-					fsl_ddr_get_dimm_params(pdimm, i, j);
+					retval = fsl_ddr_get_dimm_params(pdimm,
+									 i, j);
 				}
 #else
 				if (retval == 2) {
@@ -463,13 +470,26 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 					debug("Warning: compute_dimm_parameters"
 					" non-zero return value for memctl=%u "
 					"dimm=%u\n", i, j);
+				} else {
+					goodspd = true;
 				}
 			}
 		}
+		if (!goodspd) {
+			/*
+			 * No valid SPD found
+			 * Throw an error if this is for main memory, i.e.
+			 * first_ctrl == 0. Otherwise, siliently return 0
+			 * as the memory size.
+			 */
+			if (first_ctrl == 0)
+				printf("Error: No valid SPD detected.\n");
 
+			return 0;
+		}
 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
 	case STEP_COMPUTE_DIMM_PARMS:
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		for (i = first_ctrl; i <= last_ctrl; i++) {
 			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 				dimm_params_t *pdimm =
 					&(pinfo->dimm_params[i][j]);
@@ -483,7 +503,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 		 * STEP 3: Compute a common set of timing parameters
 		 * suitable for all of the DIMMs on each memory controller
 		 */
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		for (i = first_ctrl; i <= last_ctrl; i++) {
 			debug("Computing lowest common DIMM"
 				" parameters for memctl=%u\n", i);
 			compute_lowest_common_dimm_parameters(
@@ -494,7 +514,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 
 	case STEP_GATHER_OPTS:
 		/* STEP 4:  Gather configuration requirements from user */
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		for (i = first_ctrl; i <= last_ctrl; i++) {
 			debug("Reloading memory controller "
 				"configuration options for memctl=%u\n", i);
 			/*
@@ -516,9 +536,13 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 			if (timing_params[i].all_dimms_registered)
 				assert_reset = 1;
 		}
-		if (assert_reset) {
-			debug("Asserting mem reset\n");
-			board_assert_mem_reset();
+		if (assert_reset && !size_only) {
+			if (pinfo->board_mem_reset) {
+				debug("Asserting mem reset\n");
+				pinfo->board_mem_reset();
+			} else {
+				debug("Asserting mem reset missing\n");
+			}
 		}
 
 	case STEP_ASSIGN_ADDRESSES:
@@ -530,7 +554,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 	case STEP_COMPUTE_REGS:
 		/* STEP 6:  compute controller register values */
 		debug("FSL Memory ctrl register computation\n");
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		for (i = first_ctrl; i <= last_ctrl; i++) {
 			if (timing_params[i].ndimms_present == 0) {
 				memset(&ddr_reg[i], 0,
 					sizeof(fsl_ddr_cfg_regs_t));
@@ -558,7 +582,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 		 */
 		unsigned int max_end = 0;
 
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		for (i = first_ctrl; i <= last_ctrl; i++) {
 			for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
 				fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
 				if (reg->cs[j].config & 0x80000000) {
@@ -578,53 +602,45 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 		}
 
 		total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
-			    0xFFFFFFULL) - CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
+			    0xFFFFFFULL) - pinfo->mem_base;
 	}
 
 	return total_mem;
 }
 
-/*
- * fsl_ddr_sdram() -- this is the main function to be called by
- *	initdram() in the board file.
- *
- * It returns amount of memory configured in bytes.
- */
-phys_size_t fsl_ddr_sdram(void)
+phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 {
-	unsigned int i;
+	unsigned int i, first_ctrl, last_ctrl;
 #ifdef CONFIG_PPC
 	unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
 #endif
 	unsigned long long total_memory;
-	fsl_ddr_info_t info;
-	int deassert_reset;
+	int deassert_reset = 0;
 
-	/* Reset info structure. */
-	memset(&info, 0, sizeof(fsl_ddr_info_t));
+	first_ctrl = pinfo->first_ctrl;
+	last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 
 	/* Compute it once normally. */
 #ifdef CONFIG_FSL_DDR_INTERACTIVE
 	if (tstc() && (getc() == 'd')) {	/* we got a key press of 'd' */
-		total_memory = fsl_ddr_interactive(&info, 0);
+		total_memory = fsl_ddr_interactive(pinfo, 0);
 	} else if (fsl_ddr_interactive_env_var_exists()) {
-		total_memory = fsl_ddr_interactive(&info, 1);
+		total_memory = fsl_ddr_interactive(pinfo, 1);
 	} else
 #endif
-		total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
+		total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0);
 
 	/* setup 3-way interleaving before enabling DDRC */
-	if (info.memctl_opts[0].memctl_interleaving) {
-		switch (info.memctl_opts[0].memctl_interleaving_mode) {
-		case FSL_DDR_3WAY_1KB_INTERLEAVING:
-		case FSL_DDR_3WAY_4KB_INTERLEAVING:
-		case FSL_DDR_3WAY_8KB_INTERLEAVING:
-			fsl_ddr_set_intl3r(
-				info.memctl_opts[0].memctl_interleaving_mode);
-			break;
-		default:
-			break;
-		}
+	switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) {
+	case FSL_DDR_3WAY_1KB_INTERLEAVING:
+	case FSL_DDR_3WAY_4KB_INTERLEAVING:
+	case FSL_DDR_3WAY_8KB_INTERLEAVING:
+		fsl_ddr_set_intl3r(
+			pinfo->memctl_opts[first_ctrl].
+			memctl_interleaving_mode);
+		break;
+	default:
+		break;
 	}
 
 	/*
@@ -637,14 +653,15 @@ phys_size_t fsl_ddr_sdram(void)
 	 * For non-registered DIMMs, initialization can go through but it is
 	 * also OK to follow the same flow.
 	 */
-	deassert_reset = board_need_mem_reset();
-	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-		if (info.common_timing_params[i].all_dimms_registered)
+	if (pinfo->board_need_mem_reset)
+		deassert_reset = pinfo->board_need_mem_reset();
+	for (i = first_ctrl; i <= last_ctrl; i++) {
+		if (pinfo->common_timing_params[i].all_dimms_registered)
 			deassert_reset = 1;
 	}
-	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+	for (i = first_ctrl; i <= last_ctrl; i++) {
 		debug("Programming controller %u\n", i);
-		if (info.common_timing_params[i].ndimms_present == 0) {
+		if (pinfo->common_timing_params[i].ndimms_present == 0) {
 			debug("No dimms present on controller %u; "
 					"skipping programming\n", i);
 			continue;
@@ -653,45 +670,58 @@ phys_size_t fsl_ddr_sdram(void)
 		 * The following call with step = 1 returns before enabling
 		 * the controller. It has to finish with step = 2 later.
 		 */
-		fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i,
+		fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,
 					deassert_reset ? 1 : 0);
 	}
 	if (deassert_reset) {
 		/* Use board FPGA or GPIO to deassert reset signal */
-		debug("Deasserting mem reset\n");
-		board_deassert_mem_reset();
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		if (pinfo->board_mem_de_reset) {
+			debug("Deasserting mem reset\n");
+			pinfo->board_mem_de_reset();
+		} else {
+			debug("Deasserting mem reset missing\n");
+		}
+		for (i = first_ctrl; i <= last_ctrl; i++) {
 			/* Call with step = 2 to continue initialization */
-			fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]),
+			fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]),
 						i, 2);
 		}
 	}
 
 #ifdef CONFIG_PPC
 	/* program LAWs */
-	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-		if (info.memctl_opts[i].memctl_interleaving) {
-			switch (info.memctl_opts[i].memctl_interleaving_mode) {
+	for (i = first_ctrl; i <= last_ctrl; i++) {
+		if (pinfo->memctl_opts[i].memctl_interleaving) {
+			switch (pinfo->memctl_opts[i].
+				memctl_interleaving_mode) {
 			case FSL_DDR_CACHE_LINE_INTERLEAVING:
 			case FSL_DDR_PAGE_INTERLEAVING:
 			case FSL_DDR_BANK_INTERLEAVING:
 			case FSL_DDR_SUPERBANK_INTERLEAVING:
+				if (i % 2)
+					break;
 				if (i == 0) {
 					law_memctl = LAW_TRGT_IF_DDR_INTRLV;
-					fsl_ddr_set_lawbar(&info.common_timing_params[i],
-						law_memctl, i);
-				} else if (i == 2) {
-					law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
-					fsl_ddr_set_lawbar(&info.common_timing_params[i],
+					fsl_ddr_set_lawbar(
+						&pinfo->common_timing_params[i],
 						law_memctl, i);
 				}
+#if CONFIG_NUM_DDR_CONTROLLERS > 3
+				else if (i == 2) {
+					law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
+					fsl_ddr_set_lawbar(
+						&pinfo->common_timing_params[i],
+						law_memctl, i);
+				}
+#endif
 				break;
 			case FSL_DDR_3WAY_1KB_INTERLEAVING:
 			case FSL_DDR_3WAY_4KB_INTERLEAVING:
 			case FSL_DDR_3WAY_8KB_INTERLEAVING:
 				law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
 				if (i == 0) {
-					fsl_ddr_set_lawbar(&info.common_timing_params[i],
+					fsl_ddr_set_lawbar(
+						&pinfo->common_timing_params[i],
 						law_memctl, i);
 				}
 				break;
@@ -700,7 +730,8 @@ phys_size_t fsl_ddr_sdram(void)
 			case FSL_DDR_4WAY_8KB_INTERLEAVING:
 				law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
 				if (i == 0)
-					fsl_ddr_set_lawbar(&info.common_timing_params[i],
+					fsl_ddr_set_lawbar(
+						&pinfo->common_timing_params[i],
 						law_memctl, i);
 				/* place holder for future 4-way interleaving */
 				break;
@@ -724,8 +755,8 @@ phys_size_t fsl_ddr_sdram(void)
 			default:
 				break;
 			}
-			fsl_ddr_set_lawbar(&info.common_timing_params[i],
-					law_memctl, i);
+			fsl_ddr_set_lawbar(&pinfo->common_timing_params[i],
+					   law_memctl, i);
 		}
 	}
 #endif
@@ -734,7 +765,7 @@ phys_size_t fsl_ddr_sdram(void)
 
 #if !defined(CONFIG_PHYS_64BIT)
 	/* Check for 4G or more.  Bad. */
-	if (total_memory >= (1ull << 32)) {
+	if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) {
 		puts("Detected ");
 		print_size(total_memory, " of memory\n");
 		printf("       This U-Boot only supports < 4G of DDR\n");
@@ -748,8 +779,56 @@ phys_size_t fsl_ddr_sdram(void)
 }
 
 /*
- * fsl_ddr_sdram_size() - This function only returns the size of the total
- * memory without setting ddr control registers.
+ * fsl_ddr_sdram(void) -- this is the main function to be
+ * called by initdram() in the board file.
+ *
+ * It returns amount of memory configured in bytes.
+ */
+phys_size_t fsl_ddr_sdram(void)
+{
+	fsl_ddr_info_t info;
+
+	/* Reset info structure. */
+	memset(&info, 0, sizeof(fsl_ddr_info_t));
+	info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
+	info.first_ctrl = 0;
+	info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
+	info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
+	info.board_need_mem_reset = board_need_mem_reset;
+	info.board_mem_reset = board_assert_mem_reset;
+	info.board_mem_de_reset = board_deassert_mem_reset;
+
+	return __fsl_ddr_sdram(&info);
+}
+
+#ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
+phys_size_t fsl_other_ddr_sdram(unsigned long long base,
+				unsigned int first_ctrl,
+				unsigned int num_ctrls,
+				unsigned int dimm_slots_per_ctrl,
+				int (*board_need_reset)(void),
+				void (*board_reset)(void),
+				void (*board_de_reset)(void))
+{
+	fsl_ddr_info_t info;
+
+	/* Reset info structure. */
+	memset(&info, 0, sizeof(fsl_ddr_info_t));
+	info.mem_base = base;
+	info.first_ctrl = first_ctrl;
+	info.num_ctrls = num_ctrls;
+	info.dimm_slots_per_ctrl = dimm_slots_per_ctrl;
+	info.board_need_mem_reset = board_need_reset;
+	info.board_mem_reset = board_reset;
+	info.board_mem_de_reset = board_de_reset;
+
+	return __fsl_ddr_sdram(&info);
+}
+#endif
+
+/*
+ * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the
+ * size of the total memory without setting ddr control registers.
  */
 phys_size_t
 fsl_ddr_sdram_size(void)
@@ -758,6 +837,11 @@ fsl_ddr_sdram_size(void)
 	unsigned long long total_memory = 0;
 
 	memset(&info, 0 , sizeof(fsl_ddr_info_t));
+	info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
+	info.first_ctrl = 0;
+	info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
+	info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
+	info.board_need_mem_reset = NULL;
 
 	/* Compute it once normally. */
 	total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index 5986e1a0b9..6d098d1fa2 100644
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -777,10 +777,6 @@ unsigned int populate_memctl_options(int all_dimms_registered,
 	 */
 	popts->bstopre = 0x100;
 
-	/* Minimum CKE pulse width -- tCKE(MIN) */
-	popts->tcke_clock_pulse_width_ps
-		= mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
-
 	/*
 	 * Window for four activates -- tFAW
 	 *
@@ -1065,18 +1061,21 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo)
 	unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
 	unsigned long long check_rank_density;
 	struct dimm_params_s *dimm;
+	int first_ctrl = pinfo->first_ctrl;
+	int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
+
 	/*
 	 * Check if all controllers are configured for memory
 	 * controller interleaving. Identical dimms are recommended. At least
 	 * the size, row and col address should be checked.
 	 */
 	j = 0;
-	check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
-	check_rank_density = pinfo->dimm_params[0][0].rank_density;
-	check_n_row_addr =  pinfo->dimm_params[0][0].n_row_addr;
-	check_n_col_addr = pinfo->dimm_params[0][0].n_col_addr;
-	check_intlv = pinfo->memctl_opts[0].memctl_interleaving_mode;
-	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+	check_n_ranks = pinfo->dimm_params[first_ctrl][0].n_ranks;
+	check_rank_density = pinfo->dimm_params[first_ctrl][0].rank_density;
+	check_n_row_addr =  pinfo->dimm_params[first_ctrl][0].n_row_addr;
+	check_n_col_addr = pinfo->dimm_params[first_ctrl][0].n_col_addr;
+	check_intlv = pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode;
+	for (i = first_ctrl; i <= last_ctrl; i++) {
 		dimm = &pinfo->dimm_params[i][0];
 		if (!pinfo->memctl_opts[i].memctl_interleaving) {
 			continue;
@@ -1094,7 +1093,7 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo)
 
 	}
 	if (intlv_invalid) {
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+		for (i = first_ctrl; i <= last_ctrl; i++)
 			pinfo->memctl_opts[i].memctl_interleaving = 0;
 		printf("Not all DIMMs are identical. "
 			"Memory controller interleaving disabled.\n");
@@ -1123,10 +1122,10 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo)
 		}
 		debug("%d of %d controllers are interleaving.\n", j, k);
 		if (j && (j != k)) {
-			for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+			for (i = first_ctrl; i <= last_ctrl; i++)
 				pinfo->memctl_opts[i].memctl_interleaving = 0;
-			printf("Not all controllers have compatible "
-				"interleaving mode. All disabled.\n");
+			if ((last_ctrl - first_ctrl) > 1)
+				puts("Not all controllers have compatible interleaving mode. All disabled.\n");
 		}
 	}
 	debug("Checking interleaving options completed\n");
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index 7a22aa3988..58b519b403 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -149,7 +149,7 @@ u32 fsl_ddr_get_intl3r(void)
 	return val;
 }
 
-void board_add_ram_info(int use_default)
+void print_ddr_info(unsigned int start_ctrl)
 {
 	struct ccsr_ddr __iomem *ddr =
 		(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
@@ -164,17 +164,25 @@ void board_add_ram_info(int use_default)
 	int cas_lat;
 
 #if CONFIG_NUM_DDR_CONTROLLERS >= 2
-	if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+	if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
+	    (start_ctrl == 1)) {
 		ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
 		sdram_cfg = ddr_in32(&ddr->sdram_cfg);
 	}
 #endif
 #if CONFIG_NUM_DDR_CONTROLLERS >= 3
-	if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+	if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
+	    (start_ctrl == 2)) {
 		ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
 		sdram_cfg = ddr_in32(&ddr->sdram_cfg);
 	}
 #endif
+
+	if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+		puts(" (DDR not enabled)\n");
+		return;
+	}
+
 	puts(" (DDR");
 	switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
 		SDRAM_CFG_SDRAM_TYPE_SHIFT) {
@@ -241,7 +249,7 @@ void board_add_ram_info(int use_default)
 #endif
 #endif
 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
-	if (cs0_config & 0x20000000) {
+	if ((cs0_config & 0x20000000) && (start_ctrl == 0)) {
 		puts("\n");
 		puts("       DDR Controller Interleaving Mode: ");
 
@@ -290,3 +298,13 @@ void board_add_ram_info(int use_default)
 		}
 	}
 }
+
+void __weak detail_board_ddr_info(void)
+{
+	print_ddr_info(0);
+}
+
+void board_add_ram_info(int use_default)
+{
+	detail_board_ddr_info();
+}
diff --git a/drivers/demo/Makefile b/drivers/demo/Makefile
index baaa2baa4e..171ddf3678 100644
--- a/drivers/demo/Makefile
+++ b/drivers/demo/Makefile
@@ -4,6 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_DM_DEMO) += demo-uclass.o demo-pdata.o
+obj-y += demo-uclass.o demo-pdata.o
 obj-$(CONFIG_DM_DEMO_SIMPLE) += demo-simple.o
 obj-$(CONFIG_DM_DEMO_SHAPE) += demo-shape.o
diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index 45e49c7faf..7ef7f12b0a 100644
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -96,7 +96,7 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
 	uint xfer_size;
 
 	while (count) {
-		xfer_size = MIN(FSL_DMA_MAX_SIZE, count);
+		xfer_size = min(FSL_DMA_MAX_SIZE, count);
 
 		out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF));
 		out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF));
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c
index fe66ce2a4a..19fbe596f4 100644
--- a/drivers/i2c/ihs_i2c.c
+++ b/drivers/i2c/ihs_i2c.c
@@ -84,7 +84,7 @@ static int ihs_i2c_address(uchar chip, uint addr, int alen, bool hold_bus)
 	int shift = (alen-1) * 8;
 
 	while (alen) {
-		int transfer = MIN(alen, 2);
+		int transfer = min(alen, 2);
 		uchar buf[2];
 		bool is_last = alen <= transfer;
 
@@ -113,7 +113,7 @@ static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, uint addr,
 		return 1;
 
 	while (len) {
-		int transfer = MIN(len, 2);
+		int transfer = min(len, 2);
 
 		if (ihs_i2c_transfer(chip, buffer, transfer, read,
 				     len <= transfer))
diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 97d0389d9d..2640607248 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -610,7 +610,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 #endif
 
 	cfg->cfg.f_min = 400000;
-	cfg->cfg.f_max = MIN(gd->arch.sdhc_clk, 52000000);
+	cfg->cfg.f_max = min(gd->arch.sdhc_clk, 52000000);
 
 	cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
new file mode 100644
index 0000000000..415ab4eba9
--- /dev/null
+++ b/drivers/mtd/Kconfig
@@ -0,0 +1 @@
+source "drivers/mtd/nand/Kconfig"
diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index e0b7e3af72..cb27ff22be 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -803,7 +803,7 @@ void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset,
 	*truncated = 0;
 	*len_incl_bad = 0;
 
-	if (!mtd->block_isbad) {
+	if (!mtd->_block_isbad) {
 		*len_incl_bad = length;
 		return;
 	}
@@ -819,7 +819,7 @@ void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset,
 
 		block_len = mtd->erasesize - (offset & (mtd->erasesize - 1));
 
-		if (!mtd->block_isbad(mtd, offset & ~(mtd->erasesize - 1)))
+		if (!mtd->_block_isbad(mtd, offset & ~(mtd->erasesize - 1)))
 			len_excl_bad += block_len;
 
 		*len_incl_bad += block_len;
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
new file mode 100644
index 0000000000..75c2c065c8
--- /dev/null
+++ b/drivers/mtd/nand/Kconfig
@@ -0,0 +1,42 @@
+menu "NAND Device Support"
+
+if !SPL_BUILD
+
+config NAND_DENALI
+	bool "Support Denali NAND controller"
+	help
+	  Enable support for the Denali NAND controller.
+
+config SYS_NAND_DENALI_64BIT
+	bool "Use 64-bit variant of Denali NAND controller"
+	depends on NAND_DENALI
+	help
+	  The Denali NAND controller IP has some variations in terms of
+	  the bus interface.  The DMA setup sequence is completely differenct
+	  between 32bit / 64bit AXI bus variants.
+
+	  If your Denali NAND controller is the 64-bit variant, say Y.
+	  Otherwise (32 bit), say N.
+
+config NAND_DENALI_SPARE_AREA_SKIP_BYTES
+	int "Number of bytes skipped in OOB area"
+	depends on NAND_DENALI
+	range 0 63
+	help
+	  This option specifies the number of bytes to skip from the beginning
+	  of OOB area before last ECC sector data starts.  This is potentially
+	  used to preserve the bad block marker in the OOB area.
+
+endif
+
+if SPL_BUILD
+
+config SPL_NAND_DENALI
+	bool "Support Denali NAND controller for SPL"
+	help
+	  This is a small implementation of the Denali NAND controller
+	  for use on SPL.
+
+endif
+
+endmenu
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index bf1312a373..47eb34f9c5 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -12,6 +12,7 @@ NORMAL_DRIVERS=y
 endif
 
 obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
+obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o
 obj-$(CONFIG_SPL_NAND_DOCG4) += docg4_spl.o
 obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
 obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
@@ -42,6 +43,7 @@ obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
 obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
 obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
 obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
+obj-$(CONFIG_NAND_DENALI) += denali.o
 obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
 obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
 obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c
index ce65d8e12b..bf8b2ee16a 100644
--- a/drivers/mtd/nand/am335x_spl_bch.c
+++ b/drivers/mtd/nand/am335x_spl_bch.c
@@ -64,14 +64,18 @@ static int nand_command(int block, int page, uint32_t offs,
 		       NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
 	hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
 	/* Row address */
-	hwctrl(&nand_info[0], (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
-	hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
+	if (cmd != NAND_CMD_RNDOUT) {
+		hwctrl(&nand_info[0], (page_addr & 0xff),
+		       NAND_CTRL_ALE); /* A[19:12] */
+		hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
 		       NAND_CTRL_ALE); /* A[27:20] */
 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
-	/* One more address cycle for devices > 128MiB */
-	hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
+		/* One more address cycle for devices > 128MiB */
+		hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
 		       NAND_CTRL_ALE); /* A[31:28] */
 #endif
+	}
+
 	hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
 	if (cmd == NAND_CMD_READ0) {
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index e73834d2ef..9114a86da2 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -164,7 +164,7 @@ static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
 
 	/* Fill odd syndromes */
 	for (i = 0; i < host->pmecc_corr_cap; i++) {
-		value = readl(&host->pmecc->rem_port[sector].rem[i / 2]);
+		value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
 		if (i & 1)
 			value >>= 16;
 		value &= 0xffff;
@@ -392,10 +392,11 @@ static int pmecc_err_location(struct mtd_info *mtd)
 	int16_t *smu = host->pmecc_smu;
 	int timeout = PMECC_MAX_TIMEOUT_US;
 
-	writel(PMERRLOC_DISABLE, &host->pmerrloc->eldis);
+	pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
 
 	for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
-		writel(smu[(cap + 1) * num + i], &host->pmerrloc->sigma[i]);
+		pmecc_writel(host->pmerrloc, sigma[i],
+			     smu[(cap + 1) * num + i]);
 		err_nbr++;
 	}
 
@@ -403,12 +404,12 @@ static int pmecc_err_location(struct mtd_info *mtd)
 	if (sector_size == 1024)
 		val |= PMERRLOC_ELCFG_SECTOR_1024;
 
-	writel(val, &host->pmerrloc->elcfg);
-	writel(sector_size * 8 + host->pmecc_degree * cap,
-			&host->pmerrloc->elen);
+	pmecc_writel(host->pmerrloc, elcfg, val);
+	pmecc_writel(host->pmerrloc, elen,
+		     sector_size * 8 + host->pmecc_degree * cap);
 
 	while (--timeout) {
-		if (readl(&host->pmerrloc->elisr) & PMERRLOC_CALC_DONE)
+		if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
 			break;
 		WATCHDOG_RESET();
 		udelay(1);
@@ -419,7 +420,7 @@ static int pmecc_err_location(struct mtd_info *mtd)
 		return -1;
 	}
 
-	roots_nbr = (readl(&host->pmerrloc->elisr) & PMERRLOC_ERR_NUM_MASK)
+	roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
 			>> 8;
 	/* Number of roots == degree of smu hence <= cap */
 	if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
@@ -443,7 +444,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 	sector_size = host->pmecc_sector_size;
 
 	while (err_nbr) {
-		tmp = readl(&host->pmerrloc->el[i]) - 1;
+		tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
 		byte_pos = tmp / 8;
 		bit_pos  = tmp % 8;
 
@@ -597,7 +598,7 @@ static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 
 			pos = i * host->pmecc_bytes_per_sector + j;
 			chip->oob_poi[eccpos[pos]] =
-				readb(&host->pmecc->ecc_port[i].ecc[j]);
+				pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
 		}
 	}
 	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
@@ -881,6 +882,7 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
 		return -ENOMEM;
 	}
 
+	nand->options |= NAND_NO_SUBPAGE_WRITE;
 	nand->ecc.read_page = atmel_nand_pmecc_read_page;
 	nand->ecc.write_page = atmel_nand_pmecc_write_page;
 	nand->ecc.strength = cap;
diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h
index 55d7711c8b..92d4ec59fd 100644
--- a/drivers/mtd/nand/atmel_nand_ecc.h
+++ b/drivers/mtd/nand/atmel_nand_ecc.h
@@ -34,6 +34,9 @@
 #define pmecc_readl(addr, reg) \
 	readl(&addr->reg)
 
+#define pmecc_readb(addr, reg) \
+	readb(&addr->reg)
+
 #define pmecc_writel(addr, reg, value) \
 	writel((value), &addr->reg)
 
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 02a1130af9..41689b5165 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -363,6 +363,7 @@ static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
  * @raw: use _raw version of write_page
  */
 static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+				   uint32_t offset, int data_len,
 				   const uint8_t *buf, int oob_required,
 				   int page, int cached, int raw)
 {
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
new file mode 100644
index 0000000000..ba3de1a635
--- /dev/null
+++ b/drivers/mtd/nand/denali.c
@@ -0,0 +1,1205 @@
+/*
+ * Copyright (C) 2014       Panasonic Corporation
+ * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
+ * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <nand.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+
+#include "denali.h"
+
+#define NAND_DEFAULT_TIMINGS	-1
+
+static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
+
+/* We define a macro here that combines all interrupts this driver uses into
+ * a single constant value, for convenience. */
+#define DENALI_IRQ_ALL	(INTR_STATUS__DMA_CMD_COMP | \
+			INTR_STATUS__ECC_TRANSACTION_DONE | \
+			INTR_STATUS__ECC_ERR | \
+			INTR_STATUS__PROGRAM_FAIL | \
+			INTR_STATUS__LOAD_COMP | \
+			INTR_STATUS__PROGRAM_COMP | \
+			INTR_STATUS__TIME_OUT | \
+			INTR_STATUS__ERASE_FAIL | \
+			INTR_STATUS__RST_COMP | \
+			INTR_STATUS__ERASE_COMP | \
+			INTR_STATUS__ECC_UNCOR_ERR | \
+			INTR_STATUS__INT_ACT | \
+			INTR_STATUS__LOCKED_BLK)
+
+/* indicates whether or not the internal value for the flash bank is
+ * valid or not */
+#define CHIP_SELECT_INVALID	-1
+
+#define SUPPORT_8BITECC		1
+
+/*
+ * this macro allows us to convert from an MTD structure to our own
+ * device context (denali) structure.
+ */
+#define mtd_to_denali(m) (((struct nand_chip *)mtd->priv)->priv)
+
+/* These constants are defined by the driver to enable common driver
+ * configuration options. */
+#define SPARE_ACCESS		0x41
+#define MAIN_ACCESS		0x42
+#define MAIN_SPARE_ACCESS	0x43
+
+#define DENALI_UNLOCK_START	0x10
+#define DENALI_UNLOCK_END	0x11
+#define DENALI_LOCK		0x21
+#define DENALI_LOCK_TIGHT	0x31
+#define DENALI_BUFFER_LOAD	0x60
+#define DENALI_BUFFER_WRITE	0x62
+
+#define DENALI_READ	0
+#define DENALI_WRITE	0x100
+
+/* types of device accesses. We can issue commands and get status */
+#define COMMAND_CYCLE	0
+#define ADDR_CYCLE	1
+#define STATUS_CYCLE	2
+
+/* this is a helper macro that allows us to
+ * format the bank into the proper bits for the controller */
+#define BANK(x) ((x) << 24)
+
+/* Interrupts are cleared by writing a 1 to the appropriate status bit */
+static inline void clear_interrupt(struct denali_nand_info *denali,
+							uint32_t irq_mask)
+{
+	uint32_t intr_status_reg;
+
+	intr_status_reg = INTR_STATUS(denali->flash_bank);
+
+	writel(irq_mask, denali->flash_reg + intr_status_reg);
+}
+
+static uint32_t read_interrupt_status(struct denali_nand_info *denali)
+{
+	uint32_t intr_status_reg;
+
+	intr_status_reg = INTR_STATUS(denali->flash_bank);
+
+	return readl(denali->flash_reg + intr_status_reg);
+}
+
+static void clear_interrupts(struct denali_nand_info *denali)
+{
+	uint32_t status;
+
+	status = read_interrupt_status(denali);
+	clear_interrupt(denali, status);
+
+	denali->irq_status = 0;
+}
+
+static void denali_irq_enable(struct denali_nand_info *denali,
+							uint32_t int_mask)
+{
+	int i;
+
+	for (i = 0; i < denali->max_banks; ++i)
+		writel(int_mask, denali->flash_reg + INTR_EN(i));
+}
+
+static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
+{
+	unsigned long timeout = 1000000;
+	uint32_t intr_status;
+
+	do {
+		intr_status = read_interrupt_status(denali) & DENALI_IRQ_ALL;
+		if (intr_status & irq_mask) {
+			denali->irq_status &= ~irq_mask;
+			/* our interrupt was detected */
+			break;
+		}
+		udelay(1);
+		timeout--;
+	} while (timeout != 0);
+
+	if (timeout == 0) {
+		/* timeout */
+		printf("Denali timeout with interrupt status %08x\n",
+		       read_interrupt_status(denali));
+		intr_status = 0;
+	}
+	return intr_status;
+}
+
+/*
+ * Certain operations for the denali NAND controller use an indexed mode to
+ * read/write data. The operation is performed by writing the address value
+ * of the command to the device memory followed by the data. This function
+ * abstracts this common operation.
+*/
+static void index_addr(struct denali_nand_info *denali,
+				uint32_t address, uint32_t data)
+{
+	writel(address, denali->flash_mem + INDEX_CTRL_REG);
+	writel(data, denali->flash_mem + INDEX_DATA_REG);
+}
+
+/* Perform an indexed read of the device */
+static void index_addr_read_data(struct denali_nand_info *denali,
+				 uint32_t address, uint32_t *pdata)
+{
+	writel(address, denali->flash_mem + INDEX_CTRL_REG);
+	*pdata = readl(denali->flash_mem + INDEX_DATA_REG);
+}
+
+/* We need to buffer some data for some of the NAND core routines.
+ * The operations manage buffering that data. */
+static void reset_buf(struct denali_nand_info *denali)
+{
+	denali->buf.head = 0;
+	denali->buf.tail = 0;
+}
+
+static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
+{
+	denali->buf.buf[denali->buf.tail++] = byte;
+}
+
+/* resets a specific device connected to the core */
+static void reset_bank(struct denali_nand_info *denali)
+{
+	uint32_t irq_status;
+	uint32_t irq_mask = INTR_STATUS__RST_COMP |
+			    INTR_STATUS__TIME_OUT;
+
+	clear_interrupts(denali);
+
+	writel(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
+
+	irq_status = wait_for_irq(denali, irq_mask);
+	if (irq_status & INTR_STATUS__TIME_OUT)
+		debug("reset bank failed.\n");
+}
+
+/* Reset the flash controller */
+static uint32_t denali_nand_reset(struct denali_nand_info *denali)
+{
+	uint32_t i;
+
+	for (i = 0; i < denali->max_banks; i++)
+		writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
+		       denali->flash_reg + INTR_STATUS(i));
+
+	for (i = 0; i < denali->max_banks; i++) {
+		writel(1 << i, denali->flash_reg + DEVICE_RESET);
+		while (!(readl(denali->flash_reg + INTR_STATUS(i)) &
+			(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
+			if (readl(denali->flash_reg + INTR_STATUS(i)) &
+				INTR_STATUS__TIME_OUT)
+				debug("NAND Reset operation timed out on bank"
+				      " %d\n", i);
+	}
+
+	for (i = 0; i < denali->max_banks; i++)
+		writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
+		       denali->flash_reg + INTR_STATUS(i));
+
+	return 0;
+}
+
+/*
+ * this routine calculates the ONFI timing values for a given mode and
+ * programs the clocking register accordingly. The mode is determined by
+ * the get_onfi_nand_para routine.
+ */
+static void nand_onfi_timing_set(struct denali_nand_info *denali,
+								uint16_t mode)
+{
+	uint32_t trea[6] = {40, 30, 25, 20, 20, 16};
+	uint32_t trp[6] = {50, 25, 17, 15, 12, 10};
+	uint32_t treh[6] = {30, 15, 15, 10, 10, 7};
+	uint32_t trc[6] = {100, 50, 35, 30, 25, 20};
+	uint32_t trhoh[6] = {0, 15, 15, 15, 15, 15};
+	uint32_t trloh[6] = {0, 0, 0, 0, 5, 5};
+	uint32_t tcea[6] = {100, 45, 30, 25, 25, 25};
+	uint32_t tadl[6] = {200, 100, 100, 100, 70, 70};
+	uint32_t trhw[6] = {200, 100, 100, 100, 100, 100};
+	uint32_t trhz[6] = {200, 100, 100, 100, 100, 100};
+	uint32_t twhr[6] = {120, 80, 80, 60, 60, 60};
+	uint32_t tcs[6] = {70, 35, 25, 25, 20, 15};
+
+	uint32_t tclsrising = 1;
+	uint32_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
+	uint32_t dv_window = 0;
+	uint32_t en_lo, en_hi;
+	uint32_t acc_clks;
+	uint32_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
+
+	en_lo = DIV_ROUND_UP(trp[mode], CLK_X);
+	en_hi = DIV_ROUND_UP(treh[mode], CLK_X);
+	if ((en_hi * CLK_X) < (treh[mode] + 2))
+		en_hi++;
+
+	if ((en_lo + en_hi) * CLK_X < trc[mode])
+		en_lo += DIV_ROUND_UP((trc[mode] - (en_lo + en_hi) * CLK_X),
+				      CLK_X);
+
+	if ((en_lo + en_hi) < CLK_MULTI)
+		en_lo += CLK_MULTI - en_lo - en_hi;
+
+	while (dv_window < 8) {
+		data_invalid_rhoh = en_lo * CLK_X + trhoh[mode];
+
+		data_invalid_rloh = (en_lo + en_hi) * CLK_X + trloh[mode];
+
+		data_invalid =
+		    data_invalid_rhoh <
+		    data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh;
+
+		dv_window = data_invalid - trea[mode];
+
+		if (dv_window < 8)
+			en_lo++;
+	}
+
+	acc_clks = DIV_ROUND_UP(trea[mode], CLK_X);
+
+	while (((acc_clks * CLK_X) - trea[mode]) < 3)
+		acc_clks++;
+
+	if ((data_invalid - acc_clks * CLK_X) < 2)
+		debug("%s, Line %d: Warning!\n", __FILE__, __LINE__);
+
+	addr_2_data = DIV_ROUND_UP(tadl[mode], CLK_X);
+	re_2_we = DIV_ROUND_UP(trhw[mode], CLK_X);
+	re_2_re = DIV_ROUND_UP(trhz[mode], CLK_X);
+	we_2_re = DIV_ROUND_UP(twhr[mode], CLK_X);
+	cs_cnt = DIV_ROUND_UP((tcs[mode] - trp[mode]), CLK_X);
+	if (!tclsrising)
+		cs_cnt = DIV_ROUND_UP(tcs[mode], CLK_X);
+	if (cs_cnt == 0)
+		cs_cnt = 1;
+
+	if (tcea[mode]) {
+		while (((cs_cnt * CLK_X) + trea[mode]) < tcea[mode])
+			cs_cnt++;
+	}
+
+	/* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
+	if ((readl(denali->flash_reg + MANUFACTURER_ID) == 0) &&
+	    (readl(denali->flash_reg + DEVICE_ID) == 0x88))
+		acc_clks = 6;
+
+	writel(acc_clks, denali->flash_reg + ACC_CLKS);
+	writel(re_2_we, denali->flash_reg + RE_2_WE);
+	writel(re_2_re, denali->flash_reg + RE_2_RE);
+	writel(we_2_re, denali->flash_reg + WE_2_RE);
+	writel(addr_2_data, denali->flash_reg + ADDR_2_DATA);
+	writel(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
+	writel(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
+	writel(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
+}
+
+/* queries the NAND device to see what ONFI modes it supports. */
+static uint32_t get_onfi_nand_para(struct denali_nand_info *denali)
+{
+	int i;
+	/*
+	 * we needn't to do a reset here because driver has already
+	 * reset all the banks before
+	 */
+	if (!(readl(denali->flash_reg + ONFI_TIMING_MODE) &
+	    ONFI_TIMING_MODE__VALUE))
+		return -EIO;
+
+	for (i = 5; i > 0; i--) {
+		if (readl(denali->flash_reg + ONFI_TIMING_MODE) &
+			(0x01 << i))
+			break;
+	}
+
+	nand_onfi_timing_set(denali, i);
+
+	/* By now, all the ONFI devices we know support the page cache */
+	/* rw feature. So here we enable the pipeline_rw_ahead feature */
+	return 0;
+}
+
+static void get_samsung_nand_para(struct denali_nand_info *denali,
+							uint8_t device_id)
+{
+	if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
+		/* Set timing register values according to datasheet */
+		writel(5, denali->flash_reg + ACC_CLKS);
+		writel(20, denali->flash_reg + RE_2_WE);
+		writel(12, denali->flash_reg + WE_2_RE);
+		writel(14, denali->flash_reg + ADDR_2_DATA);
+		writel(3, denali->flash_reg + RDWR_EN_LO_CNT);
+		writel(2, denali->flash_reg + RDWR_EN_HI_CNT);
+		writel(2, denali->flash_reg + CS_SETUP_CNT);
+	}
+}
+
+static void get_toshiba_nand_para(struct denali_nand_info *denali)
+{
+	uint32_t tmp;
+
+	/* Workaround to fix a controller bug which reports a wrong */
+	/* spare area size for some kind of Toshiba NAND device */
+	if ((readl(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
+	    (readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
+		writel(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
+		tmp = readl(denali->flash_reg + DEVICES_CONNECTED) *
+			readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
+		writel(tmp, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
+	}
+}
+
+static void get_hynix_nand_para(struct denali_nand_info *denali,
+							uint8_t device_id)
+{
+	uint32_t main_size, spare_size;
+
+	switch (device_id) {
+	case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
+	case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
+		writel(128, denali->flash_reg + PAGES_PER_BLOCK);
+		writel(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
+		writel(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
+		main_size = 4096 *
+			readl(denali->flash_reg + DEVICES_CONNECTED);
+		spare_size = 224 *
+			readl(denali->flash_reg + DEVICES_CONNECTED);
+		writel(main_size, denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
+		writel(spare_size, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
+		writel(0, denali->flash_reg + DEVICE_WIDTH);
+		break;
+	default:
+		debug("Spectra: Unknown Hynix NAND (Device ID: 0x%x)."
+		      "Will use default parameter values instead.\n",
+		      device_id);
+	}
+}
+
+/*
+ * determines how many NAND chips are connected to the controller. Note for
+ * Intel CE4100 devices we don't support more than one device.
+ */
+static void find_valid_banks(struct denali_nand_info *denali)
+{
+	uint32_t id[denali->max_banks];
+	int i;
+
+	denali->total_used_banks = 1;
+	for (i = 0; i < denali->max_banks; i++) {
+		index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90);
+		index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0);
+		index_addr_read_data(denali,
+				     (uint32_t)(MODE_11 | (i << 24) | 2),
+				     &id[i]);
+
+		if (i == 0) {
+			if (!(id[i] & 0x0ff))
+				break;
+		} else {
+			if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
+				denali->total_used_banks++;
+			else
+				break;
+		}
+	}
+}
+
+/*
+ * Use the configuration feature register to determine the maximum number of
+ * banks that the hardware supports.
+ */
+static void detect_max_banks(struct denali_nand_info *denali)
+{
+	uint32_t features = readl(denali->flash_reg + FEATURES);
+	denali->max_banks = 2 << (features & FEATURES__N_BANKS);
+}
+
+static void detect_partition_feature(struct denali_nand_info *denali)
+{
+	/*
+	 * For MRST platform, denali->fwblks represent the
+	 * number of blocks firmware is taken,
+	 * FW is in protect partition and MTD driver has no
+	 * permission to access it. So let driver know how many
+	 * blocks it can't touch.
+	 */
+	if (readl(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
+		if ((readl(denali->flash_reg + PERM_SRC_ID(1)) &
+			PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
+			denali->fwblks =
+			    ((readl(denali->flash_reg + MIN_MAX_BANK(1)) &
+			      MIN_MAX_BANK__MIN_VALUE) *
+			     denali->blksperchip)
+			    +
+			    (readl(denali->flash_reg + MIN_BLK_ADDR(1)) &
+			    MIN_BLK_ADDR__VALUE);
+		} else {
+			denali->fwblks = SPECTRA_START_BLOCK;
+		}
+	} else {
+		denali->fwblks = SPECTRA_START_BLOCK;
+	}
+}
+
+static uint32_t denali_nand_timing_set(struct denali_nand_info *denali)
+{
+	uint32_t id_bytes[5], addr;
+	uint8_t i, maf_id, device_id;
+
+	/* Use read id method to get device ID and other
+	 * params. For some NAND chips, controller can't
+	 * report the correct device ID by reading from
+	 * DEVICE_ID register
+	 * */
+	addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
+	index_addr(denali, (uint32_t)addr | 0, 0x90);
+	index_addr(denali, (uint32_t)addr | 1, 0);
+	for (i = 0; i < 5; i++)
+		index_addr_read_data(denali, addr | 2, &id_bytes[i]);
+	maf_id = id_bytes[0];
+	device_id = id_bytes[1];
+
+	if (readl(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
+		ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
+		if (get_onfi_nand_para(denali))
+			return -EIO;
+	} else if (maf_id == 0xEC) { /* Samsung NAND */
+		get_samsung_nand_para(denali, device_id);
+	} else if (maf_id == 0x98) { /* Toshiba NAND */
+		get_toshiba_nand_para(denali);
+	} else if (maf_id == 0xAD) { /* Hynix NAND */
+		get_hynix_nand_para(denali, device_id);
+	}
+
+	find_valid_banks(denali);
+
+	detect_partition_feature(denali);
+
+	/* If the user specified to override the default timings
+	 * with a specific ONFI mode, we apply those changes here.
+	 */
+	if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
+		nand_onfi_timing_set(denali, onfi_timing_mode);
+
+	return 0;
+}
+
+/* validation function to verify that the controlling software is making
+ * a valid request
+ */
+static inline bool is_flash_bank_valid(int flash_bank)
+{
+	return flash_bank >= 0 && flash_bank < 4;
+}
+
+static void denali_irq_init(struct denali_nand_info *denali)
+{
+	uint32_t int_mask = 0;
+	int i;
+
+	/* Disable global interrupts */
+	writel(0, denali->flash_reg + GLOBAL_INT_ENABLE);
+
+	int_mask = DENALI_IRQ_ALL;
+
+	/* Clear all status bits */
+	for (i = 0; i < denali->max_banks; ++i)
+		writel(0xFFFF, denali->flash_reg + INTR_STATUS(i));
+
+	denali_irq_enable(denali, int_mask);
+}
+
+/* This helper function setups the registers for ECC and whether or not
+ * the spare area will be transferred. */
+static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
+				bool transfer_spare)
+{
+	int ecc_en_flag = 0, transfer_spare_flag = 0;
+
+	/* set ECC, transfer spare bits if needed */
+	ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
+	transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
+
+	/* Enable spare area/ECC per user's request. */
+	writel(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
+	/* applicable for MAP01 only */
+	writel(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);
+}
+
+/* sends a pipeline command operation to the controller. See the Denali NAND
+ * controller's user guide for more information (section 4.2.3.6).
+ */
+static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
+					bool ecc_en, bool transfer_spare,
+					int access_type, int op)
+{
+	uint32_t addr, cmd, irq_status;
+	static uint32_t page_count = 1;
+
+	setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
+
+	/* clear interrupts */
+	clear_interrupts(denali);
+
+	addr = BANK(denali->flash_bank) | denali->page;
+
+	/* setup the acccess type */
+	cmd = MODE_10 | addr;
+	index_addr(denali, cmd, access_type);
+
+	/* setup the pipeline command */
+	index_addr(denali, cmd, 0x2000 | op | page_count);
+
+	cmd = MODE_01 | addr;
+	writel(cmd, denali->flash_mem + INDEX_CTRL_REG);
+
+	if (op == DENALI_READ) {
+		/* wait for command to be accepted */
+		irq_status = wait_for_irq(denali, INTR_STATUS__LOAD_COMP);
+
+		if (irq_status == 0)
+			return -EIO;
+	}
+
+	return 0;
+}
+
+/* helper function that simply writes a buffer to the flash */
+static int write_data_to_flash_mem(struct denali_nand_info *denali,
+						const uint8_t *buf, int len)
+{
+	uint32_t i = 0, *buf32;
+
+	/* verify that the len is a multiple of 4. see comment in
+	 * read_data_from_flash_mem() */
+	BUG_ON((len % 4) != 0);
+
+	/* write the data to the flash memory */
+	buf32 = (uint32_t *)buf;
+	for (i = 0; i < len / 4; i++)
+		writel(*buf32++, denali->flash_mem + INDEX_DATA_REG);
+	return i * 4; /* intent is to return the number of bytes read */
+}
+
+/* helper function that simply reads a buffer from the flash */
+static int read_data_from_flash_mem(struct denali_nand_info *denali,
+						uint8_t *buf, int len)
+{
+	uint32_t i, *buf32;
+
+	/*
+	 * we assume that len will be a multiple of 4, if not
+	 * it would be nice to know about it ASAP rather than
+	 * have random failures...
+	 * This assumption is based on the fact that this
+	 * function is designed to be used to read flash pages,
+	 * which are typically multiples of 4...
+	 */
+
+	BUG_ON((len % 4) != 0);
+
+	/* transfer the data from the flash */
+	buf32 = (uint32_t *)buf;
+	for (i = 0; i < len / 4; i++)
+		*buf32++ = readl(denali->flash_mem + INDEX_DATA_REG);
+
+	return i * 4; /* intent is to return the number of bytes read */
+}
+
+static void denali_mode_main_access(struct denali_nand_info *denali)
+{
+	uint32_t addr, cmd;
+
+	addr = BANK(denali->flash_bank) | denali->page;
+	cmd = MODE_10 | addr;
+	index_addr(denali, cmd, MAIN_ACCESS);
+}
+
+static void denali_mode_main_spare_access(struct denali_nand_info *denali)
+{
+	uint32_t addr, cmd;
+
+	addr = BANK(denali->flash_bank) | denali->page;
+	cmd = MODE_10 | addr;
+	index_addr(denali, cmd, MAIN_SPARE_ACCESS);
+}
+
+/* writes OOB data to the device */
+static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
+{
+	struct denali_nand_info *denali = mtd_to_denali(mtd);
+	uint32_t irq_status;
+	uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
+						INTR_STATUS__PROGRAM_FAIL;
+	int status = 0;
+
+	denali->page = page;
+
+	if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
+				     DENALI_WRITE) == 0) {
+		write_data_to_flash_mem(denali, buf, mtd->oobsize);
+
+		/* wait for operation to complete */
+		irq_status = wait_for_irq(denali, irq_mask);
+
+		if (irq_status == 0) {
+			dev_err(denali->dev, "OOB write failed\n");
+			status = -EIO;
+		}
+	} else {
+		printf("unable to send pipeline command\n");
+		status = -EIO;
+	}
+	return status;
+}
+
+/* reads OOB data from the device */
+static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
+{
+	struct denali_nand_info *denali = mtd_to_denali(mtd);
+	uint32_t irq_mask = INTR_STATUS__LOAD_COMP,
+			 irq_status = 0, addr = 0x0, cmd = 0x0;
+
+	denali->page = page;
+
+	if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
+				     DENALI_READ) == 0) {
+		read_data_from_flash_mem(denali, buf, mtd->oobsize);
+
+		/* wait for command to be accepted
+		 * can always use status0 bit as the mask is identical for each
+		 * bank. */
+		irq_status = wait_for_irq(denali, irq_mask);
+
+		if (irq_status == 0)
+			printf("page on OOB timeout %d\n", denali->page);
+
+		/* We set the device back to MAIN_ACCESS here as I observed
+		 * instability with the controller if you do a block erase
+		 * and the last transaction was a SPARE_ACCESS. Block erase
+		 * is reliable (according to the MTD test infrastructure)
+		 * if you are in MAIN_ACCESS.
+		 */
+		addr = BANK(denali->flash_bank) | denali->page;
+		cmd = MODE_10 | addr;
+		index_addr(denali, cmd, MAIN_ACCESS);
+	}
+}
+
+/* this function examines buffers to see if they contain data that
+ * indicate that the buffer is part of an erased region of flash.
+ */
+static bool is_erased(uint8_t *buf, int len)
+{
+	int i = 0;
+	for (i = 0; i < len; i++)
+		if (buf[i] != 0xFF)
+			return false;
+	return true;
+}
+
+/* programs the controller to either enable/disable DMA transfers */
+static void denali_enable_dma(struct denali_nand_info *denali, bool en)
+{
+	uint32_t reg_val = 0x0;
+
+	if (en)
+		reg_val = DMA_ENABLE__FLAG;
+
+	writel(reg_val, denali->flash_reg + DMA_ENABLE);
+	readl(denali->flash_reg + DMA_ENABLE);
+}
+
+/* setups the HW to perform the data DMA */
+static void denali_setup_dma(struct denali_nand_info *denali, int op)
+{
+	uint32_t mode;
+	const int page_count = 1;
+	uint32_t addr = (uint32_t)denali->buf.dma_buf;
+
+	flush_dcache_range(addr, addr + sizeof(denali->buf.dma_buf));
+
+/* For Denali controller that is 64 bit bus IP core */
+#ifdef CONFIG_SYS_NAND_DENALI_64BIT
+	mode = MODE_10 | BANK(denali->flash_bank) | denali->page;
+
+	/* DMA is a three step process */
+
+	/* 1. setup transfer type, interrupt when complete,
+	      burst len = 64 bytes, the number of pages */
+	index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count);
+
+	/* 2. set memory low address bits 31:0 */
+	index_addr(denali, mode, addr);
+
+	/* 3. set memory high address bits 64:32 */
+	index_addr(denali, mode, 0);
+#else
+	mode = MODE_10 | BANK(denali->flash_bank);
+
+	/* DMA is a four step process */
+
+	/* 1. setup transfer type and # of pages */
+	index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
+
+	/* 2. set memory high address bits 23:8 */
+	index_addr(denali, mode | ((uint32_t)(addr >> 16) << 8), 0x2200);
+
+	/* 3. set memory low address bits 23:8 */
+	index_addr(denali, mode | ((uint32_t)addr << 8), 0x2300);
+
+	/* 4.  interrupt when complete, burst len = 64 bytes*/
+	index_addr(denali, mode | 0x14000, 0x2400);
+#endif
+}
+
+/* Common DMA function */
+static uint32_t denali_dma_configuration(struct denali_nand_info *denali,
+					 uint32_t ops, bool raw_xfer,
+					 uint32_t irq_mask, int oob_required)
+{
+	uint32_t irq_status = 0;
+	/* setup_ecc_for_xfer(bool ecc_en, bool transfer_spare) */
+	setup_ecc_for_xfer(denali, !raw_xfer, oob_required);
+
+	/* clear any previous interrupt flags */
+	clear_interrupts(denali);
+
+	/* enable the DMA */
+	denali_enable_dma(denali, true);
+
+	/* setup the DMA */
+	denali_setup_dma(denali, ops);
+
+	/* wait for operation to complete */
+	irq_status = wait_for_irq(denali, irq_mask);
+
+	/* if ECC fault happen, seems we need delay before turning off DMA.
+	 * If not, the controller will go into non responsive condition */
+	if (irq_status & INTR_STATUS__ECC_UNCOR_ERR)
+		udelay(100);
+
+	/* disable the DMA */
+	denali_enable_dma(denali, false);
+
+	return irq_status;
+}
+
+static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
+			const uint8_t *buf, bool raw_xfer, int oob_required)
+{
+	struct denali_nand_info *denali = mtd_to_denali(mtd);
+
+	uint32_t irq_status = 0;
+	uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
+
+	denali->status = 0;
+
+	/* copy buffer into DMA buffer */
+	memcpy(denali->buf.dma_buf, buf, mtd->writesize);
+
+	/* need extra memcpy for raw transfer */
+	if (raw_xfer)
+		memcpy(denali->buf.dma_buf + mtd->writesize,
+		       chip->oob_poi, mtd->oobsize);
+
+	/* setting up DMA */
+	irq_status = denali_dma_configuration(denali, DENALI_WRITE, raw_xfer,
+					      irq_mask, oob_required);
+
+	/* if timeout happen, error out */
+	if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {
+		debug("DMA timeout for denali write_page\n");
+		denali->status = NAND_STATUS_FAIL;
+		return -EIO;
+	}
+
+	if (irq_status & INTR_STATUS__LOCKED_BLK) {
+		debug("Failed as write to locked block\n");
+		denali->status = NAND_STATUS_FAIL;
+		return -EIO;
+	}
+	return 0;
+}
+
+/* NAND core entry points */
+
+/*
+ * this is the callback that the NAND core calls to write a page. Since
+ * writing a page with ECC or without is similar, all the work is done
+ * by write_page above.
+ */
+static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+				const uint8_t *buf, int oob_required)
+{
+	struct denali_nand_info *denali = mtd_to_denali(mtd);
+
+	/*
+	 * for regular page writes, we let HW handle all the ECC
+	 * data written to the device.
+	 */
+	if (oob_required)
+		/* switch to main + spare access */
+		denali_mode_main_spare_access(denali);
+	else
+		/* switch to main access only */
+		denali_mode_main_access(denali);
+
+	return write_page(mtd, chip, buf, false, oob_required);
+}
+
+/*
+ * This is the callback that the NAND core calls to write a page without ECC.
+ * raw access is similar to ECC page writes, so all the work is done in the
+ * write_page() function above.
+ */
+static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+					const uint8_t *buf, int oob_required)
+{
+	struct denali_nand_info *denali = mtd_to_denali(mtd);
+
+	/*
+	 * for raw page writes, we want to disable ECC and simply write
+	 * whatever data is in the buffer.
+	 */
+
+	if (oob_required)
+		/* switch to main + spare access */
+		denali_mode_main_spare_access(denali);
+	else
+		/* switch to main access only */
+		denali_mode_main_access(denali);
+
+	return write_page(mtd, chip, buf, true, oob_required);
+}
+
+static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+				int page)
+{
+	return write_oob_data(mtd, chip->oob_poi, page);
+}
+
+/* raw include ECC value and all the spare area */
+static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+				uint8_t *buf, int oob_required, int page)
+{
+	struct denali_nand_info *denali = mtd_to_denali(mtd);
+
+	uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP;
+
+	if (denali->page != page) {
+		debug("Missing NAND_CMD_READ0 command\n");
+		return -EIO;
+	}
+
+	if (oob_required)
+		/* switch to main + spare access */
+		denali_mode_main_spare_access(denali);
+	else
+		/* switch to main access only */
+		denali_mode_main_access(denali);
+
+	/* setting up the DMA where ecc_enable is false */
+	irq_status = denali_dma_configuration(denali, DENALI_READ, true,
+					      irq_mask, oob_required);
+
+	/* if timeout happen, error out */
+	if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {
+		debug("DMA timeout for denali_read_page_raw\n");
+		return -EIO;
+	}
+
+	/* splitting the content to destination buffer holder */
+	memcpy(chip->oob_poi, (denali->buf.dma_buf + mtd->writesize),
+	       mtd->oobsize);
+	memcpy(buf, denali->buf.dma_buf, mtd->writesize);
+
+	return 0;
+}
+
+static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+				uint8_t *buf, int oob_required, int page)
+{
+	struct denali_nand_info *denali = mtd_to_denali(mtd);
+	uint32_t irq_status, irq_mask =	INTR_STATUS__DMA_CMD_COMP;
+
+	if (denali->page != page) {
+		debug("Missing NAND_CMD_READ0 command\n");
+		return -EIO;
+	}
+
+	if (oob_required)
+		/* switch to main + spare access */
+		denali_mode_main_spare_access(denali);
+	else
+		/* switch to main access only */
+		denali_mode_main_access(denali);
+
+	/* setting up the DMA where ecc_enable is true */
+	irq_status = denali_dma_configuration(denali, DENALI_READ, false,
+					      irq_mask, oob_required);
+
+	memcpy(buf, denali->buf.dma_buf, mtd->writesize);
+
+	/* check whether any ECC error */
+	if (irq_status & INTR_STATUS__ECC_UNCOR_ERR) {
+		/* is the ECC cause by erase page, check using read_page_raw */
+		debug("  Uncorrected ECC detected\n");
+		denali_read_page_raw(mtd, chip, buf, oob_required,
+				     denali->page);
+
+		if (is_erased(buf, mtd->writesize) == true &&
+		    is_erased(chip->oob_poi, mtd->oobsize) == true) {
+			debug("  ECC error cause by erased block\n");
+			/* false alarm, return the 0xFF */
+		} else {
+			return -EIO;
+		}
+	}
+	memcpy(buf, denali->buf.dma_buf, mtd->writesize);
+	return 0;
+}
+
+static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+				int page)
+{
+	read_oob_data(mtd, chip->oob_poi, page);
+
+	return 0;
+}
+
+static uint8_t denali_read_byte(struct mtd_info *mtd)
+{
+	struct denali_nand_info *denali = mtd_to_denali(mtd);
+	uint32_t addr, result;
+
+	addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
+	index_addr_read_data(denali, addr | 2, &result);
+	return (uint8_t)result & 0xFF;
+}
+
+static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	struct denali_nand_info *denali = mtd_to_denali(mtd);
+	uint32_t i, addr, result;
+
+	/* delay for tR (data transfer from Flash array to data register) */
+	udelay(25);
+
+	/* ensure device completed else additional delay and polling */
+	wait_for_irq(denali, INTR_STATUS__INT_ACT);
+
+	addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
+	for (i = 0; i < len; i++) {
+		index_addr_read_data(denali, (uint32_t)addr | 2, &result);
+		write_byte_to_buf(denali, result);
+	}
+	memcpy(buf, denali->buf.buf, len);
+}
+
+static void denali_select_chip(struct mtd_info *mtd, int chip)
+{
+	struct denali_nand_info *denali = mtd_to_denali(mtd);
+
+	denali->flash_bank = chip;
+}
+
+static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
+{
+	struct denali_nand_info *denali = mtd_to_denali(mtd);
+	int status = denali->status;
+	denali->status = 0;
+
+	return status;
+}
+
+static void denali_erase(struct mtd_info *mtd, int page)
+{
+	struct denali_nand_info *denali = mtd_to_denali(mtd);
+	uint32_t cmd, irq_status;
+
+	/* clear interrupts */
+	clear_interrupts(denali);
+
+	/* setup page read request for access type */
+	cmd = MODE_10 | BANK(denali->flash_bank) | page;
+	index_addr(denali, cmd, 0x1);
+
+	/* wait for erase to complete or failure to occur */
+	irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
+					INTR_STATUS__ERASE_FAIL);
+
+	if (irq_status & INTR_STATUS__ERASE_FAIL ||
+	    irq_status & INTR_STATUS__LOCKED_BLK)
+		denali->status = NAND_STATUS_FAIL;
+	else
+		denali->status = 0;
+}
+
+static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
+			   int page)
+{
+	struct denali_nand_info *denali = mtd_to_denali(mtd);
+	uint32_t addr;
+
+	switch (cmd) {
+	case NAND_CMD_PAGEPROG:
+		break;
+	case NAND_CMD_STATUS:
+		addr = MODE_11 | BANK(denali->flash_bank);
+		index_addr(denali, addr | 0, cmd);
+		break;
+	case NAND_CMD_PARAM:
+		clear_interrupts(denali);
+	case NAND_CMD_READID:
+		reset_buf(denali);
+		/* sometimes ManufactureId read from register is not right
+		 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
+		 * So here we send READID cmd to NAND insteand
+		 * */
+		addr = MODE_11 | BANK(denali->flash_bank);
+		index_addr(denali, addr | 0, cmd);
+		index_addr(denali, addr | 1, col & 0xFF);
+		break;
+	case NAND_CMD_READ0:
+	case NAND_CMD_SEQIN:
+		denali->page = page;
+		break;
+	case NAND_CMD_RESET:
+		reset_bank(denali);
+		break;
+	case NAND_CMD_READOOB:
+		/* TODO: Read OOB data */
+		break;
+	case NAND_CMD_ERASE1:
+		/*
+		 * supporting block erase only, not multiblock erase as
+		 * it will cross plane and software need complex calculation
+		 * to identify the block count for the cross plane
+		 */
+		denali_erase(mtd, page);
+		break;
+	case NAND_CMD_ERASE2:
+		/* nothing to do here as it was done during NAND_CMD_ERASE1 */
+		break;
+	case NAND_CMD_UNLOCK1:
+		addr = MODE_10 | BANK(denali->flash_bank) | page;
+		index_addr(denali, addr | 0, DENALI_UNLOCK_START);
+		break;
+	case NAND_CMD_UNLOCK2:
+		addr = MODE_10 | BANK(denali->flash_bank) | page;
+		index_addr(denali, addr | 0, DENALI_UNLOCK_END);
+		break;
+	case NAND_CMD_LOCK:
+		addr = MODE_10 | BANK(denali->flash_bank);
+		index_addr(denali, addr | 0, DENALI_LOCK);
+		break;
+	default:
+		printf(": unsupported command received 0x%x\n", cmd);
+		break;
+	}
+}
+/* end NAND core entry points */
+
+/* Initialization code to bring the device up to a known good state */
+static void denali_hw_init(struct denali_nand_info *denali)
+{
+	/*
+	 * tell driver how many bit controller will skip before writing
+	 * ECC code in OOB. This is normally used for bad block marker
+	 */
+	writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES,
+	       denali->flash_reg + SPARE_AREA_SKIP_BYTES);
+	detect_max_banks(denali);
+	denali_nand_reset(denali);
+	writel(0x0F, denali->flash_reg + RB_PIN_ENABLED);
+	writel(CHIP_EN_DONT_CARE__FLAG,
+	       denali->flash_reg + CHIP_ENABLE_DONT_CARE);
+	writel(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
+
+	/* Should set value for these registers when init */
+	writel(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
+	writel(1, denali->flash_reg + ECC_ENABLE);
+	denali_nand_timing_set(denali);
+	denali_irq_init(denali);
+}
+
+static struct nand_ecclayout nand_oob;
+
+static int denali_nand_init(struct nand_chip *nand)
+{
+	struct denali_nand_info *denali;
+
+	denali = malloc(sizeof(*denali));
+	if (!denali)
+		return -ENOMEM;
+
+	nand->priv = denali;
+
+	denali->flash_reg = (void  __iomem *)CONFIG_SYS_NAND_REGS_BASE;
+	denali->flash_mem = (void  __iomem *)CONFIG_SYS_NAND_DATA_BASE;
+
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+	/* check whether flash got BBT table (located at end of flash). As we
+	 * use NAND_BBT_NO_OOB, the BBT page will start with
+	 * bbt_pattern. We will have mirror pattern too */
+	nand->bbt_options |= NAND_BBT_USE_FLASH;
+	/*
+	 * We are using main + spare with ECC support. As BBT need ECC support,
+	 * we need to ensure BBT code don't write to OOB for the BBT pattern.
+	 * All BBT info will be stored into data area with ECC support.
+	 */
+	nand->bbt_options |= NAND_BBT_NO_OOB;
+#endif
+
+	nand->ecc.mode = NAND_ECC_HW;
+	nand->ecc.size = CONFIG_NAND_DENALI_ECC_SIZE;
+	nand->ecc.read_oob = denali_read_oob;
+	nand->ecc.write_oob = denali_write_oob;
+	nand->ecc.read_page = denali_read_page;
+	nand->ecc.read_page_raw = denali_read_page_raw;
+	nand->ecc.write_page = denali_write_page;
+	nand->ecc.write_page_raw = denali_write_page_raw;
+	/*
+	 * Tell driver the ecc strength. This register may be already set
+	 * correctly. So we read this value out.
+	 */
+	nand->ecc.strength = readl(denali->flash_reg + ECC_CORRECTION);
+	switch (nand->ecc.size) {
+	case 512:
+		nand->ecc.bytes = (nand->ecc.strength * 13 + 15) / 16 * 2;
+		break;
+	case 1024:
+		nand->ecc.bytes = (nand->ecc.strength * 14 + 15) / 16 * 2;
+		break;
+	default:
+		pr_err("Unsupported ECC size\n");
+		return -EINVAL;
+	}
+	nand_oob.eccbytes = nand->ecc.bytes;
+	nand->ecc.layout = &nand_oob;
+
+	/* Set address of hardware control function */
+	nand->cmdfunc = denali_cmdfunc;
+	nand->read_byte = denali_read_byte;
+	nand->read_buf = denali_read_buf;
+	nand->select_chip = denali_select_chip;
+	nand->waitfunc = denali_waitfunc;
+	denali_hw_init(denali);
+	return 0;
+}
+
+int board_nand_init(struct nand_chip *chip)
+{
+	return denali_nand_init(chip);
+}
diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h
new file mode 100644
index 0000000000..3277da71e1
--- /dev/null
+++ b/drivers/mtd/nand/denali.h
@@ -0,0 +1,467 @@
+/*
+ * Copyright (C) 2013-2014 Altera Corporation <www.altera.com>
+ * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/mtd/nand.h>
+
+#define DEVICE_RESET				0x0
+#define     DEVICE_RESET__BANK0				0x0001
+#define     DEVICE_RESET__BANK1				0x0002
+#define     DEVICE_RESET__BANK2				0x0004
+#define     DEVICE_RESET__BANK3				0x0008
+
+#define TRANSFER_SPARE_REG			0x10
+#define     TRANSFER_SPARE_REG__FLAG			0x0001
+
+#define LOAD_WAIT_CNT				0x20
+#define     LOAD_WAIT_CNT__VALUE			0xffff
+
+#define PROGRAM_WAIT_CNT			0x30
+#define     PROGRAM_WAIT_CNT__VALUE			0xffff
+
+#define ERASE_WAIT_CNT				0x40
+#define     ERASE_WAIT_CNT__VALUE			0xffff
+
+#define INT_MON_CYCCNT				0x50
+#define     INT_MON_CYCCNT__VALUE			0xffff
+
+#define RB_PIN_ENABLED				0x60
+#define     RB_PIN_ENABLED__BANK0			0x0001
+#define     RB_PIN_ENABLED__BANK1			0x0002
+#define     RB_PIN_ENABLED__BANK2			0x0004
+#define     RB_PIN_ENABLED__BANK3			0x0008
+
+#define MULTIPLANE_OPERATION			0x70
+#define     MULTIPLANE_OPERATION__FLAG			0x0001
+
+#define MULTIPLANE_READ_ENABLE			0x80
+#define     MULTIPLANE_READ_ENABLE__FLAG		0x0001
+
+#define COPYBACK_DISABLE			0x90
+#define     COPYBACK_DISABLE__FLAG			0x0001
+
+#define CACHE_WRITE_ENABLE			0xa0
+#define     CACHE_WRITE_ENABLE__FLAG			0x0001
+
+#define CACHE_READ_ENABLE			0xb0
+#define     CACHE_READ_ENABLE__FLAG			0x0001
+
+#define PREFETCH_MODE				0xc0
+#define     PREFETCH_MODE__PREFETCH_EN			0x0001
+#define     PREFETCH_MODE__PREFETCH_BURST_LENGTH	0xfff0
+
+#define CHIP_ENABLE_DONT_CARE			0xd0
+#define     CHIP_EN_DONT_CARE__FLAG			0x01
+
+#define ECC_ENABLE				0xe0
+#define     ECC_ENABLE__FLAG				0x0001
+
+#define GLOBAL_INT_ENABLE			0xf0
+#define     GLOBAL_INT_EN_FLAG				0x01
+
+#define WE_2_RE					0x100
+#define     WE_2_RE__VALUE				0x003f
+
+#define ADDR_2_DATA				0x110
+#define     ADDR_2_DATA__VALUE				0x003f
+
+#define RE_2_WE					0x120
+#define     RE_2_WE__VALUE				0x003f
+
+#define ACC_CLKS				0x130
+#define     ACC_CLKS__VALUE				0x000f
+
+#define NUMBER_OF_PLANES			0x140
+#define     NUMBER_OF_PLANES__VALUE			0x0007
+
+#define PAGES_PER_BLOCK				0x150
+#define     PAGES_PER_BLOCK__VALUE			0xffff
+
+#define DEVICE_WIDTH				0x160
+#define     DEVICE_WIDTH__VALUE				0x0003
+
+#define DEVICE_MAIN_AREA_SIZE			0x170
+#define     DEVICE_MAIN_AREA_SIZE__VALUE		0xffff
+
+#define DEVICE_SPARE_AREA_SIZE			0x180
+#define     DEVICE_SPARE_AREA_SIZE__VALUE		0xffff
+
+#define TWO_ROW_ADDR_CYCLES			0x190
+#define     TWO_ROW_ADDR_CYCLES__FLAG			0x0001
+
+#define MULTIPLANE_ADDR_RESTRICT		0x1a0
+#define     MULTIPLANE_ADDR_RESTRICT__FLAG		0x0001
+
+#define ECC_CORRECTION				0x1b0
+#define     ECC_CORRECTION__VALUE			0x001f
+
+#define READ_MODE				0x1c0
+#define     READ_MODE__VALUE				0x000f
+
+#define WRITE_MODE				0x1d0
+#define     WRITE_MODE__VALUE				0x000f
+
+#define COPYBACK_MODE				0x1e0
+#define     COPYBACK_MODE__VALUE			0x000f
+
+#define RDWR_EN_LO_CNT				0x1f0
+#define     RDWR_EN_LO_CNT__VALUE			0x001f
+
+#define RDWR_EN_HI_CNT				0x200
+#define     RDWR_EN_HI_CNT__VALUE			0x001f
+
+#define MAX_RD_DELAY				0x210
+#define     MAX_RD_DELAY__VALUE				0x000f
+
+#define CS_SETUP_CNT				0x220
+#define     CS_SETUP_CNT__VALUE				0x001f
+
+#define SPARE_AREA_SKIP_BYTES			0x230
+#define     SPARE_AREA_SKIP_BYTES__VALUE		0x003f
+
+#define SPARE_AREA_MARKER			0x240
+#define     SPARE_AREA_MARKER__VALUE			0xffff
+
+#define DEVICES_CONNECTED			0x250
+#define     DEVICES_CONNECTED__VALUE			0x0007
+
+#define DIE_MASK				0x260
+#define     DIE_MASK__VALUE				0x00ff
+
+#define FIRST_BLOCK_OF_NEXT_PLANE		0x270
+#define     FIRST_BLOCK_OF_NEXT_PLANE__VALUE		0xffff
+
+#define WRITE_PROTECT				0x280
+#define     WRITE_PROTECT__FLAG				0x0001
+
+#define RE_2_RE					0x290
+#define     RE_2_RE__VALUE				0x003f
+
+#define MANUFACTURER_ID				0x300
+#define     MANUFACTURER_ID__VALUE			0x00ff
+
+#define DEVICE_ID				0x310
+#define     DEVICE_ID__VALUE				0x00ff
+
+#define DEVICE_PARAM_0				0x320
+#define     DEVICE_PARAM_0__VALUE			0x00ff
+
+#define DEVICE_PARAM_1				0x330
+#define     DEVICE_PARAM_1__VALUE			0x00ff
+
+#define DEVICE_PARAM_2				0x340
+#define     DEVICE_PARAM_2__VALUE			0x00ff
+
+#define LOGICAL_PAGE_DATA_SIZE			0x350
+#define     LOGICAL_PAGE_DATA_SIZE__VALUE		0xffff
+
+#define LOGICAL_PAGE_SPARE_SIZE			0x360
+#define     LOGICAL_PAGE_SPARE_SIZE__VALUE		0xffff
+
+#define REVISION				0x370
+#define     REVISION__VALUE				0xffff
+
+#define ONFI_DEVICE_FEATURES			0x380
+#define     ONFI_DEVICE_FEATURES__VALUE			0x003f
+
+#define ONFI_OPTIONAL_COMMANDS			0x390
+#define     ONFI_OPTIONAL_COMMANDS__VALUE		0x003f
+
+#define ONFI_TIMING_MODE			0x3a0
+#define     ONFI_TIMING_MODE__VALUE			0x003f
+
+#define ONFI_PGM_CACHE_TIMING_MODE		0x3b0
+#define     ONFI_PGM_CACHE_TIMING_MODE__VALUE		0x003f
+
+#define ONFI_DEVICE_NO_OF_LUNS			0x3c0
+#define     ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS		0x00ff
+#define     ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE		0x0100
+
+#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L	0x3d0
+#define     ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE	0xffff
+
+#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U	0x3e0
+#define     ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE	0xffff
+
+#define FEATURES					0x3f0
+#define     FEATURES__N_BANKS				0x0003
+#define     FEATURES__ECC_MAX_ERR			0x003c
+#define     FEATURES__DMA				0x0040
+#define     FEATURES__CMD_DMA				0x0080
+#define     FEATURES__PARTITION				0x0100
+#define     FEATURES__XDMA_SIDEBAND			0x0200
+#define     FEATURES__GPREG				0x0400
+#define     FEATURES__INDEX_ADDR			0x0800
+
+#define TRANSFER_MODE				0x400
+#define     TRANSFER_MODE__VALUE			0x0003
+
+#define INTR_STATUS(__bank)	(0x410 + ((__bank) * 0x50))
+#define INTR_EN(__bank)		(0x420 + ((__bank) * 0x50))
+
+/*
+ * Some versions of the IP have the ECC fixup handled in hardware.  In this
+ * configuration we only get interrupted when the error is uncorrectable.
+ * Unfortunately this bit replaces INTR_STATUS__ECC_TRANSACTION_DONE from the
+ * old IP.
+ */
+#define     INTR_STATUS__ECC_UNCOR_ERR			0x0001
+#define     INTR_STATUS__ECC_TRANSACTION_DONE		0x0001
+#define     INTR_STATUS__ECC_ERR			0x0002
+#define     INTR_STATUS__DMA_CMD_COMP			0x0004
+#define     INTR_STATUS__TIME_OUT			0x0008
+#define     INTR_STATUS__PROGRAM_FAIL			0x0010
+#define     INTR_STATUS__ERASE_FAIL			0x0020
+#define     INTR_STATUS__LOAD_COMP			0x0040
+#define     INTR_STATUS__PROGRAM_COMP			0x0080
+#define     INTR_STATUS__ERASE_COMP			0x0100
+#define     INTR_STATUS__PIPE_CPYBCK_CMD_COMP		0x0200
+#define     INTR_STATUS__LOCKED_BLK			0x0400
+#define     INTR_STATUS__UNSUP_CMD			0x0800
+#define     INTR_STATUS__INT_ACT			0x1000
+#define     INTR_STATUS__RST_COMP			0x2000
+#define     INTR_STATUS__PIPE_CMD_ERR			0x4000
+#define     INTR_STATUS__PAGE_XFER_INC			0x8000
+
+#define     INTR_EN__ECC_TRANSACTION_DONE		0x0001
+#define     INTR_EN__ECC_ERR				0x0002
+#define     INTR_EN__DMA_CMD_COMP			0x0004
+#define     INTR_EN__TIME_OUT				0x0008
+#define     INTR_EN__PROGRAM_FAIL			0x0010
+#define     INTR_EN__ERASE_FAIL				0x0020
+#define     INTR_EN__LOAD_COMP				0x0040
+#define     INTR_EN__PROGRAM_COMP			0x0080
+#define     INTR_EN__ERASE_COMP				0x0100
+#define     INTR_EN__PIPE_CPYBCK_CMD_COMP		0x0200
+#define     INTR_EN__LOCKED_BLK				0x0400
+#define     INTR_EN__UNSUP_CMD				0x0800
+#define     INTR_EN__INT_ACT				0x1000
+#define     INTR_EN__RST_COMP				0x2000
+#define     INTR_EN__PIPE_CMD_ERR			0x4000
+#define     INTR_EN__PAGE_XFER_INC			0x8000
+
+#define PAGE_CNT(__bank)	(0x430 + ((__bank) * 0x50))
+#define ERR_PAGE_ADDR(__bank)	(0x440 + ((__bank) * 0x50))
+#define ERR_BLOCK_ADDR(__bank)	(0x450 + ((__bank) * 0x50))
+
+#define DATA_INTR				0x550
+#define     DATA_INTR__WRITE_SPACE_AV			0x0001
+#define     DATA_INTR__READ_DATA_AV			0x0002
+
+#define DATA_INTR_EN				0x560
+#define     DATA_INTR_EN__WRITE_SPACE_AV		0x0001
+#define     DATA_INTR_EN__READ_DATA_AV			0x0002
+
+#define GPREG_0					0x570
+#define     GPREG_0__VALUE				0xffff
+
+#define GPREG_1					0x580
+#define     GPREG_1__VALUE				0xffff
+
+#define GPREG_2					0x590
+#define     GPREG_2__VALUE				0xffff
+
+#define GPREG_3					0x5a0
+#define     GPREG_3__VALUE				0xffff
+
+#define ECC_THRESHOLD				0x600
+#define     ECC_THRESHOLD__VALUE			0x03ff
+
+#define ECC_ERROR_BLOCK_ADDRESS			0x610
+#define     ECC_ERROR_BLOCK_ADDRESS__VALUE		0xffff
+
+#define ECC_ERROR_PAGE_ADDRESS			0x620
+#define     ECC_ERROR_PAGE_ADDRESS__VALUE		0x0fff
+#define     ECC_ERROR_PAGE_ADDRESS__BANK		0xf000
+
+#define ECC_ERROR_ADDRESS			0x630
+#define     ECC_ERROR_ADDRESS__OFFSET			0x0fff
+#define     ECC_ERROR_ADDRESS__SECTOR_NR		0xf000
+
+#define ERR_CORRECTION_INFO			0x640
+#define     ERR_CORRECTION_INFO__BYTEMASK		0x00ff
+#define     ERR_CORRECTION_INFO__DEVICE_NR		0x0f00
+#define     ERR_CORRECTION_INFO__ERROR_TYPE		0x4000
+#define     ERR_CORRECTION_INFO__LAST_ERR_INFO		0x8000
+
+#define DMA_ENABLE				0x700
+#define     DMA_ENABLE__FLAG				0x0001
+
+#define IGNORE_ECC_DONE				0x710
+#define     IGNORE_ECC_DONE__FLAG			0x0001
+
+#define DMA_INTR				0x720
+#define     DMA_INTR__TARGET_ERROR			0x0001
+#define     DMA_INTR__DESC_COMP_CHANNEL0		0x0002
+#define     DMA_INTR__DESC_COMP_CHANNEL1		0x0004
+#define     DMA_INTR__DESC_COMP_CHANNEL2		0x0008
+#define     DMA_INTR__DESC_COMP_CHANNEL3		0x0010
+#define     DMA_INTR__MEMCOPY_DESC_COMP		0x0020
+
+#define DMA_INTR_EN				0x730
+#define     DMA_INTR_EN__TARGET_ERROR			0x0001
+#define     DMA_INTR_EN__DESC_COMP_CHANNEL0		0x0002
+#define     DMA_INTR_EN__DESC_COMP_CHANNEL1		0x0004
+#define     DMA_INTR_EN__DESC_COMP_CHANNEL2		0x0008
+#define     DMA_INTR_EN__DESC_COMP_CHANNEL3		0x0010
+#define     DMA_INTR_EN__MEMCOPY_DESC_COMP		0x0020
+
+#define TARGET_ERR_ADDR_LO			0x740
+#define     TARGET_ERR_ADDR_LO__VALUE			0xffff
+
+#define TARGET_ERR_ADDR_HI			0x750
+#define     TARGET_ERR_ADDR_HI__VALUE			0xffff
+
+#define CHNL_ACTIVE				0x760
+#define     CHNL_ACTIVE__CHANNEL0			0x0001
+#define     CHNL_ACTIVE__CHANNEL1			0x0002
+#define     CHNL_ACTIVE__CHANNEL2			0x0004
+#define     CHNL_ACTIVE__CHANNEL3			0x0008
+
+#define ACTIVE_SRC_ID				0x800
+#define     ACTIVE_SRC_ID__VALUE			0x00ff
+
+#define PTN_INTR					0x810
+#define     PTN_INTR__CONFIG_ERROR			0x0001
+#define     PTN_INTR__ACCESS_ERROR_BANK0		0x0002
+#define     PTN_INTR__ACCESS_ERROR_BANK1		0x0004
+#define     PTN_INTR__ACCESS_ERROR_BANK2		0x0008
+#define     PTN_INTR__ACCESS_ERROR_BANK3		0x0010
+#define     PTN_INTR__REG_ACCESS_ERROR			0x0020
+
+#define PTN_INTR_EN				0x820
+#define     PTN_INTR_EN__CONFIG_ERROR			0x0001
+#define     PTN_INTR_EN__ACCESS_ERROR_BANK0		0x0002
+#define     PTN_INTR_EN__ACCESS_ERROR_BANK1		0x0004
+#define     PTN_INTR_EN__ACCESS_ERROR_BANK2		0x0008
+#define     PTN_INTR_EN__ACCESS_ERROR_BANK3		0x0010
+#define     PTN_INTR_EN__REG_ACCESS_ERROR		0x0020
+
+#define PERM_SRC_ID(__bank)	(0x830 + ((__bank) * 0x40))
+#define     PERM_SRC_ID__SRCID				0x00ff
+#define     PERM_SRC_ID__DIRECT_ACCESS_ACTIVE		0x0800
+#define     PERM_SRC_ID__WRITE_ACTIVE			0x2000
+#define     PERM_SRC_ID__READ_ACTIVE			0x4000
+#define     PERM_SRC_ID__PARTITION_VALID		0x8000
+
+#define MIN_BLK_ADDR(__bank)	(0x840 + ((__bank) * 0x40))
+#define     MIN_BLK_ADDR__VALUE				0xffff
+
+#define MAX_BLK_ADDR(__bank)	(0x850 + ((__bank) * 0x40))
+#define     MAX_BLK_ADDR__VALUE				0xffff
+
+#define MIN_MAX_BANK(__bank)	(0x860 + ((__bank) * 0x40))
+#define     MIN_MAX_BANK__MIN_VALUE			0x0003
+#define     MIN_MAX_BANK__MAX_VALUE			0x000c
+
+/* lld.h */
+#define GOOD_BLOCK 0
+#define DEFECTIVE_BLOCK 1
+#define READ_ERROR 2
+
+#define CLK_X  5
+#define CLK_MULTI 4
+
+/* spectraswconfig.h */
+#define CMD_DMA 0
+
+#define SPECTRA_PARTITION_ID    0
+/**** Block Table and Reserved Block Parameters *****/
+#define SPECTRA_START_BLOCK     3
+#define NUM_FREE_BLOCKS_GATE    30
+
+/* KBV - Updated to LNW scratch register address */
+#define SCRATCH_REG_ADDR    CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR
+#define SCRATCH_REG_SIZE    64
+
+#define GLOB_HWCTL_DEFAULT_BLKS    2048
+
+#define CUSTOM_CONF_PARAMS      0
+
+#ifndef _LLD_NAND_
+#define _LLD_NAND_
+
+#define INDEX_CTRL_REG    0x0
+#define INDEX_DATA_REG    0x10
+
+#define MODE_00    0x00000000
+#define MODE_01    0x04000000
+#define MODE_10    0x08000000
+#define MODE_11    0x0C000000
+
+
+#define DATA_TRANSFER_MODE              0
+#define PROTECTION_PER_BLOCK            1
+#define LOAD_WAIT_COUNT                 2
+#define PROGRAM_WAIT_COUNT              3
+#define ERASE_WAIT_COUNT                4
+#define INT_MONITOR_CYCLE_COUNT         5
+#define READ_BUSY_PIN_ENABLED           6
+#define MULTIPLANE_OPERATION_SUPPORT    7
+#define PRE_FETCH_MODE                  8
+#define CE_DONT_CARE_SUPPORT            9
+#define COPYBACK_SUPPORT                10
+#define CACHE_WRITE_SUPPORT             11
+#define CACHE_READ_SUPPORT              12
+#define NUM_PAGES_IN_BLOCK              13
+#define ECC_ENABLE_SELECT               14
+#define WRITE_ENABLE_2_READ_ENABLE      15
+#define ADDRESS_2_DATA                  16
+#define READ_ENABLE_2_WRITE_ENABLE      17
+#define TWO_ROW_ADDRESS_CYCLES          18
+#define MULTIPLANE_ADDRESS_RESTRICT     19
+#define ACC_CLOCKS                      20
+#define READ_WRITE_ENABLE_LOW_COUNT     21
+#define READ_WRITE_ENABLE_HIGH_COUNT    22
+
+#define ECC_SECTOR_SIZE     512
+
+#define DENALI_BUF_SIZE		(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE)
+
+struct nand_buf {
+	int head;
+	int tail;
+	/* seprating dma_buf as buf can be used for status read purpose */
+	uint8_t dma_buf[DENALI_BUF_SIZE]  __aligned(64);
+	uint8_t buf[DENALI_BUF_SIZE];
+};
+
+#define INTEL_CE4100	1
+#define INTEL_MRST	2
+#define DT		3
+
+struct denali_nand_info {
+	struct mtd_info mtd;
+	struct nand_chip *nand;
+
+	int flash_bank; /* currently selected chip */
+	int status;
+	int platform;
+	struct nand_buf buf;
+	struct device *dev;
+	int total_used_banks;
+	uint32_t block;  /* stored for future use */
+	uint32_t page;
+	void __iomem *flash_reg;  /* Mapped io reg base address */
+	void __iomem *flash_mem;  /* Mapped io reg base address */
+
+	/* elements used by ISR */
+	/*struct completion complete;*/
+
+	uint32_t irq_status;
+	int irq_debug_array[32];
+	int idx;
+	int irq;
+
+	uint32_t devnum;	/* represent how many nands connected */
+	uint32_t fwblks; /* represent how many blocks FW used */
+	uint32_t totalblks;
+	uint32_t blksperchip;
+	uint32_t bbtskipbytes;
+	uint32_t max_banks;
+};
+
+#endif /*_LLD_NAND_*/
diff --git a/drivers/mtd/nand/denali_spl.c b/drivers/mtd/nand/denali_spl.c
new file mode 100644
index 0000000000..65fdde8a65
--- /dev/null
+++ b/drivers/mtd/nand/denali_spl.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2014       Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/unaligned.h>
+#include <linux/mtd/nand.h>
+#include "denali.h"
+
+#define SPARE_ACCESS		0x41
+#define MAIN_ACCESS		0x42
+#define PIPELINE_ACCESS		0x2000
+
+#define BANK(x) ((x) << 24)
+
+static void __iomem *denali_flash_mem =
+			(void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
+static void __iomem *denali_flash_reg =
+			(void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
+
+static const int flash_bank;
+static uint8_t page_buffer[NAND_MAX_PAGESIZE];
+static int page_size, oob_size, pages_per_block;
+
+static void index_addr(uint32_t address, uint32_t data)
+{
+	writel(address, denali_flash_mem + INDEX_CTRL_REG);
+	writel(data, denali_flash_mem + INDEX_DATA_REG);
+}
+
+static int wait_for_irq(uint32_t irq_mask)
+{
+	unsigned long timeout = 1000000;
+	uint32_t intr_status;
+
+	do {
+		intr_status = readl(denali_flash_reg + INTR_STATUS(flash_bank));
+
+		if (intr_status & INTR_STATUS__ECC_UNCOR_ERR) {
+			debug("Uncorrected ECC detected\n");
+			return -EIO;
+		}
+
+		if (intr_status & irq_mask)
+			break;
+
+		udelay(1);
+		timeout--;
+	} while (timeout);
+
+	if (!timeout) {
+		debug("Timeout with interrupt status %08x\n", intr_status);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static void read_data_from_flash_mem(uint8_t *buf, int len)
+{
+	int i;
+	uint32_t *buf32;
+
+	/* transfer the data from the flash */
+	buf32 = (uint32_t *)buf;
+
+	/*
+	 * Let's take care of unaligned access although it rarely happens.
+	 * Avoid put_unaligned() for the normal use cases since it leads to
+	 * a bit performance regression.
+	 */
+	if ((unsigned long)buf32 % 4) {
+		for (i = 0; i < len / 4; i++)
+			put_unaligned(readl(denali_flash_mem + INDEX_DATA_REG),
+				      buf32++);
+	} else {
+		for (i = 0; i < len / 4; i++)
+			*buf32++ = readl(denali_flash_mem + INDEX_DATA_REG);
+	}
+
+	if (len % 4) {
+		u32 tmp;
+
+		tmp = cpu_to_le32(readl(denali_flash_mem + INDEX_DATA_REG));
+		buf = (uint8_t *)buf32;
+		for (i = 0; i < len % 4; i++) {
+			*buf++ = tmp;
+			tmp >>= 8;
+		}
+	}
+}
+
+int denali_send_pipeline_cmd(int page, int ecc_en, int access_type)
+{
+	uint32_t addr, cmd;
+	static uint32_t page_count = 1;
+
+	writel(ecc_en, denali_flash_reg + ECC_ENABLE);
+
+	/* clear all bits of intr_status. */
+	writel(0xffff, denali_flash_reg + INTR_STATUS(flash_bank));
+
+	addr = BANK(flash_bank) | page;
+
+	/* setup the acccess type */
+	cmd = MODE_10 | addr;
+	index_addr(cmd, access_type);
+
+	/* setup the pipeline command */
+	index_addr(cmd, PIPELINE_ACCESS | page_count);
+
+	cmd = MODE_01 | addr;
+	writel(cmd, denali_flash_mem + INDEX_CTRL_REG);
+
+	return wait_for_irq(INTR_STATUS__LOAD_COMP);
+}
+
+static int nand_read_oob(void *buf, int page)
+{
+	int ret;
+
+	ret = denali_send_pipeline_cmd(page, 0, SPARE_ACCESS);
+	if (ret < 0)
+		return ret;
+
+	read_data_from_flash_mem(buf, oob_size);
+
+	return 0;
+}
+
+static int nand_read_page(void *buf, int page)
+{
+	int ret;
+
+	ret = denali_send_pipeline_cmd(page, 1, MAIN_ACCESS);
+	if (ret < 0)
+		return ret;
+
+	read_data_from_flash_mem(buf, page_size);
+
+	return 0;
+}
+
+static int nand_block_isbad(int block)
+{
+	int ret;
+
+	ret = nand_read_oob(page_buffer, block * pages_per_block);
+	if (ret < 0)
+		return ret;
+
+	return page_buffer[CONFIG_SYS_NAND_BAD_BLOCK_POS] != 0xff;
+}
+
+/* nand_init() - initialize data to make nand usable by SPL */
+void nand_init(void)
+{
+	/* access to main area */
+	writel(0, denali_flash_reg + TRANSFER_SPARE_REG);
+
+	/*
+	 * These registers are expected to be already set by the hardware
+	 * or earlier boot code.  So we read these values out.
+	 */
+	page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE);
+	oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE);
+	pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK);
+}
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
+{
+	int block, page, column, readlen;
+	int ret;
+	int force_bad_block_check = 1;
+
+	page = offs / page_size;
+	column = offs % page_size;
+
+	block = page / pages_per_block;
+	page = page % pages_per_block;
+
+	while (size) {
+		if (force_bad_block_check || page == 0) {
+			ret = nand_block_isbad(block);
+			if (ret < 0)
+				return ret;
+
+			if (ret) {
+				block++;
+				continue;
+			}
+		}
+
+		force_bad_block_check = 0;
+
+		if (unlikely(column || size < page_size)) {
+			/* Partial page read */
+			ret = nand_read_page(page_buffer,
+					     block * pages_per_block + page);
+			if (ret < 0)
+				return ret;
+
+			readlen = min(page_size - column, size);
+			memcpy(dst, page_buffer, readlen);
+
+			column = 0;
+		} else {
+			ret = nand_read_page(dst,
+					     block * pages_per_block + page);
+			if (ret < 0)
+				return ret;
+
+			readlen = page_size;
+		}
+
+		size -= readlen;
+		dst += readlen;
+		page++;
+		if (page == pages_per_block) {
+			block++;
+			page = 0;
+		}
+	}
+
+	return 0;
+}
+
+void nand_deselect(void) {}
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 7e1e6ec78b..3372b64212 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -37,7 +37,6 @@
 
 #define MAX_BANKS 8
 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
-#define FCM_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for FCM */
 
 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
 
@@ -199,7 +198,8 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 	fsl_lbc_t *lbc = ctrl->regs;
-	long long end_tick;
+	u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
+	u32 time_start;
 	u32 ltesr;
 
 	/* Setup the FMR[OP] to execute without write protection */
@@ -218,10 +218,10 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
 	out_be32(&lbc->lsor, priv->bank);
 
 	/* wait for FCM complete flag or timeout */
-	end_tick = usec2ticks(FCM_TIMEOUT_MSECS * 1000) + get_ticks();
+	time_start = get_timer(0);
 
 	ltesr = 0;
-	while (end_tick > get_ticks()) {
+	while (get_timer(time_start) < timeo) {
 		ltesr = in_be32(&lbc->ltesr);
 		if (ltesr & LTESR_CC)
 			break;
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 2f04c698d3..81b5070b54 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -26,8 +26,6 @@
 #define MAX_BANKS	CONFIG_SYS_FSL_IFC_BANK_COUNT
 #define ERR_BYTE	0xFF /* Value returned for read bytes
 				when read failed */
-#define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC
-				NAND Machine */
 
 struct fsl_ifc_ctrl;
 
@@ -292,7 +290,8 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
 	struct fsl_ifc_mtd *priv = chip->priv;
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	struct fsl_ifc *ifc = ctrl->regs;
-	long long end_tick;
+	u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
+	u32 time_start;
 	u32 eccstat[4];
 	int i;
 
@@ -304,9 +303,9 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
 		  IFC_NAND_SEQ_STRT_FIR_STRT);
 
 	/* wait for NAND Machine complete flag or timeout */
-	end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
+	time_start = get_timer(0);
 
-	while (end_tick > get_ticks()) {
+	while (get_timer(time_start) < timeo) {
 		ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 
 		if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
@@ -812,15 +811,16 @@ static int fsl_ifc_sram_init(uint32_t ver)
 	struct fsl_ifc *ifc = ifc_ctrl->regs;
 	uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
 	uint32_t ncfgr = 0;
-	long long end_tick;
+	u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
+	u32 time_start;
 
 	if (ver > FSL_IFC_V1_1_0) {
 		ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
 		ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
 
 		/* wait for  SRAM_INIT bit to be clear or timeout */
-		end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
-		while (end_tick > get_ticks()) {
+		time_start = get_timer(0);
+		while (get_timer(time_start) < timeo) {
 			ifc_ctrl->status =
 				ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 
@@ -863,10 +863,9 @@ static int fsl_ifc_sram_init(uint32_t ver)
 	/* start read seq */
 	ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
 
-	/* wait for NAND Machine complete flag or timeout */
-	end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
+	time_start = get_timer(0);
 
-	while (end_tick > get_ticks()) {
+	while (get_timer(time_start) < timeo) {
 		ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 
 		if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 7153e3ca36..0b6e7ee385 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -308,8 +308,7 @@ static void ioread16_rep(void *addr, void *buf, int len)
 {
 	int i;
  	u16 *p = (u16 *) buf;
-	len >>= 1;
- 
+
 	for (i = 0; i < len; i++)
 		p[i] = readw(addr);
 }
@@ -318,7 +317,6 @@ static void iowrite16_rep(void *addr, void *buf, int len)
 {
 	int i;
         u16 *p = (u16 *) buf;
-        len >>= 1;
 
         for (i = 0; i < len; i++)
                 writew(p[i], addr);
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index a62ef4cbbd..98e0a34d4e 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -51,46 +51,7 @@ static const char *sandbox_sf_state_name(enum sandbox_sf_state state)
 /* Assume all SPI flashes have 3 byte addresses since they do atm */
 #define SF_ADDR_LEN	3
 
-struct sandbox_spi_flash_erase_commands {
-	u8 cmd;
-	u32 size;
-};
-#define IDCODE_LEN 5
-#define MAX_ERASE_CMDS 3
-struct sandbox_spi_flash_data {
-	const char *name;
-	u8 idcode[IDCODE_LEN];
-	u32 size;
-	const struct sandbox_spi_flash_erase_commands
-						erase_cmds[MAX_ERASE_CMDS];
-};
-
-/* Structure describing all the flashes we know how to emulate */
-static const struct sandbox_spi_flash_data sandbox_sf_flashes[] = {
-	{
-		"M25P16", { 0x20, 0x20, 0x15 }, (2 << 20),
-		{	/* erase commands */
-			{ 0xd8, (64 << 10), }, /* sector */
-			{ 0xc7, (2 << 20), }, /* bulk */
-		},
-	},
-	{
-		"W25Q32", { 0xef, 0x40, 0x16 }, (4 << 20),
-		{	/* erase commands */
-			{ 0x20, (4 << 10), }, /* 4KB */
-			{ 0xd8, (64 << 10), }, /* sector */
-			{ 0xc7, (4 << 20), }, /* bulk */
-		},
-	},
-	{
-		"W25Q128", { 0xef, 0x40, 0x18 }, (16 << 20),
-		{	/* erase commands */
-			{ 0x20, (4 << 10), }, /* 4KB */
-			{ 0xd8, (64 << 10), }, /* sector */
-			{ 0xc7, (16 << 20), }, /* bulk */
-		},
-	},
-};
+#define IDCODE_LEN 3
 
 /* Used to quickly bulk erase backing store */
 static u8 sandbox_sf_0xff[0x1000];
@@ -109,7 +70,8 @@ struct sandbox_spi_flash {
 	 */
 	enum sandbox_sf_state state;
 	uint cmd;
-	const void *cmd_data;
+	/* Erase size of current erase command */
+	uint erase_size;
 	/* Current position in the flash; used when reading/writing/etc... */
 	uint off;
 	/* How many address bytes we've consumed */
@@ -117,7 +79,7 @@ struct sandbox_spi_flash {
 	/* The current flash status (see STAT_XXX defines above) */
 	u16 status;
 	/* Data describing the flash we're emulating */
-	const struct sandbox_spi_flash_data *data;
+	const struct spi_flash_params *data;
 	/* The file on disk to serv up data from */
 	int fd;
 };
@@ -127,8 +89,8 @@ static int sandbox_sf_setup(void **priv, const char *spec)
 	/* spec = idcode:file */
 	struct sandbox_spi_flash *sbsf;
 	const char *file;
-	size_t i, len, idname_len;
-	const struct sandbox_spi_flash_data *data;
+	size_t len, idname_len;
+	const struct spi_flash_params *data;
 
 	file = strchr(spec, ':');
 	if (!file) {
@@ -138,15 +100,14 @@ static int sandbox_sf_setup(void **priv, const char *spec)
 	idname_len = file - spec;
 	++file;
 
-	for (i = 0; i < ARRAY_SIZE(sandbox_sf_flashes); ++i) {
-		data = &sandbox_sf_flashes[i];
+	for (data = spi_flash_params_table; data->name; data++) {
 		len = strlen(data->name);
 		if (idname_len != len)
 			continue;
 		if (!memcmp(spec, data->name, len))
 			break;
 	}
-	if (i == ARRAY_SIZE(sandbox_sf_flashes)) {
+	if (!data->name) {
 		printf("sandbox_sf: unknown flash '%*s'\n", (int)idname_len,
 		       spec);
 		goto error;
@@ -223,7 +184,6 @@ static int sandbox_sf_process_cmd(struct sandbox_spi_flash *sbsf, const u8 *rx,
 		sbsf->pad_addr_bytes = 1;
 	case CMD_READ_ARRAY_SLOW:
 	case CMD_PAGE_PROGRAM:
- state_addr:
 		sbsf->state = SF_ADDR;
 		break;
 	case CMD_WRITE_DISABLE:
@@ -241,24 +201,25 @@ static int sandbox_sf_process_cmd(struct sandbox_spi_flash *sbsf, const u8 *rx,
 		sbsf->status |= STAT_WEL;
 		break;
 	default: {
-		size_t i;
+		int flags = sbsf->data->flags;
 
-		/* handle erase commands first */
-		for (i = 0; i < MAX_ERASE_CMDS; ++i) {
-			const struct sandbox_spi_flash_erase_commands *
-				erase_cmd = &sbsf->data->erase_cmds[i];
-
-			if (erase_cmd->cmd == 0x00)
-				continue;
-			if (sbsf->cmd != erase_cmd->cmd)
-				continue;
-
-			sbsf->cmd_data = erase_cmd;
-			goto state_addr;
+		/* we only support erase here */
+		if (sbsf->cmd == CMD_ERASE_CHIP) {
+			sbsf->erase_size = sbsf->data->sector_size *
+				sbsf->data->nr_sectors;
+		} else if (sbsf->cmd == CMD_ERASE_4K && (flags & SECT_4K)) {
+			sbsf->erase_size = 4 << 10;
+		} else if (sbsf->cmd == CMD_ERASE_32K && (flags & SECT_32K)) {
+			sbsf->erase_size = 32 << 10;
+		} else if (sbsf->cmd == CMD_ERASE_64K &&
+			   !(flags & (SECT_4K | SECT_32K))) {
+			sbsf->erase_size = 64 << 10;
+		} else {
+			debug(" cmd unknown: %#x\n", sbsf->cmd);
+			return 1;
 		}
-
-		debug(" cmd unknown: %#x\n", sbsf->cmd);
-		return 1;
+		sbsf->state = SF_ADDR;
+		break;
 	}
 	}
 
@@ -309,11 +270,14 @@ static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
 			u8 id;
 
 			debug(" id: off:%u tx:", sbsf->off);
-			if (sbsf->off < IDCODE_LEN)
-				id = sbsf->data->idcode[sbsf->off];
-			else
+			if (sbsf->off < IDCODE_LEN) {
+				/* Extract correct byte from ID 0x00aabbcc */
+				id = sbsf->data->jedec >>
+					(8 * (IDCODE_LEN - 1 - sbsf->off));
+			} else {
 				id = 0;
-			debug("%02x\n", id);
+			}
+			debug("%d %02x\n", sbsf->off, id);
 			tx[pos++] = id;
 			++sbsf->off;
 			break;
@@ -406,24 +370,22 @@ static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
 			break;
 		case SF_ERASE:
  case_sf_erase: {
-			const struct sandbox_spi_flash_erase_commands *
-						erase_cmd = sbsf->cmd_data;
-
 			if (!(sbsf->status & STAT_WEL)) {
 				puts("sandbox_sf: write enable not set before erase\n");
 				goto done;
 			}
 
 			/* verify address is aligned */
-			if (sbsf->off & (erase_cmd->size - 1)) {
+			if (sbsf->off & (sbsf->erase_size - 1)) {
 				debug(" sector erase: cmd:%#x needs align:%#x, but we got %#x\n",
-				      erase_cmd->cmd, erase_cmd->size,
+				      sbsf->cmd, sbsf->erase_size,
 				      sbsf->off);
 				sbsf->status &= ~STAT_WEL;
 				goto done;
 			}
 
-			debug(" sector erase addr: %u\n", sbsf->off);
+			debug(" sector erase addr: %u, size: %u\n", sbsf->off,
+			      sbsf->erase_size);
 
 			cnt = bytes - pos;
 			sandbox_spi_tristate(&tx[pos], cnt);
@@ -433,7 +395,7 @@ static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
 			 * TODO(vapier@gentoo.org): latch WIP in status, and
 			 * delay before clearing it ?
 			 */
-			ret = sandbox_erase_part(sbsf, erase_cmd->size);
+			ret = sandbox_erase_part(sbsf, sbsf->erase_size);
 			sbsf->status &= ~STAT_WEL;
 			if (ret) {
 				debug("sandbox_sf: Erase failed\n");
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index ac886fd071..453edf0149 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -68,9 +68,12 @@ const struct spi_flash_params spi_flash_params_table[] = {
 	{"M25P40",	   0x202013, 0x0,       64 * 1024,     8,	0,			  0},
 	{"M25P80",	   0x202014, 0x0,       64 * 1024,    16,	0,			  0},
 	{"M25P16",	   0x202015, 0x0,       64 * 1024,    32,	0,			  0},
+	{"M25PE16",	   0x208015, 0x1000,    64 * 1024,    32,	0,			  0},
+	{"M25PX16",	   0x207115, 0x1000,    64 * 1024,    32, RD_EXTN,			  0},
 	{"M25P32",	   0x202016, 0x0,       64 * 1024,    64,	0,			  0},
 	{"M25P64",	   0x202017, 0x0,       64 * 1024,   128,	0,			  0},
 	{"M25P128",	   0x202018, 0x0,      256 * 1024,    64,	0,			  0},
+	{"M25PX64",	   0x207117, 0x0,       64 * 1024,   128,	0,		    SECT_4K},
 	{"N25Q32",	   0x20ba16, 0x0,       64 * 1024,    64, RD_FULL,	   WR_QPP | SECT_4K},
 	{"N25Q32A",	   0x20bb16, 0x0,       64 * 1024,    64, RD_FULL,	   WR_QPP | SECT_4K},
 	{"N25Q64",	   0x20ba17, 0x0,       64 * 1024,   128, RD_FULL,	   WR_QPP | SECT_4K},
@@ -116,6 +119,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
 	{"W25Q64DW",	   0xef6017, 0x0,	64 * 1024,   128, RD_FULL,	    WR_QPP | SECT_4K},
 	{"W25Q128FW",	   0xef6018, 0x0,	64 * 1024,   256, RD_FULL,	    WR_QPP | SECT_4K},
 #endif
+	{},	/* Empty entry to terminate the list */
 	/*
 	 * Note:
 	 * Below paired flash devices has similar spi_flash params.
diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c
index 1954b7e886..59cca0f4d9 100644
--- a/drivers/mtd/spi/spi_spl_load.c
+++ b/drivers/mtd/spi/spi_spl_load.c
@@ -56,8 +56,10 @@ void spl_spi_load_image(void)
 	 * Load U-Boot image from SPI flash into RAM
 	 */
 
-	flash = spi_flash_probe(CONFIG_SPL_SPI_BUS, CONFIG_SPL_SPI_CS,
-				CONFIG_SF_DEFAULT_SPEED, SPI_MODE_3);
+	flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
+				CONFIG_SF_DEFAULT_CS,
+				CONFIG_SF_DEFAULT_SPEED,
+				CONFIG_SF_DEFAULT_MODE);
 	if (!flash) {
 		puts("SPI probe failed.\n");
 		hang();
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 0eba57cf0c..6e8765cf7b 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -5362,7 +5362,9 @@ e1000_initialize(bd_t * bis)
 		hw->autoneg_failed = 0;
 		hw->autoneg = 1;
 		hw->get_link_status = true;
+#ifndef CONFIG_E1000_NO_NVM
 		hw->eeprom_semaphore_present = true;
+#endif
 		hw->hw_addr = pci_map_bar(devno,	PCI_BASE_ADDRESS_0,
 							PCI_REGION_MEM);
 		hw->mac_type = e1000_undefined;
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 4cefda48e4..549d648613 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -28,6 +28,14 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 #define FEC_XFER_TIMEOUT	5000
 
+/*
+ * The standard 32-byte DMA alignment does not work on mx6solox, which requires
+ * 64-byte alignment in the DMA RX FEC buffer.
+ * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
+ * satisfies the alignment on other SoCs (32-bytes)
+ */
+#define FEC_DMA_RX_MINALIGN	64
+
 #ifndef CONFIG_MII
 #error "CONFIG_MII has to be defined!"
 #endif
@@ -711,13 +719,37 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
 			break;
 	}
 
+	if (!timeout) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	/*
+	 * The TDAR bit is cleared when the descriptors are all out from TX
+	 * but on mx6solox we noticed that the READY bit is still not cleared
+	 * right after TDAR.
+	 * These are two distinct signals, and in IC simulation, we found that
+	 * TDAR always gets cleared prior than the READY bit of last BD becomes
+	 * cleared.
+	 * In mx6solox, we use a later version of FEC IP. It looks like that
+	 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
+	 * version.
+	 *
+	 * Fix this by polling the READY bit of BD after the TDAR polling,
+	 * which covers the mx6solox case and does not harm the other SoCs.
+	 */
+	timeout = FEC_XFER_TIMEOUT;
+	while (--timeout) {
+		invalidate_dcache_range(addr, addr + size);
+		if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
+		    FEC_TBD_READY))
+			break;
+	}
+
 	if (!timeout)
 		ret = -EINVAL;
 
-	invalidate_dcache_range(addr, addr + size);
-	if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)
-		ret = -EINVAL;
-
+out:
 	debug("fec_send: status 0x%x index %d ret %i\n",
 			readw(&fec->tbd_base[fec->tbd_index].status),
 			fec->tbd_index, ret);
@@ -881,9 +913,9 @@ static int fec_alloc_descs(struct fec_priv *fec)
 	/* Allocate RX buffers. */
 
 	/* Maximum RX buffer size. */
-	size = roundup(FEC_MAX_PKT_SIZE, ARCH_DMA_MINALIGN);
+	size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
 	for (i = 0; i < FEC_RBD_NUM; i++) {
-		data = memalign(ARCH_DMA_MINALIGN, size);
+		data = memalign(FEC_DMA_RX_MINALIGN, size);
 		if (!data) {
 			printf("%s: error allocating rxbuf %d\n", __func__, i);
 			goto err_ring;
diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c
index bcc871d842..4cce46d7f8 100644
--- a/drivers/net/fm/t1040.c
+++ b/drivers/net/fm/t1040.c
@@ -49,8 +49,6 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
 		else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
 				FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII)
 			return PHY_INTERFACE_MODE_MII;
-		else
-			return PHY_INTERFACE_MODE_NONE;
 	}
 
 	switch (port) {
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 4fd9c532b3..28859f3161 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -648,6 +648,10 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus)
 		pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
 		pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 
+#ifdef CONFIG_PCI_FIXUP_DEV
+		board_pci_fixup_dev(hose, dev, vendor, device, class);
+#endif
+
 #ifdef CONFIG_PCI_SCAN_SHOW
 		indent++;
 
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index a3982c4553..fd7e4d499f 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -23,13 +23,20 @@
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
 
+#ifdef CONFIG_MX6SX
+#define MX6_DBI_ADDR	0x08ffc000
+#define MX6_IO_ADDR	0x08000000
+#define MX6_MEM_ADDR	0x08100000
+#define MX6_ROOT_ADDR	0x08f00000
+#else
 #define MX6_DBI_ADDR	0x01ffc000
-#define MX6_DBI_SIZE	0x4000
 #define MX6_IO_ADDR	0x01000000
-#define MX6_IO_SIZE	0x100000
 #define MX6_MEM_ADDR	0x01100000
-#define MX6_MEM_SIZE	0xe00000
 #define MX6_ROOT_ADDR	0x01f00000
+#endif
+#define MX6_DBI_SIZE	0x4000
+#define MX6_IO_SIZE	0x100000
+#define MX6_MEM_SIZE	0xe00000
 #define MX6_ROOT_SIZE	0xfc000
 
 /* PCIe Port Logic registers (memory-mapped) */
@@ -57,6 +64,8 @@
 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
 
+#define PCIE_PHY_PUP_REQ		(1 << 7)
+
 /* iATU registers */
 #define PCIE_ATU_VIEWPORT		0x900
 #define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
@@ -421,9 +430,19 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
 static int imx6_pcie_assert_core_reset(void)
 {
 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+#if defined(CONFIG_MX6SX)
+	struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
 
+	/* SSP_EN is not used on MX6SX anymore */
+	setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
+	/* Force PCIe PHY reset */
+	setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
+	/* Power up PCIe PHY */
+	setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
+#else
 	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
 	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+#endif
 
 	return 0;
 }
@@ -441,6 +460,12 @@ static int imx6_pcie_init_phy(void)
 			IOMUXC_GPR12_LOS_LEVEL_MASK,
 			IOMUXC_GPR12_LOS_LEVEL_9);
 
+#ifdef CONFIG_MX6SX
+	clrsetbits_le32(&iomuxc_regs->gpr[12],
+			IOMUXC_GPR12_RX_EQ_MASK,
+			IOMUXC_GPR12_RX_EQ_2);
+#endif
+
 	writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
 	       (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
 	       (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
@@ -517,9 +542,16 @@ static int imx6_pcie_deassert_core_reset(void)
 	 */
 	mdelay(50);
 
+#if defined(CONFIG_MX6SX)
+	/* SSP_EN is not used on MX6SX anymore */
+	clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
+	/* Clear PCIe PHY reset bit */
+	clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
+#else
 	/* Enable PCIe */
 	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
 	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+#endif
 
 	imx6_pcie_toggle_reset();
 
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 853a8c6919..b4f299bb0e 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
 obj-$(CONFIG_MXS_AUART) += mxs_auart.o
 obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
 obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
+obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index d04104e747..1ac943f692 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -25,6 +25,7 @@ struct udevice *cur_dev __attribute__ ((section(".data")));
 
 static void serial_find_console_or_panic(void)
 {
+#ifdef CONFIG_OF_CONTROL
 	int node;
 
 	/* Check for a chosen console */
@@ -44,7 +45,7 @@ static void serial_find_console_or_panic(void)
 			return;
 		cur_dev = NULL;
 	}
-
+#endif
 	/*
 	 * Failing that, get the device with sequence number 0, or in extremis
 	 * just the first serial device we can find. But we insist on having
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index bbe60af627..82fbbd92e2 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -157,6 +157,7 @@ serial_initfunc(sh_serial_initialize);
 serial_initfunc(arm_dcc_initialize);
 serial_initfunc(mxs_auart_initialize);
 serial_initfunc(arc_serial_initialize);
+serial_initfunc(uniphier_serial_initialize);
 
 /**
  * serial_register() - Register serial driver with serial driver core
@@ -250,6 +251,7 @@ void serial_initialize(void)
 	arm_dcc_initialize();
 	mxs_auart_initialize();
 	arc_serial_initialize();
+	uniphier_serial_initialize();
 
 	serial_assign(default_serial_console()->name);
 }
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index b0c6f6f4ab..63fc388b26 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -14,8 +14,13 @@
 
 #define US1_TDRE        (1 << 7)
 #define US1_RDRF        (1 << 5)
+#define US1_OR          (1 << 3)
 #define UC2_TE          (1 << 3)
 #define UC2_RE          (1 << 2)
+#define CFIFO_TXFLUSH   (1 << 7)
+#define CFIFO_RXFLUSH   (1 << 6)
+#define SFIFO_RXOF      (1 << 2)
+#define SFIFO_RXUF      (1 << 0)
 
 #define STAT_LBKDIF	(1 << 31)
 #define STAT_RXEDGIF	(1 << 30)
@@ -62,14 +67,10 @@ static void lpuart_serial_setbrg(void)
 
 static int lpuart_serial_getc(void)
 {
-	u8 status;
-
-	while (!(__raw_readb(&base->us1) & US1_RDRF))
+	while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
 		WATCHDOG_RESET();
 
-	status = __raw_readb(&base->us1);
-	status |= US1_RDRF;
-	__raw_writeb(status, &base->us1);
+	barrier();
 
 	return __raw_readb(&base->ud);
 }
@@ -112,6 +113,12 @@ static int lpuart_serial_init(void)
 	__raw_writeb(0, &base->umodem);
 	__raw_writeb(0, &base->uc1);
 
+	/* Disable FIFO and flush buffer */
+	__raw_writeb(0x0, &base->upfifo);
+	__raw_writeb(0x0, &base->utwfifo);
+	__raw_writeb(0x1, &base->urwfifo);
+	__raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
+
 	/* provide data bits, parity, stop bit, etc */
 
 	serial_setbrg();
diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c
new file mode 100644
index 0000000000..f8c9d921e2
--- /dev/null
+++ b/drivers/serial/serial_uniphier.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * Based on serial_ns16550.c
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <serial.h>
+
+#define UART_REG(x)					\
+	u8 x;						\
+	u8 postpad_##x[3];
+
+/*
+ * Note: Register map is slightly different from that of 16550.
+ */
+struct uniphier_serial {
+	UART_REG(rbr);		/* 0x00 */
+	UART_REG(ier);		/* 0x04 */
+	UART_REG(iir);		/* 0x08 */
+	UART_REG(fcr);		/* 0x0c */
+	u8 mcr;			/* 0x10 */
+	u8 lcr;
+	u16 __postpad;
+	UART_REG(lsr);		/* 0x14 */
+	UART_REG(msr);		/* 0x18 */
+	u32 __none1;
+	u32 __none2;
+	u16 dlr;
+	u16 __postpad2;
+};
+
+#define thr rbr
+
+/*
+ * These are the definitions for the Line Control Register
+ */
+#define UART_LCR_WLS_8	0x03		/* 8 bit character length */
+
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_DR	0x01		/* Data ready */
+#define UART_LSR_THRE	0x20		/* Xmit holding register empty */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void uniphier_serial_init(struct uniphier_serial *port)
+{
+	const unsigned int mode_x_div = 16;
+	unsigned int divisor;
+
+	writeb(UART_LCR_WLS_8, &port->lcr);
+
+	divisor = DIV_ROUND_CLOSEST(CONFIG_SYS_UNIPHIER_UART_CLK,
+						mode_x_div * gd->baudrate);
+
+	writew(divisor, &port->dlr);
+}
+
+static void uniphier_serial_setbrg(struct uniphier_serial *port)
+{
+	uniphier_serial_init(port);
+}
+
+static int uniphier_serial_tstc(struct uniphier_serial *port)
+{
+	return (readb(&port->lsr) & UART_LSR_DR) != 0;
+}
+
+static int uniphier_serial_getc(struct uniphier_serial *port)
+{
+	while (!uniphier_serial_tstc(port))
+		;
+
+	return readb(&port->rbr);
+}
+
+static void uniphier_serial_putc(struct uniphier_serial *port, const char c)
+{
+	if (c == '\n')
+		uniphier_serial_putc(port, '\r');
+
+	while (!(readb(&port->lsr) & UART_LSR_THRE))
+		;
+
+	writeb(c, &port->thr);
+}
+
+static struct uniphier_serial *serial_ports[4] = {
+#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE0
+	(struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE0,
+#else
+	NULL,
+#endif
+#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE1
+	(struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE1,
+#else
+	NULL,
+#endif
+#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE2
+	(struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE2,
+#else
+	NULL,
+#endif
+#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE3
+	(struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE3,
+#else
+	NULL,
+#endif
+};
+
+/* Multi serial device functions */
+#define DECLARE_ESERIAL_FUNCTIONS(port) \
+	static int  eserial##port##_init(void) \
+	{ \
+		uniphier_serial_init(serial_ports[port]); \
+		return 0 ; \
+	} \
+	static void eserial##port##_setbrg(void) \
+	{ \
+		uniphier_serial_setbrg(serial_ports[port]); \
+	} \
+	static int  eserial##port##_getc(void) \
+	{ \
+		return uniphier_serial_getc(serial_ports[port]); \
+	} \
+	static int  eserial##port##_tstc(void) \
+	{ \
+		return uniphier_serial_tstc(serial_ports[port]); \
+	} \
+	static void eserial##port##_putc(const char c) \
+	{ \
+		uniphier_serial_putc(serial_ports[port], c); \
+	}
+
+/* Serial device descriptor */
+#define INIT_ESERIAL_STRUCTURE(port, __name) {	\
+	.name	= __name,			\
+	.start	= eserial##port##_init,		\
+	.stop	= NULL,				\
+	.setbrg	= eserial##port##_setbrg,	\
+	.getc	= eserial##port##_getc,		\
+	.tstc	= eserial##port##_tstc,		\
+	.putc	= eserial##port##_putc,		\
+	.puts	= default_serial_puts,		\
+}
+
+#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE0)
+DECLARE_ESERIAL_FUNCTIONS(0);
+struct serial_device uniphier_serial0_device =
+	INIT_ESERIAL_STRUCTURE(0, "ttyS0");
+#endif
+#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE1)
+DECLARE_ESERIAL_FUNCTIONS(1);
+struct serial_device uniphier_serial1_device =
+	INIT_ESERIAL_STRUCTURE(1, "ttyS1");
+#endif
+#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE2)
+DECLARE_ESERIAL_FUNCTIONS(2);
+struct serial_device uniphier_serial2_device =
+	INIT_ESERIAL_STRUCTURE(2, "ttyS2");
+#endif
+#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE3)
+DECLARE_ESERIAL_FUNCTIONS(3);
+struct serial_device uniphier_serial3_device =
+	INIT_ESERIAL_STRUCTURE(3, "ttyS3");
+#endif
+
+__weak struct serial_device *default_serial_console(void)
+{
+#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE0)
+	return &uniphier_serial0_device;
+#elif defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE1)
+	return &uniphier_serial1_device;
+#elif defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE2)
+	return &uniphier_serial2_device;
+#elif defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE3)
+	return &uniphier_serial3_device;
+#else
+#error "No uniphier serial ports configured."
+#endif
+}
+
+void uniphier_serial_initialize(void)
+{
+#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE0)
+	serial_register(&uniphier_serial0_device);
+#endif
+#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE1)
+	serial_register(&uniphier_serial1_device);
+#endif
+#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE2)
+	serial_register(&uniphier_serial2_device);
+#endif
+#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE3)
+	serial_register(&uniphier_serial3_device);
+#endif
+}
diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c
index b030526b6a..7fb0b92078 100644
--- a/drivers/serial/usbtty.c
+++ b/drivers/serial/usbtty.c
@@ -475,7 +475,7 @@ static void __usbtty_puts (const char *str, int len)
 		if (space) {
 			write_buffer (&usbtty_output);
 
-			n = MIN (space, MIN (len, maxlen));
+			n = min(space, min(len, maxlen));
 			buf_push (&usbtty_output, str, n);
 
 			str += n;
@@ -882,7 +882,7 @@ static int write_buffer (circbuf_t * buf)
 			space_avail =
 				current_urb->buffer_length -
 				current_urb->actual_length;
-			popnum = MIN (space_avail, buf->size);
+			popnum = min(space_avail, buf->size);
 			if (popnum == 0)
 				break;
 
diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index 942a208c2c..3d58bcc1b9 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -18,7 +18,7 @@
 
 static struct kwspi_registers *spireg = (struct kwspi_registers *)KW_SPI_BASE;
 
-u32 cs_spi_mpp_back[2];
+static u32 cs_spi_mpp_back[2];
 
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 				unsigned int max_hz, unsigned int mode)
@@ -37,7 +37,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	if (!slave)
 		return NULL;
 
-	writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, &spireg->ctrl);
+	writel(KWSPI_SMEMRDY, &spireg->ctrl);
 
 	/* calculate spi clock prescaller using max_hz */
 	data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
@@ -46,7 +46,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 
 	/* program spi clock prescaller using max_hz */
 	writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
-	debug("data = 0x%08x \n", data);
+	debug("data = 0x%08x\n", data);
 
 	writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
 	writel(KWSPI_IRQMASK, &spireg->irq_mask);
@@ -100,7 +100,6 @@ int spi_claim_bus(struct spi_slave *slave)
 
 	/* set new spi mpp and save current mpp config */
 	kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
-
 #endif
 
 	return board_spi_claim_bus(slave);
@@ -127,7 +126,7 @@ void spi_release_bus(struct spi_slave *slave)
  */
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {
-	return (bus == 0 && (cs == 0 || cs == 1));
+	return bus == 0 && (cs == 0 || cs == 1);
 }
 #endif
 
@@ -137,12 +136,12 @@ void spi_init(void)
 
 void spi_cs_activate(struct spi_slave *slave)
 {
-	writel(readl(&spireg->ctrl) | KWSPI_IRQUNMASK, &spireg->ctrl);
+	setbits_le32(&spireg->ctrl, KWSPI_CSN_ACT);
 }
 
 void spi_cs_deactivate(struct spi_slave *slave)
 {
-	writel(readl(&spireg->ctrl) & KWSPI_IRQMASK, &spireg->ctrl);
+	clrbits_le32(&spireg->ctrl, KWSPI_CSN_ACT);
 }
 
 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
@@ -161,8 +160,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 	 * handle data in 8-bit chunks
 	 * TBD: 2byte xfer mode to be enabled
 	 */
-	writel(((readl(&spireg->cfg) & ~KWSPI_XFERLEN_MASK) |
-		KWSPI_XFERLEN_1BYTE), &spireg->cfg);
+	clrsetbits_le32(&spireg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
 
 	while (bitlen > 4) {
 		debug("loopstart bitlen %d\n", bitlen);
@@ -170,9 +168,9 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 
 		/* Shift data so it's msb-justified */
 		if (dout)
-			tmpdout = *(u32 *) dout & 0x0ff;
+			tmpdout = *(u32 *)dout & 0xff;
 
-		writel(~KWSPI_SMEMRDIRQ, &spireg->irq_cause);
+		clrbits_le32(&spireg->irq_cause, KWSPI_SMEMRDIRQ);
 		writel(tmpdout, &spireg->dout);	/* Write the data out */
 		debug("*** spi_xfer: ... %08x written, bitlen %d\n",
 		      tmpdout, bitlen);
@@ -186,12 +184,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 			if (readl(&spireg->irq_cause) & KWSPI_SMEMRDIRQ) {
 				isread = 1;
 				tmpdin = readl(&spireg->din);
-				debug
-					("spi_xfer: din %p..%08x read\n",
-					din, tmpdin);
+				debug("spi_xfer: din %p..%08x read\n",
+				      din, tmpdin);
 
 				if (din) {
-					*((u8 *) din) = (u8) tmpdin;
+					*((u8 *)din) = (u8)tmpdin;
 					din += 1;
 				}
 				if (dout)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 2d5f3850da..026f680d80 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -25,6 +25,11 @@ static unsigned long spi_bases[] = {
 	MXC_SPI_BASE_ADDRESSES
 };
 
+__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return -1;
+}
+
 #define OUT	MXC_GPIO_DIRECTION_OUT
 
 #define reg_read readl
@@ -371,31 +376,30 @@ void spi_init(void)
 {
 }
 
-static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
+/*
+ * Some SPI devices require active chip-select over multiple
+ * transactions, we achieve this using a GPIO. Still, the SPI
+ * controller has to be configured to use one of its own chipselects.
+ * To use this feature you have to implement board_spi_cs_gpio() to assign
+ * a gpio value for each cs (-1 if cs doesn't need to use gpio).
+ * You must use some unused on this SPI controller cs between 0 and 3.
+ */
+static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
+			 unsigned int bus, unsigned int cs)
 {
 	int ret;
 
-	/*
-	 * Some SPI devices require active chip-select over multiple
-	 * transactions, we achieve this using a GPIO. Still, the SPI
-	 * controller has to be configured to use one of its own chipselects.
-	 * To use this feature you have to call spi_setup_slave() with
-	 * cs = internal_cs | (gpio << 8), and you have to use some unused
-	 * on this SPI controller cs between 0 and 3.
-	 */
-	if (cs > 3) {
-		mxcs->gpio = cs >> 8;
-		cs &= 3;
-		ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
-		if (ret) {
-			printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
-			return -EINVAL;
-		}
-	} else {
-		mxcs->gpio = -1;
+	mxcs->gpio = board_spi_cs_gpio(bus, cs);
+	if (mxcs->gpio == -1)
+		return 0;
+
+	ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
+	if (ret) {
+		printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
+		return -EINVAL;
 	}
 
-	return cs;
+	return 0;
 }
 
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
@@ -415,14 +419,12 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 
 	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
 
-	ret = decode_cs(mxcs, cs);
+	ret = setup_cs_gpio(mxcs, bus, cs);
 	if (ret < 0) {
 		free(mxcs);
 		return NULL;
 	}
 
-	cs = ret;
-
 	mxcs->base = spi_bases[bus];
 
 	ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c
index 7a7a6767c7..6bca34dcf5 100644
--- a/drivers/usb/eth/smsc95xx.c
+++ b/drivers/usb/eth/smsc95xx.c
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
  * Copyright (C) 2009 NVIDIA, Corporation
+ * Copyright (C) 2007-2008 SMSC (Steve Glendinning)
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
diff --git a/drivers/usb/gadget/designware_udc.c b/drivers/usb/gadget/designware_udc.c
index b7c10384a3..3559400b28 100644
--- a/drivers/usb/gadget/designware_udc.c
+++ b/drivers/usb/gadget/designware_udc.c
@@ -269,7 +269,7 @@ static void dw_write_noniso_tx_fifo(struct usb_endpoint_instance
 		UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d",
 			urb->buffer, urb->buffer_length, urb->actual_length);
 
-		last = MIN(urb->actual_length - endpoint->sent,
+		last = min(urb->actual_length - endpoint->sent,
 			   endpoint->tx_packetSize);
 
 		if (last) {
@@ -285,7 +285,7 @@ static void dw_write_noniso_tx_fifo(struct usb_endpoint_instance
 
 			align = ((ulong)cp % sizeof(int));
 			if (align)
-				last = MIN(last, sizeof(int) - align);
+				last = min(last, sizeof(int) - align);
 
 			UDCDBGA("endpoint->sent %d, tx_packetSize %d, last %d",
 				endpoint->sent, endpoint->tx_packetSize, last);
diff --git a/drivers/usb/gadget/ep0.c b/drivers/usb/gadget/ep0.c
index b3214882f7..4ba2f3d99f 100644
--- a/drivers/usb/gadget/ep0.c
+++ b/drivers/usb/gadget/ep0.c
@@ -315,7 +315,7 @@ static int ep0_get_descriptor (struct usb_device_instance *device,
 			/*copy_config(urb, &report_descriptor->bData[0], report_descriptor->wLength, max); */
 			if (max - urb->actual_length > 0) {
 				int length =
-					MIN (report_descriptor->wLength,
+					min(report_descriptor->wLength,
 					     max - urb->actual_length);
 				memcpy (urb->buffer + urb->actual_length,
 					&report_descriptor->bData[0], length);
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 7a1acb9df0..38c09658cc 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -10,6 +10,7 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
+#include <config.h>
 #include <common.h>
 #include <errno.h>
 #include <malloc.h>
@@ -19,6 +20,9 @@
 #include <linux/compiler.h>
 #include <version.h>
 #include <g_dnl.h>
+#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
+#include <fb_mmc.h>
+#endif
 
 #define FASTBOOT_VERSION		"0.4"
 
@@ -38,7 +42,7 @@
 struct f_fastboot {
 	struct usb_function usb_function;
 
-	/* IN/OUT EP's and correspoinding requests */
+	/* IN/OUT EP's and corresponding requests */
 	struct usb_ep *in_ep, *out_ep;
 	struct usb_request *in_req, *out_req;
 };
@@ -290,7 +294,7 @@ static int fastboot_add(struct usb_configuration *c)
 }
 DECLARE_GADGET_BIND_CALLBACK(usb_dnl_fastboot, fastboot_add);
 
-int fastboot_tx_write(const char *buffer, unsigned int buffer_size)
+static int fastboot_tx_write(const char *buffer, unsigned int buffer_size)
 {
 	struct usb_request *in_req = fastboot_func->in_req;
 	int ret;
@@ -338,6 +342,7 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req)
 
 	strsep(&cmd, ":");
 	if (!cmd) {
+		error("missing variable\n");
 		fastboot_tx_write_str("FAILmissing var");
 		return;
 	}
@@ -358,6 +363,7 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req)
 		else
 			strcpy(response, "FAILValue not set");
 	} else {
+		error("unknown variable: %s\n", cmd);
 		strcpy(response, "FAILVariable not implemented");
 	}
 	fastboot_tx_write_str(response);
@@ -469,6 +475,28 @@ static void cb_boot(struct usb_ep *ep, struct usb_request *req)
 	fastboot_tx_write_str("OKAY");
 }
 
+#ifdef CONFIG_FASTBOOT_FLASH
+static void cb_flash(struct usb_ep *ep, struct usb_request *req)
+{
+	char *cmd = req->buf;
+	char response[RESPONSE_LEN];
+
+	strsep(&cmd, ":");
+	if (!cmd) {
+		error("missing partition name\n");
+		fastboot_tx_write_str("FAILmissing partition name");
+		return;
+	}
+
+	strcpy(response, "FAILno flash device defined");
+#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
+	fb_mmc_flash_write(cmd, (void *)CONFIG_USB_FASTBOOT_BUF_ADDR,
+			   download_bytes, response);
+#endif
+	fastboot_tx_write_str(response);
+}
+#endif
+
 struct cmd_dispatch_info {
 	char *cmd;
 	void (*cb)(struct usb_ep *ep, struct usb_request *req);
@@ -488,6 +516,12 @@ static const struct cmd_dispatch_info cmd_dispatch_info[] = {
 		.cmd = "boot",
 		.cb = cb_boot,
 	},
+#ifdef CONFIG_FASTBOOT_FLASH
+	{
+		.cmd = "flash",
+		.cb = cb_flash,
+	},
+#endif
 };
 
 static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
@@ -503,10 +537,12 @@ static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
 		}
 	}
 
-	if (!func_cb)
+	if (!func_cb) {
+		error("unknown command: %s\n", cmdbuf);
 		fastboot_tx_write_str("FAILunknown command");
-	else
+	} else {
 		func_cb(ep, req);
+	}
 
 	if (req->status == 0) {
 		*cmdbuf = '\0';
diff --git a/drivers/usb/gadget/mpc8xx_udc.c b/drivers/usb/gadget/mpc8xx_udc.c
index 7f72972dcc..b3e178abef 100644
--- a/drivers/usb/gadget/mpc8xx_udc.c
+++ b/drivers/usb/gadget/mpc8xx_udc.c
@@ -897,7 +897,7 @@ static int mpc8xx_udc_ep_tx (struct usb_endpoint_instance *epi)
 		pkt_len = urb->actual_length - epi->sent;
 
 		if (pkt_len > epi->tx_packetSize || pkt_len > EP_MAX_PKT) {
-			pkt_len = MIN (epi->tx_packetSize, EP_MAX_PKT);
+			pkt_len = min(epi->tx_packetSize, EP_MAX_PKT);
 		}
 
 		for (x = 0; x < pkt_len; x++) {
@@ -942,7 +942,7 @@ static int mpc8xx_udc_ep_tx (struct usb_endpoint_instance *epi)
 
 		/* TX ACK : USB 2.0 8.7.2, Toggle PID, Advance TX */
 		epi->sent += pkt_len;
-		epi->last = MIN (urb->actual_length - epi->sent, epi->tx_packetSize);
+		epi->last = min(urb->actual_length - epi->sent, epi->tx_packetSize);
 		TOGGLE_TX_PID (ep_ref[ep].pid);
 
 		if (epi->sent >= epi->tx_urb->actual_length) {
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index 733558def7..efd5c7fda1 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -65,7 +65,7 @@ static int udc_write_urb(struct usb_endpoint_instance *endpoint)
 	if (!urb || !urb->actual_length)
 		return -1;
 
-	n = MIN(urb->actual_length - endpoint->sent, endpoint->tx_packetSize);
+	n = min(urb->actual_length - endpoint->sent, endpoint->tx_packetSize);
 	if (n <= 0)
 		return -1;
 
diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c
index 9ffe5010be..9a8f004ece 100644
--- a/drivers/usb/host/ehci-atmel.c
+++ b/drivers/usb/host/ehci-atmel.c
@@ -40,7 +40,11 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 	}
 
 	/* Enable USB Host clock */
+#ifdef CPU_HAS_PCR
+	at91_periph_clk_enable(ATMEL_ID_UHPHS);
+#else
 	writel(1 << ATMEL_ID_UHPHS, &pmc->pcer);
+#endif
 
 	*hccr = (struct ehci_hccr *)ATMEL_BASE_EHCI;
 	*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
@@ -55,7 +59,11 @@ int ehci_hcd_stop(int index)
 	ulong start_time, tmp_time;
 
 	/* Disable USB Host Clock */
+#ifdef CPU_HAS_PCR
+	at91_periph_clk_disable(ATMEL_ID_UHPHS);
+#else
 	writel(1 << ATMEL_ID_UHPHS, &pmc->pcdr);
+#endif
 
 	start_time = get_timer(0);
 	/* Disable UTMI PLL */
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index c24505e78e..820e2e56ef 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -38,8 +38,8 @@ int usb_cpu_init(void)
 #endif
 
 	/* Enable USB host clock. */
-#ifdef CONFIG_SAMA5D3
-	writel(1 << (ATMEL_ID_UHP - 32), &pmc->pcer1);
+#ifdef CPU_HAS_PCR
+	at91_periph_clk_enable(ATMEL_ID_UHP);
 #else
 	writel(1 << ATMEL_ID_UHP, &pmc->pcer);
 #endif
@@ -58,8 +58,8 @@ int usb_cpu_stop(void)
 	at91_pmc_t *pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
 
 	/* Disable USB host clock. */
-#ifdef CONFIG_SAMA5D3
-	writel(1 << (ATMEL_ID_UHP - 32), &pmc->pcdr1);
+#ifdef CPU_HAS_PCR
+	at91_periph_clk_disable(ATMEL_ID_UHP);
 #else
 	writel(1 << ATMEL_ID_UHP, &pmc->pcdr);
 #endif
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/dts/Kconfig b/dts/Kconfig
new file mode 100644
index 0000000000..83ba7a6e98
--- /dev/null
+++ b/dts/Kconfig
@@ -0,0 +1,55 @@
+#
+# Device Tree Control
+#
+# TODO:
+#   This feature is not currently supported for SPL,
+#    but this restriction should be removed in the future.
+
+config SUPPORT_OF_CONTROL
+	bool
+
+menu "Device Tree Control"
+	depends on !SPL_BUILD
+	depends on SUPPORT_OF_CONTROL
+
+config OF_CONTROL
+	bool "Run-time configuration via Device Tree"
+	help
+	  This feature provides for run-time configuration of U-Boot
+	  via a flattened device tree.
+
+choice
+	prompt "Provider of DTB for DT control"
+	depends on OF_CONTROL
+
+config OF_SEPARATE
+	bool "Separate DTB for DT control"
+	depends on !SANDBOX
+	help
+	  If this option is enabled, the device tree will be built and
+	  placed as a separate u-boot.dtb file alongside the U-Boot image.
+
+config OF_EMBED
+	bool "Embedded DTB for DT control"
+	help
+	  If this option is enabled, the device tree will be picked up and
+	  built into the U-Boot image.
+
+config OF_HOSTFILE
+	bool "Host filed DTB for DT control"
+	depends on SANDBOX
+	help
+	  If this option is enabled, DTB will be read from a file on startup.
+	  This is only useful for Sandbox.  Use the -d flag to U-Boot to
+	  specify the file to read.
+
+endchoice
+
+config DEFAULT_DEVICE_TREE
+	string "Default Device Tree for DT control"
+	help
+	  This option specifies the default Device Tree used for DT control.
+	  It can be overrided from the command line:
+	  $ make DEVICE_TREE=<device-tree-name>
+
+endmenu
diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile
index 2dacba2eba..0863a8cda2 100644
--- a/examples/standalone/Makefile
+++ b/examples/standalone/Makefile
@@ -22,7 +22,7 @@ extra-$(CONFIG_PPC)                += sched
 ELF := $(strip $(extra-y))
 
 extra-y += $(addsuffix .srec,$(extra-y)) $(addsuffix .bin,$(extra-y))
-clean-files  := $(extra-) $(addsuffix .srec,$(extra-)) $(addsuffix .bin,$(extra-))
+clean-files  := *.srec *.bin
 
 COBJS	:= $(ELF:=.o)
 
diff --git a/fs/Kconfig b/fs/Kconfig
new file mode 100644
index 0000000000..41bb0b9f3a
--- /dev/null
+++ b/fs/Kconfig
@@ -0,0 +1,19 @@
+#
+# File system configuration
+#
+
+menu "File systems"
+
+source "fs/ext4/Kconfig"
+
+source "fs/reiserfs/Kconfig"
+
+source "fs/fat/Kconfig"
+
+source "fs/jffs2/Kconfig"
+
+source "fs/ubifs/Kconfig"
+
+source "fs/cramfs/Kconfig"
+
+endmenu
diff --git a/fs/cramfs/Kconfig b/fs/cramfs/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/fs/ext4/Kconfig b/fs/ext4/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/fs/fat/Kconfig b/fs/fat/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/fs/jffs2/Kconfig b/fs/jffs2/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/fs/reiserfs/Kconfig b/fs/reiserfs/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/fs/ubifs/Kconfig b/fs/ubifs/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/fs/zfs/zfs.c b/fs/zfs/zfs.c
index 099d51718b..818d3d926d 100644
--- a/fs/zfs/zfs.c
+++ b/fs/zfs/zfs.c
@@ -772,7 +772,7 @@ zap_leaf_array_equal(zap_leaf_phys_t *l, zfs_endian_t endian,
 
 	while (bseen < array_len) {
 		struct zap_leaf_array *la = &ZAP_LEAF_CHUNK(l, blksft, chunk).l_array;
-		int toread = MIN(array_len - bseen, ZAP_LEAF_ARRAY_BYTES);
+		int toread = min(array_len - bseen, ZAP_LEAF_ARRAY_BYTES);
 
 		if (chunk >= ZAP_LEAF_NUMCHUNKS(blksft))
 			return 0;
@@ -794,7 +794,7 @@ zap_leaf_array_get(zap_leaf_phys_t *l, zfs_endian_t endian, int blksft,
 
 	while (bseen < array_len) {
 		struct zap_leaf_array *la = &ZAP_LEAF_CHUNK(l, blksft, chunk).l_array;
-		int toread = MIN(array_len - bseen, ZAP_LEAF_ARRAY_BYTES);
+		int toread = min(array_len - bseen, ZAP_LEAF_ARRAY_BYTES);
 
 		if (chunk >= ZAP_LEAF_NUMCHUNKS(blksft))
 			/* Don't use errno because this error is to be ignored.  */
@@ -2118,7 +2118,7 @@ zfs_read(zfs_file_t file, char *buf, uint64_t len)
 		data->file_start = blkid * blksz;
 		data->file_end = data->file_start + blksz;
 
-		movesize = MIN(length, data->file_end - (int) file->offset - red);
+		movesize = min(length, data->file_end - (int)file->offset - red);
 
 		memmove(buf, data->file_buf + file->offset + red
 				- data->file_start, movesize);
diff --git a/include/common.h b/include/common.h
index 97c04df588..d5020c8c45 100644
--- a/include/common.h
+++ b/include/common.h
@@ -181,9 +181,6 @@ typedef void (interrupt_handler_t)(void *);
 		typeof(Y) __y = (Y);		\
 		(__x > __y) ? __x : __y; })
 
-#define MIN(x, y)  min(x, y)
-#define MAX(x, y)  max(x, y)
-
 #define min3(X, Y, Z)				\
 	({ typeof(X) __x = (X);			\
 		typeof(Y) __y = (Y);		\
@@ -198,9 +195,6 @@ typedef void (interrupt_handler_t)(void *);
 		__x > __y ? (__x > __z ? __x : __z) :	\
 		(__y > __z ? __y : __z); })
 
-#define MIN3(x, y, z)  min3(x, y, z)
-#define MAX3(x, y, z)  max3(x, y, z)
-
 /*
  * Return the absolute value of a number.
  *
diff --git a/include/compiler.h b/include/compiler.h
index 9afc11be19..14519163a3 100644
--- a/include/compiler.h
+++ b/include/compiler.h
@@ -129,9 +129,6 @@ typedef unsigned long int uintptr_t;
 
 #endif /* USE_HOSTCC */
 
-/* compiler options */
-#define uninitialized_var(x)		x = x
-
 #define likely(x)	__builtin_expect(!!(x), 1)
 #define unlikely(x)	__builtin_expect(!!(x), 0)
 
diff --git a/include/config_cmd_defaults.h b/include/config_cmd_defaults.h
deleted file mode 100644
index a55b268b9b..0000000000
--- a/include/config_cmd_defaults.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * config_cmd_defaults.h - sane defaults for everyone
- *
- * Copyright (c) 2010-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CONFIG_CMD_DEFAULTS_H_
-#define _CONFIG_CMD_DEFAULTS_H_
-
-#define CONFIG_CMD_BOOTM 1
-#define CONFIG_CMD_CRC32 1
-#define CONFIG_CMD_EXPORTENV 1
-#define CONFIG_CMD_GO 1
-#define CONFIG_CMD_IMPORTENV 1
-
-#endif
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 90d990157f..be616e8bfd 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -53,10 +53,23 @@
 #endif
 
 #ifdef CONFIG_CMD_SCSI
-#define BOOTENV_SHARED_SCSI	BOOTENV_SHARED_BLKDEV(scsi)
+#define BOOTENV_RUN_SCSI_INIT "run scsi_init; "
+#define BOOTENV_SET_SCSI_NEED_INIT "setenv scsi_need_init; "
+#define BOOTENV_SHARED_SCSI \
+	"scsi_init=" \
+		"if ${scsi_need_init}; then " \
+			"setenv scsi_need_init false; " \
+			"scsi scan; " \
+		"fi\0" \
+	\
+	"scsi_boot=" \
+		BOOTENV_RUN_SCSI_INIT \
+		BOOTENV_SHARED_BLKDEV_BODY(scsi)
 #define BOOTENV_DEV_SCSI	BOOTENV_DEV_BLKDEV
 #define BOOTENV_DEV_NAME_SCSI	BOOTENV_DEV_NAME_BLKDEV
 #else
+#define BOOTENV_RUN_SCSI_INIT
+#define BOOTENV_SET_SCSI_NEED_INIT
 #define BOOTENV_SHARED_SCSI
 #define BOOTENV_DEV_SCSI \
 	BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_CMD_SCSI
@@ -189,7 +202,7 @@
 	\
 	BOOT_TARGET_DEVICES(BOOTENV_DEV)                                  \
 	\
-	"bootcmd=" BOOTENV_SET_USB_NEED_INIT                              \
+	"bootcmd=" BOOTENV_SET_USB_NEED_INIT BOOTENV_SET_SCSI_NEED_INIT   \
 		"for target in ${boot_targets}; do "                      \
 			"run bootcmd_${target}; "                         \
 		"done\0"
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 953d06b53c..9063c57b40 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -227,6 +227,7 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 /* EEPROM */
+#define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM	0
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
@@ -819,9 +820,16 @@ unsigned long get_board_ddr_clk(void);
 
 #define __USB_PHY_TYPE	ulpi
 
+#ifdef CONFIG_PPC_B4860
+#define HWCONFIG	"hwconfig=fsl_ddr:ctlr_intlv=null,"	\
+			"bank_intlv=cs0_cs1;"	\
+			"en_cpc:cpc2;"
+#else
+#define	HWCONFIG	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
+#endif
+
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
-	"hwconfig=fsl_ddr:ctlr_intlv=null,"		\
-	"bank_intlv=cs0_cs1;"					\
+	HWCONFIG						\
 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 	"netdev=eth0\0"						\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 0ee0ff242d..5e2c100d93 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -19,6 +19,9 @@
 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
 #endif
 #ifdef CONFIG_T1042RDB_PI
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg
+#endif
+#ifdef CONFIG_T1042RDB
 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
 #endif
 
@@ -477,7 +480,7 @@
 
 /* I2C bus multiplexer */
 #define I2C_MUX_PCA_ADDR                0x70
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
 #define I2C_MUX_CH_DEFAULT      0x8
 #endif
 
@@ -503,6 +506,7 @@
 #define CONFIG_FSL_ESPI
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
 #define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
@@ -633,7 +637,7 @@
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_DPAA_PME
 
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
 #define CONFIG_QE
 #define CONFIG_U_QE
 #endif
@@ -662,7 +666,7 @@
 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
 #endif
 
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
 #if defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_QE_FW_ADDR		0x130000
 #elif defined(CONFIG_SDCARD)
@@ -686,7 +690,7 @@
 #endif
 
 #ifdef CONFIG_FMAN_ENET
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
 #define CONFIG_SYS_SGMII1_PHY_ADDR		0x03
 #endif
 #define CONFIG_SYS_RGMII1_PHY_ADDR		0x01
@@ -788,13 +792,14 @@
 #define CONFIG_BAUDRATE	115200
 
 #define __USB_PHY_TYPE	utmi
+#define RAMDISKFILE	"t104xrdb/ramdisk.uboot"
 
 #ifdef CONFIG_T1040RDB
 #define FDTFILE		"t1040rdb/t1040rdb.dtb"
-#define RAMDISKFILE	"t1040rdb/ramdisk.uboot"
-#elif CONFIG_T1042RDB_PI
-#define FDTFILE		"t1040rdb_pi/t1040rdb_pi.dtb"
-#define RAMDISKFILE	"t1040rdb_pi/ramdisk.uboot"
+#elif defined(CONFIG_T1042RDB_PI)
+#define FDTFILE		"t1042rdb_pi/t1042rdb_pi.dtb"
+#elif defined(CONFIG_T1042RDB)
+#define FDTFILE		"t1042rdb/t1042rdb.dtb"
 #endif
 
 #ifdef CONFIG_FSL_DIU_FB
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index df1a6fc528..e2f7ead9bc 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -23,9 +23,6 @@
 # define CONFIG_TIMESTAMP
 # define CONFIG_LZO
 # ifdef CONFIG_ENABLE_VBOOT
-#  define CONFIG_OF_CONTROL
-#  define CONFIG_OF_SEPARATE
-#  define CONFIG_DEFAULT_DEVICE_TREE am335x-boneblack
 #  define CONFIG_FIT_SIGNATURE
 #  define CONFIG_RSA
 # endif
@@ -115,6 +112,9 @@
 		"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
 		"ip=dhcp\0" \
 	"bootenv=uEnv.txt\0" \
+	"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+		"source ${loadaddr}\0" \
 	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
 	"importbootenv=echo Importing environment from mmc ...; " \
 		"env import -t -r $loadaddr $filesize\0" \
@@ -142,17 +142,21 @@
 	"mmcboot=mmc dev ${mmcdev}; " \
 		"if mmc rescan; then " \
 			"echo SD/MMC found on device ${mmcdev};" \
-			"if run loadbootenv; then " \
-				"echo Loaded environment from ${bootenv};" \
-				"run importbootenv;" \
-			"fi;" \
-			"if test -n $uenvcmd; then " \
-				"echo Running uenvcmd ...;" \
-				"run uenvcmd;" \
-			"fi;" \
-			"if run loadimage; then " \
-				"run mmcloados;" \
-			"fi;" \
+			"if run loadbootscript; then " \
+				"run bootscript;" \
+			"else " \
+				"if run loadbootenv; then " \
+					"echo Loaded environment from ${bootenv};" \
+					"run importbootenv;" \
+				"fi;" \
+				"if test -n $uenvcmd; then " \
+					"echo Running uenvcmd ...;" \
+					"run uenvcmd;" \
+				"fi;" \
+				"if run loadimage; then " \
+					"run mmcloados;" \
+				"fi;" \
+			"fi ;" \
 		"fi;\0" \
 	"spiboot=echo Booting from spi ...; " \
 		"run spiargs; " \
@@ -398,8 +402,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS		0
-#define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
 
 #define CONFIG_ENV_IS_IN_SPI_FLASH
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index 75f9933778..43077cf851 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -22,8 +22,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
 
 /* Allow tracing to be enabled */
 #define CONFIG_TRACE
@@ -226,7 +224,6 @@
 #define CONFIG_POWER_I2C
 #define CONFIG_POWER_MAX77686
 
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos5250-arndale
 
 #define CONFIG_PREBOOT
 
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index 9b0e588c6b..f02fce95b3 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -31,6 +31,7 @@
 #define CONFIG_DISPLAY_CPUINFO
 
 #define CONFIG_OF_LIBFDT
+#define CONFIG_SYS_GENERIC_BOARD
 
 /* general purpose I/O */
 #define CONFIG_AT91_GPIO
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 3747098d2a..b8d5dd156f 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -34,6 +34,8 @@
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_OF_LIBFDT
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 #define CONFIG_ATMEL_LEGACY
 #define CONFIG_AT91_GPIO		1
 #define CONFIG_AT91_GPIO_PULLUP		1
diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h
index c1eda96385..d0828d5f5c 100644
--- a/include/configs/bct-brettl2.h
+++ b/include/configs/bct-brettl2.h
@@ -137,7 +137,6 @@
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
 #define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/beaver.h b/include/configs/beaver.h
index d8ed717f5a..164b2dd951 100644
--- a/include/configs/beaver.h
+++ b/include/configs/beaver.h
@@ -24,11 +24,6 @@
 /* VDD core PMIC */
 #define CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
 
-/* Enable fdt support for Beaver. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra30-beaver
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT		"Tegra30 (Beaver) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Beaver"
diff --git a/include/configs/bf506f-ezkit.h b/include/configs/bf506f-ezkit.h
index 5db181984f..0b66cdbc01 100644
--- a/include/configs/bf506f-ezkit.h
+++ b/include/configs/bf506f-ezkit.h
@@ -85,8 +85,6 @@
  */
 #define CONFIG_ENV_IS_NOWHERE
 #define CONFIG_ENV_SIZE 0x400
-#undef CONFIG_CMD_EXPORTENV
-#undef CONFIG_CMD_IMPORTENV
 
 
 /*
@@ -102,7 +100,6 @@
 #define CONFIG_CMD_MEMORY
 #undef CONFIG_GZIP
 #undef CONFIG_ZLIB
-#undef CONFIG_CMD_BOOTM
 #undef CONFIG_BOOTM_RTEMS
 #undef CONFIG_BOOTM_LINUX
 
diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h
index 9e374c4024..20f6ed1992 100644
--- a/include/configs/bf518f-ezbrd.h
+++ b/include/configs/bf518f-ezbrd.h
@@ -155,7 +155,6 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
index 972eca9c17..c33d035022 100644
--- a/include/configs/bf526-ezbrd.h
+++ b/include/configs/bf526-ezbrd.h
@@ -153,7 +153,6 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	1
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /* define to enable run status via led */
 /* #define CONFIG_STATUS_LED */
diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h
index c0dfe2685b..b497f26773 100644
--- a/include/configs/bf527-ad7160-eval.h
+++ b/include/configs/bf527-ad7160-eval.h
@@ -136,7 +136,6 @@
  */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index 92c183e27c..0bca53f2a6 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -179,7 +179,6 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	1
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h
index 458868af72..9d43b811e3 100644
--- a/include/configs/bf527-sdp.h
+++ b/include/configs/bf527-sdp.h
@@ -112,7 +112,6 @@
  */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index b50352823e..0fda967ac2 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -110,7 +110,6 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 3d36d84c7c..ae4d83a8f1 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -186,7 +186,6 @@
  */
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /* FLASH/ETHERNET uses the same async bank */
 #define SHARED_RESOURCES 	1
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index a302f839a1..29f9316067 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -254,7 +254,6 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /* Define if want to do post memory test */
 #undef CONFIG_POST
diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h
index 32df5ec8f0..a65528246d 100644
--- a/include/configs/bf538f-ezkit.h
+++ b/include/configs/bf538f-ezkit.h
@@ -135,7 +135,6 @@
  */
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index 1a245a2b81..da5f029435 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -181,7 +181,6 @@
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	1
 #define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 #define CONFIG_ADI_GPIO2
 
diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h
index 3db917e37b..6871d8c422 100644
--- a/include/configs/bf561-acvilon.h
+++ b/include/configs/bf561-acvilon.h
@@ -160,7 +160,6 @@
 #define CONFIG_UART_CONSOLE			0
 #define CONFIG_BAUDRATE				57600
 #define CONFIG_SYS_PROMPT "Acvilon> "
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 0a309d9269..fb6f94873a 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -102,7 +102,6 @@
  * Misc Settings
  */
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Run core 1 from L1 SRAM start address when init uboot on core 0
diff --git a/include/configs/br4.h b/include/configs/br4.h
index f8d3158d47..3f240085e3 100644
--- a/include/configs/br4.h
+++ b/include/configs/br4.h
@@ -135,7 +135,6 @@
 #define CONFIG_BOOTCOMMAND	"run nandboot"
 #define CONFIG_BOOTDELAY	2
 #define CONFIG_LOADADDR		0x2000000
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
index 3f889f8d4f..e9d5d01620 100644
--- a/include/configs/bur_am335x_common.h
+++ b/include/configs/bur_am335x_common.h
@@ -151,7 +151,6 @@
 #undef CONFIG_CMD_NFS
 #undef CONFIG_CMD_SETGETDCR
 #undef CONFIG_CMD_XIMG
-#undef CONFIG_CMD_CRC32
 /* define command we need always */
 #define CONFIG_CMD_ECHO
 #define CONFIG_CMD_SOURCE
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
index 59f429cf57..09129c7767 100644
--- a/include/configs/cardhu.h
+++ b/include/configs/cardhu.h
@@ -24,11 +24,6 @@
 /* VDD core PMIC */
 #define CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
 
-/* Enable fdt support for Cardhu. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra30-cardhu
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT		"Tegra30 (Cardhu) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Cardhu"
diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h
index 8d3ae49913..f5351ad264 100644
--- a/include/configs/cm-bf527.h
+++ b/include/configs/cm-bf527.h
@@ -128,7 +128,6 @@
 #define FLASHBOOT_ENV_SETTINGS \
 	"flashboot=flread 20040000 1000000 300000;" \
 	"bootm 0x1000000\0"
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h
index 8bd499a7d2..485f01a01c 100644
--- a/include/configs/cm-bf533.h
+++ b/include/configs/cm-bf533.h
@@ -97,7 +97,6 @@
 #define CONFIG_UART_CONSOLE	0
 #define CONFIG_BOOTCOMMAND	"run flashboot"
 #define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
index 47967d7120..1729b44a1b 100644
--- a/include/configs/cm-bf537e.h
+++ b/include/configs/cm-bf537e.h
@@ -146,7 +146,6 @@
 	"flashboot=flread 20040000 1000000 3c0000;" \
 	"bootm 0x1000000\0"
 #define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
index 88c99821b1..272aa744a9 100644
--- a/include/configs/cm-bf537u.h
+++ b/include/configs/cm-bf537u.h
@@ -143,7 +143,6 @@
 	"flashboot=flread 20040000 1000000 300000;" \
 	"bootm 0x1000000\0"
 #define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h
index 346e27f3eb..7f27eda416 100644
--- a/include/configs/cm-bf548.h
+++ b/include/configs/cm-bf548.h
@@ -117,7 +117,6 @@
 #define CONFIG_UART_CONSOLE	1
 #define CONFIG_BOOTCOMMAND	"run flashboot"
 #define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 #define CONFIG_ADI_GPIO2
 
diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h
index 5265e5f6ef..96910a7afd 100644
--- a/include/configs/cm-bf561.h
+++ b/include/configs/cm-bf561.h
@@ -99,7 +99,6 @@
 #define CONFIG_UART_CONSOLE	0
 #define CONFIG_BOOTCOMMAND	"run flashboot"
 #define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
new file mode 100644
index 0000000000..10d02b4e18
--- /dev/null
+++ b/include/configs/cm_fx6.h
@@ -0,0 +1,290 @@
+/*
+ * Config file for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_CM_FX6_H
+#define __CONFIG_CM_FX6_H
+
+#include <asm/arch/imx-regs.h>
+#include <config_distro_defaults.h>
+#include "mx6_common.h"
+
+/* Machine config */
+#define CONFIG_MX6
+#define CONFIG_SYS_LITTLE_ENDIAN
+#define CONFIG_MACH_TYPE		4273
+#define CONFIG_SYS_HZ			1000
+
+/* Display information on boot */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_TIMESTAMP
+
+/* CMD */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_GREPENV
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+
+/* RAM */
+#define PHYS_SDRAM_1			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_2			MMDC1_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x10010000
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Serial console */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART4_BASE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/* Shell */
+#define CONFIG_SYS_PROMPT	"CM-FX6 # "
+#define CONFIG_SYS_CBSIZE	1024
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* SPI flash */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		25000000
+#define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_0)
+
+/* Environment */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_OFFSET		(768 * 1024)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel=uImage-cm-fx6\0" \
+	"autoload=no\0" \
+	"loadaddr=0x10800000\0" \
+	"fdtaddr=0x11000000\0" \
+	"console=ttymxc3,115200\0" \
+	"ethprime=FEC0\0" \
+	"bootscr=boot.scr\0" \
+	"bootm_low=18000000\0" \
+	"video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \
+	"video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
+	"fdtfile=cm-fx6.dtb\0" \
+	"doboot=bootm ${loadaddr}\0" \
+	"loadfdt=false\0" \
+	"setboottypez=setenv kernel zImage-cm-fx6;" \
+		"setenv doboot bootz ${loadaddr} - ${fdtaddr};" \
+		"setenv loadfdt true;\0" \
+	"setboottypem=setenv kernel uImage-cm-fx6;" \
+		"setenv doboot bootm ${loadaddr};" \
+		"setenv loadfdt false;\0"\
+	"run_eboot=echo Starting EBOOT ...; "\
+		"mmc dev ${mmcdev} && " \
+		"mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
+	"mmcdev=2\0" \
+	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
+	"loadmmcbootscript=load mmc ${mmcdev} ${loadaddr} ${bootscr}\0" \
+	"mmcbootscript=echo Running bootscript from mmc ...; "\
+		"source ${loadaddr}\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=${mmcroot} " \
+		"${video}\0" \
+	"mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
+	"mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"run doboot\0" \
+	"satadev=0\0" \
+	"sataroot=/dev/sda2 rw rootwait\0" \
+	"sataargs=setenv bootargs console=${console} " \
+		"root=${sataroot} " \
+		"${video}\0" \
+	"loadsatabootscript=load sata ${satadev} ${loadaddr} ${bootscr}\0" \
+	"satabootscript=echo Running bootscript from sata ...; " \
+		"source ${loadaddr}\0" \
+	"sataloadkernel=load sata ${satadev} ${loadaddr} ${kernel}\0" \
+	"sataloadfdt=load sata ${satadev} ${fdtaddr} ${fdtfile}\0" \
+	"sataboot=echo Booting from sata ...; "\
+		"run sataargs; " \
+		"run doboot\0" \
+	"nandroot=/dev/mtdblock4 rw\0" \
+	"nandrootfstype=ubifs\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype} " \
+		"${video}\0" \
+	"nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 0 780000; " \
+		"if ${loadfdt}; then " \
+			"run nandloadfdt;" \
+		"fi; " \
+		"run doboot\0" \
+	"boot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"if run loadmmcbootscript; then " \
+				"run mmcbootscript;" \
+			"else " \
+				"if run mmcloadkernel; then " \
+					"if ${loadfdt}; then " \
+						"run mmcloadfdt;" \
+					"fi;" \
+					"run mmcboot;" \
+				"fi;" \
+			"fi;" \
+		"fi;" \
+		"if sata init; then " \
+			"if run loadsatabootscript; then " \
+				"run satabootscript;" \
+			"else "\
+				"if run sataloadkernel; then " \
+					"if ${loadfdt}; then " \
+						"run sataloadfdt; " \
+					"fi;" \
+					"run sataboot;" \
+				"fi;" \
+			"fi;" \
+		"fi;" \
+		"run nandboot\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"run setboottypem; run boot"
+
+/* SPI */
+#define CONFIG_SPI
+#define CONFIG_MXC_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SPI_FLASH_EON
+#define CONFIG_SPI_FLASH_GIGADEVICE
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_WINBOND
+
+/* NAND */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* APBH DMA is required for NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+#endif
+
+/* Ethernet */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR		0
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+#define CONFIG_MII
+#define CONFIG_ETHPRIME			"FEC0"
+#define CONFIG_ARP_TIMEOUT		200UL
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_NET_RETRY_COUNT		5
+
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_MXC_I2C3_SPEED	400000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	2
+
+/* SATA */
+#define CONFIG_CMD_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+#define CONFIG_DWC_AHSATA
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+
+/* GPIO */
+#define CONFIG_MXC_GPIO
+
+/* Boot */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_LOADADDR			0x10800000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SYS_BOOTMAPSZ	        (8 << 20)
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+/* misc */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_STACKSIZE			(128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN			(2 * 1024 * 1024)
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	800 /* 400 KB */
+#define CONFIG_OF_BOARD_SETUP
+
+/* SPL */
+#include "imx6_spl.h"
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x80 /* offset 64 kb */
+#define CONFIG_SYS_MONITOR_LEN	(CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS / 2 * 1024)
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	(64 * 1024)
+#define CONFIG_SPL_SPI_LOAD
+
+#endif	/* __CONFIG_CM_FX6_H */
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index a3e6452ec1..767ef3a266 100644
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -107,6 +107,7 @@
 /* I2C Configuration */
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	0
 
 /* SPL */
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 70df1ebc67..6f4d97f2fd 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -135,6 +135,7 @@
 #define CONFIG_SYS_I2C_OMAP34XX
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	0
 #define CONFIG_I2C_MULTI_BUS
 
 /*
diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h
index df93a59c1b..641ab48c2c 100644
--- a/include/configs/cm_t54.h
+++ b/include/configs/cm_t54.h
@@ -30,6 +30,7 @@
 #define CONFIG_SYS_I2C_OMAP34XX
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	0
 
 /* Enable SD/MMC CD and WP GPIOs */
 #define OMAP_HSMMC_USE_GPIO
diff --git a/include/configs/colibri_t20_iris.h b/include/configs/colibri_t20_iris.h
index 6f9e08cac0..2b876fede1 100644
--- a/include/configs/colibri_t20_iris.h
+++ b/include/configs/colibri_t20_iris.h
@@ -9,11 +9,6 @@
 
 #include "tegra20-common.h"
 
-/* Enable FDT support */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-colibri_t20_iris
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT                   "Tegra20 (Colibri) # "
 #define CONFIG_TEGRA_BOARD_STRING  "Toradex Colibri T20 on Iris"
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
index eacff5b792..782b9d16b7 100644
--- a/include/configs/colibri_t30.h
+++ b/include/configs/colibri_t30.h
@@ -11,9 +11,6 @@
 
 #include "tegra30-common.h"
 
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra30-colibri
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
 
 #define V_PROMPT			"Colibri T30 # "
 #define CONFIG_TEGRA_BOARD_STRING	"Toradex Colibri T30"
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 7eaaf69951..bfcfa0c8c9 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -434,7 +434,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_LAST_STAGE_INIT
-#undef CONFIG_CMD_BOOTM
 
 #endif /* CONFIG_TRAILBLAZER */
 
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index a1a63a018d..936be14511 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -28,9 +28,6 @@
 
 #define CONFIG_LMB
 #define CONFIG_OF_LIBFDT
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-#define CONFIG_DEFAULT_DEVICE_TREE	link
 
 #define CONFIG_BOOTSTAGE
 #define CONFIG_BOOTSTAGE_REPORT
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 1252d7a54a..5f85755737 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -157,8 +157,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
 #define CONFIG_SYS_SPI_U_BOOT_SIZE	0x30000
 #endif
@@ -376,8 +374,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
index fd774a3314..ff7ec4a93b 100644
--- a/include/configs/dalmore.h
+++ b/include/configs/dalmore.h
@@ -21,11 +21,6 @@
 
 #include "tegra114-common.h"
 
-/* Enable fdt support for Dalmore. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra114-dalmore
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT		"Tegra114 (Dalmore) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Dalmore"
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 4143a4ddeb..2eaabdefee 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -116,8 +116,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_BUS             0
-#define CONFIG_SPL_SPI_CS              0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x40000
 
 #define CONFIG_SUPPORT_EMMC_BOOT
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index a7fd43bc7b..185edbe7fe 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -102,7 +102,7 @@
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS		0
-#define CONFIG_SF_DEFAULT_CS		(0 | (IMX_GPIO_NR(2, 30) << 8))
+#define CONFIG_SF_DEFAULT_CS		0
 #define CONFIG_SF_DEFAULT_SPEED		20000000
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #endif
diff --git a/include/configs/exynos4-dt.h b/include/configs/exynos4-dt.h
index 7dac1a3717..99472acd0c 100644
--- a/include/configs/exynos4-dt.h
+++ b/include/configs/exynos4-dt.h
@@ -22,10 +22,6 @@
 #define CONFIG_BOARD_COMMON
 #define CONFIG_SYS_GENERIC_BOARD
 
-/* Enable fdt support */
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 #define CONFIG_SYS_CACHELINE_SIZE	32
 
 /* input clock of PLL: EXYNOS4 boards have 24MHz input clock */
diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
index a7c6292863..1dc3002523 100644
--- a/include/configs/exynos5-dt.h
+++ b/include/configs/exynos5-dt.h
@@ -24,10 +24,6 @@
 #define CONFIG_ARCH_EARLY_INIT_R
 #define CONFIG_EXYNOS_SPL
 
-/* Enable fdt support for Exynos5250 */
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* Allow tracing to be enabled */
 #define CONFIG_TRACE
 #define CONFIG_CMD_TRACE
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index b991b093cb..620f9501d2 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -61,7 +61,7 @@
   #define CONFIG_SPI_FLASH_BAR
   #define CONFIG_SPI_FLASH_WINBOND
   #define CONFIG_SF_DEFAULT_BUS              0
-  #define CONFIG_SF_DEFAULT_CS               (0|(IMX_GPIO_NR(3, 19)<<8))
+  #define CONFIG_SF_DEFAULT_CS               0
 					     /* GPIO 3-19 (21248) */
   #define CONFIG_SF_DEFAULT_SPEED            30000000
   #define CONFIG_SF_DEFAULT_MODE             (SPI_MODE_0)
@@ -141,6 +141,7 @@
 #define CONFIG_PCI
 #define CONFIG_PCI_PNP
 #define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCI_FIXUP_DEV
 #define CONFIG_PCIE_IMX
 #endif
 
diff --git a/include/configs/h2200.h b/include/configs/h2200.h
index 9470ad6abc..109cee985b 100644
--- a/include/configs/h2200.h
+++ b/include/configs/h2200.h
@@ -116,7 +116,6 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 38400, 115200 }
 
-#define CONFIG_CMD_IMPORTENV		1
 #define CONFIG_CMD_LOADB
 #define CONFIG_CMD_SOURCE
 #define CONFIG_CMD_RUN
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index 3ec0e418c1..ff9fbc9965 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -11,11 +11,6 @@
 #include <linux/sizes.h>
 #include "tegra20-common.h"
 
-/* Enable fdt support for Harmony. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-harmony
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (Harmony) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Harmony"
diff --git a/include/configs/ip04.h b/include/configs/ip04.h
index 3767502faa..ec510bdac4 100644
--- a/include/configs/ip04.h
+++ b/include/configs/ip04.h
@@ -133,7 +133,6 @@
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_MISC_INIT_R	/* needed for MAC address */
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 #undef CONFIG_SHOW_BOOT_PROGRESS
 /* Enable this if bootretry required; currently it's disabled */
diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
index d03a66cd22..d67c025b9c 100644
--- a/include/configs/jetson-tk1.h
+++ b/include/configs/jetson-tk1.h
@@ -12,11 +12,6 @@
 
 #include "tegra124-common.h"
 
-/* Enable fdt support for Jetson TK1. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra124-jetson-tk1
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT			"Tegra124 (Jetson TK1) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Jetson TK1"
diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
index 43db581c75..51926f721f 100644
--- a/include/configs/ks2_evm.h
+++ b/include/configs/ks2_evm.h
@@ -58,8 +58,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS		0
-#define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
 #define CONFIG_SPL_FRAMEWORK
 
diff --git a/include/configs/kwb.h b/include/configs/kwb.h
index 0860434f22..29b263f301 100644
--- a/include/configs/kwb.h
+++ b/include/configs/kwb.h
@@ -89,7 +89,6 @@
 #undef	CONFIG_BOOTM_RTEMS
 #undef	CONFIG_GZIP
 #undef	CONFIG_ZLIB
-#undef CONFIG_CMD_CRC32
 
 /* USB configuration */
 #define CONFIG_USB_MUSB_DSPS
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 657e3b6d48..bb47813345 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -49,10 +49,12 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_DDR_SPD
 #define SPD_EEPROM_ADDRESS		0x51
 #define CONFIG_SYS_SPD_BUS_NUM		0
-#define CONFIG_SYS_DDR_RAW_TIMING
 
 #define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
+#ifndef CONFIG_SYS_FSL_DDR4
 #define CONFIG_SYS_FSL_DDR3		/* Use DDR3 memory */
+#define CONFIG_SYS_DDR_RAW_TIMING
+#endif
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	4
 
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 2bd5a472b3..a72e1f3567 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -15,9 +15,11 @@
 #define CONFIG_GICV3
 
 /* Link Definitions */
-#define CONFIG_SYS_TEXT_BASE		0x30000000
+#define CONFIG_SYS_TEXT_BASE		0x30001000
 
+#ifdef CONFIG_EMU
 #define CONFIG_SYS_NO_FLASH
+#endif
 
 #define CONFIG_SUPPORT_RAW_INITRD
 
@@ -45,13 +47,27 @@
 
 #define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */
 
-/* SMP Definitions */
-#define CPU_RELEASE_ADDR		CONFIG_SYS_INIT_SP_ADDR
-
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	2
+
+/*
+ * SMP Definitinos
+ */
+#define CPU_RELEASE_ADDR		secondary_boot_func
+
+#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
+#define CONFIG_SYS_DP_DDR_BASE		0x6000000000ULL
+/*
+ * DDR controller use 0 as the base address for binding.
+ * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+ */
+#define CONFIG_SYS_DP_DDR_BASE_PHY	0
+#define CONFIG_DP_DDR_CTRL		2
+#define CONFIG_DP_DDR_NUM_CTRLS		1
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
 
 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY		12000000	/* 12MHz */
@@ -118,6 +134,66 @@
 #define CONFIG_SYS_NOR_FTIM3	0x04000000
 #define CONFIG_SYS_IFC_CCR	0x01000000
 
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#endif
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_BASE		0x520000000
+#define CONFIG_SYS_NAND_BASE_PHYS	0x20000000
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
 #define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
@@ -167,6 +243,7 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+#define CONFIG_ARCH_EARLY_INIT_R
 
 /* Physical Memory Map */
 /* fixme: these need to be checked against the board */
@@ -174,7 +251,7 @@
 #define CONFIG_SYS_CLK_FREQ	133333333
 
 
-#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_NR_DRAM_BANKS		3
 
 #define CONFIG_SYS_HZ			1000
 
diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2085a_emu.h
index a5cea63b33..487cd99c5d 100644
--- a/include/configs/ls2085a_emu.h
+++ b/include/configs/ls2085a_emu.h
@@ -13,6 +13,7 @@
 #define CONFIG_SYS_FSL_DDR_EMU		/* Support emulator */
 #define SPD_EEPROM_ADDRESS1	0x51
 #define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS3	0x53
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
 #define CONFIG_SYS_SPD_BUS_NUM	1	/* SPD on I2C bus 1 */
 
diff --git a/include/configs/ls2085a_simu.h b/include/configs/ls2085a_simu.h
index 46d47b06e4..0f40b787b4 100644
--- a/include/configs/ls2085a_simu.h
+++ b/include/configs/ls2085a_simu.h
@@ -13,4 +13,13 @@
 #define CONFIG_SMC91111
 #define CONFIG_SMC91111_BASE	(0x2210000)
 
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+
 #endif /* __LS2_SIMU_H */
diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h
index 40155c3796..ac5208fa0d 100644
--- a/include/configs/medcom-wide.h
+++ b/include/configs/medcom-wide.h
@@ -12,11 +12,6 @@
 
 #include "tegra20-common.h"
 
-/* Enable fdt support for Medcom-Wide. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-medcom-wide
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT			"Tegra20 (Medcom-Wide) # "
 #define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Medcom-Wide"
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 1a82a57c75..bb07060002 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -14,11 +14,6 @@
 /* MicroBlaze CPU */
 #define	MICROBLAZE_V5		1
 
-/* Open Firmware DTS */
-#define CONFIG_OF_CONTROL	1
-#define CONFIG_OF_EMBED		1
-#define CONFIG_DEFAULT_DEVICE_TREE microblaze-generic
-
 /* linear and spi flash memory */
 #ifdef XILINX_FLASH_START
 #define	FLASH
diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h
index 0f2a4ef973..fce7ead977 100644
--- a/include/configs/mx51_efikamx.h
+++ b/include/configs/mx51_efikamx.h
@@ -96,11 +96,11 @@
 
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_SST
-#define CONFIG_SF_DEFAULT_CS		(1 | 121 << 8)
+#define CONFIG_SF_DEFAULT_CS		1
 #define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_0)
 #define CONFIG_SF_DEFAULT_SPEED		25000000
 
-#define CONFIG_ENV_SPI_CS		(1 | 121 << 8)
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
 #define CONFIG_ENV_SPI_BUS		0
 #define CONFIG_ENV_SPI_MAX_HZ		25000000
 #define CONFIG_ENV_SPI_MODE		(SPI_MODE_0)
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index fd651cfa50..35c0a85080 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -23,6 +23,8 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
 
diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h
index d1639c4c76..0ab31279cc 100644
--- a/include/configs/mx6qsabreauto.h
+++ b/include/configs/mx6qsabreauto.h
@@ -45,7 +45,4 @@
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_SPEED		100000
 
-#define CONFIG_OF_SEPARATE
-#define CONFIG_DEFAULT_DEVICE_TREE   imx6q-sabreauto
-
 #endif                         /* __MX6QSABREAUTO_CONFIG_H */
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index e59a3b4b05..2d93d6c700 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -74,7 +74,7 @@
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS		0
-#define CONFIG_SF_DEFAULT_CS		(0 | (IMX_GPIO_NR(4, 9) << 8))
+#define CONFIG_SF_DEFAULT_CS		0
 #define CONFIG_SF_DEFAULT_SPEED		20000000
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #endif
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 3d05a647d9..4208ba1563 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -26,6 +26,8 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
 
@@ -203,7 +205,7 @@
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS		0
-#define CONFIG_SF_DEFAULT_CS		(0 | (IMX_GPIO_NR(4, 11) << 8))
+#define CONFIG_SF_DEFAULT_CS		0
 #define CONFIG_SF_DEFAULT_SPEED		20000000
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #endif
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 1eda65e081..b92d9443d4 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -198,6 +198,16 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
+#define CONFIG_CMD_PCI
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(2, 1)
+#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(2, 0)
+#endif
+
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index b2b17ce969..39d5bb34bb 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -53,7 +53,7 @@
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS  0
-#define CONFIG_SF_DEFAULT_CS   (0|(IMX_GPIO_NR(3, 19)<<8))
+#define CONFIG_SF_DEFAULT_CS   0
 #define CONFIG_SF_DEFAULT_SPEED 25000000
 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
 #endif
@@ -192,11 +192,11 @@
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
 		"root=${mmcroot}\0" \
 	"loadbootscript=" \
-		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
-	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
-	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loaduimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index 29dcc4a298..b616ac2fbd 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -16,8 +16,6 @@
 
 #define CONFIG_SYS_PROMPT	"Odroid # "	/* Monitor Command Prompt */
 
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos4412-odroid
 
 #define CONFIG_SYS_L2CACHE_OFF
 #ifndef CONFIG_SYS_L2CACHE_OFF
diff --git a/include/configs/origen.h b/include/configs/origen.h
index 5d24916389..fb1536c62c 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -13,8 +13,6 @@
 
 #define CONFIG_SYS_PROMPT		"ORIGEN # "
 
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos4210-origen
 
 /* High Level Configuration Options */
 #define CONFIG_EXYNOS4210		1	/* which is a EXYNOS4210 SoC */
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index dd0abf8de6..45bb47088b 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -20,11 +20,6 @@
 #include <linux/sizes.h>
 #include "tegra20-common.h"
 
-/* Enable fdt support for Paz00. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-paz00
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (Paz00) MOD # "
 #define CONFIG_TEGRA_BOARD_STRING	"Compal Paz00"
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index 5efcd7613f..7d102a4699 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -128,8 +128,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS		0
-#define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
 #define CONFIG_SYS_SPI_U_BOOT_SIZE	0x40000
 #endif
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
index 88c093fb9b..987cef504c 100644
--- a/include/configs/peach-pit.h
+++ b/include/configs/peach-pit.h
@@ -13,8 +13,6 @@
 
 #include <configs/exynos5420.h>
 
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos5420-peach-pit
 
 /* select serial console configuration */
 #define CONFIG_SERIAL3		/* use SERIAL 3 */
diff --git a/include/configs/ph1_ld4.h b/include/configs/ph1_ld4.h
new file mode 100644
index 0000000000..a28d7b579a
--- /dev/null
+++ b/include/configs/ph1_ld4.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PH1_XXX_H
+#define __PH1_XXX_H
+
+/*
+ * Support Card Select
+ *
+ *  CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
+ *  CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
+ *                       CPLD is re-programmed for ARIMA board compatibility.
+ *  No define                     - No support card.
+ */
+
+#if 0
+#define CONFIG_PFC_MICRO_SUPPORT_CARD
+#else
+#define CONFIG_DCC_MICRO_SUPPORT_CARD
+#endif
+
+/*
+ * Serial Configuration
+ *   SoC UART     : enable CONFIG_UNIPHIER_SERIAL
+ *   On-board UART: enable CONFIG_SYS_NS16550_SERIAL
+ */
+#if 1
+#define CONFIG_UNIPHIER_SERIAL
+#else
+#define CONFIG_SYS_NS16550_SERIAL
+#endif
+
+#define CONFIG_SYS_UNIPHIER_UART_CLK    36864000
+
+#define CONFIG_SMC911X
+
+#define CONFIG_DDR_NUM_CH0 1
+#define CONFIG_DDR_NUM_CH1 1
+
+#define CONFIG_DDR_FREQ 1600
+
+/*
+ * Memory Size & Mapping
+ */
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE	0x80000000
+#define CONFIG_SDRAM0_SIZE	0x10000000
+#define CONFIG_SDRAM1_BASE	0x90000000
+#define CONFIG_SDRAM1_SIZE	0x10000000
+
+#define CONFIG_SPL_TEXT_BASE 0x40000
+
+#include "uniphier-common.h"
+
+#endif /* __PH1_XXX_H */
diff --git a/include/configs/ph1_pro4.h b/include/configs/ph1_pro4.h
new file mode 100644
index 0000000000..b79967f7da
--- /dev/null
+++ b/include/configs/ph1_pro4.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PH1_XXX_H
+#define __PH1_XXX_H
+
+/*
+ * Support Card Select
+ *
+ *  CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
+ *  CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
+ *                       CPLD is re-programmed for ARIMA board compatibility.
+ *  No define                     - No support card.
+ */
+
+#if 0
+#define CONFIG_PFC_MICRO_SUPPORT_CARD
+#else
+#define CONFIG_DCC_MICRO_SUPPORT_CARD
+#endif
+
+/*
+ * Serial Configuration
+ *   SoC UART     : enable CONFIG_UNIPHIER_SERIAL
+ *   On-board UART: enable CONFIG_SYS_NS16550_SERIAL
+ */
+#if 1
+#define CONFIG_UNIPHIER_SERIAL
+#else
+#define CONFIG_SYS_NS16550_SERIAL
+#endif
+
+#define CONFIG_SYS_UNIPHIER_UART_CLK    73728000
+
+#define CONFIG_SMC911X
+
+#define CONFIG_DDR_NUM_CH0 2
+#define CONFIG_DDR_NUM_CH1 2
+
+#define CONFIG_DDR_FREQ 1600
+
+#define CONFIG_UNIPHIER_SMP
+
+/*
+ * Memory Size & Mapping
+ */
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE	0x80000000
+#define CONFIG_SDRAM0_SIZE	0x20000000
+#define CONFIG_SDRAM1_BASE	0xa0000000
+#define CONFIG_SDRAM1_SIZE	0x20000000
+
+#define CONFIG_SPL_TEXT_BASE 0x100000
+
+#include "uniphier-common.h"
+
+#endif /* __PH1_XXX_H */
diff --git a/include/configs/ph1_sld8.h b/include/configs/ph1_sld8.h
new file mode 100644
index 0000000000..9d391f1d74
--- /dev/null
+++ b/include/configs/ph1_sld8.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PH1_XXX_H
+#define __PH1_XXX_H
+
+/*
+ * Support Card Select
+ *
+ *  CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
+ *  CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
+ *                       CPLD is re-programmed for ARIMA board compatibility.
+ *  No define                     - No support card.
+ */
+
+#if 0
+#define CONFIG_PFC_MICRO_SUPPORT_CARD
+#else
+#define CONFIG_DCC_MICRO_SUPPORT_CARD
+#endif
+
+/*
+ * Serial Configuration
+ *   SoC UART     : enable CONFIG_UNIPHIER_SERIAL
+ *   On-board UART: enable CONFIG_SYS_NS16550_SERIAL
+ */
+#if 1
+#define CONFIG_UNIPHIER_SERIAL
+#else
+#define CONFIG_SYS_NS16550_SERIAL
+#endif
+
+#define CONFIG_SYS_UNIPHIER_UART_CLK    80000000
+
+#define CONFIG_SMC911X
+
+#define CONFIG_DDR_NUM_CH0 1
+#define CONFIG_DDR_NUM_CH1 1
+
+#define CONFIG_DDR_FREQ 1333
+
+/* #define CONFIG_DDR_STANDARD */
+
+/*
+ * Memory Size & Mapping
+ */
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE	0x80000000
+#define CONFIG_SDRAM0_SIZE	0x10000000
+#define CONFIG_SDRAM1_BASE	0x90000000
+#define CONFIG_SDRAM1_SIZE	0x10000000
+
+#define CONFIG_SPL_TEXT_BASE 0x40000
+
+#include "uniphier-common.h"
+
+#endif /* __PH1_XXX_H */
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
index a473f232f3..b663b89d2c 100644
--- a/include/configs/plutux.h
+++ b/include/configs/plutux.h
@@ -12,11 +12,6 @@
 
 #include "tegra20-common.h"
 
-/* Enable fdt support for Plutux. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-plutux
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT			"Tegra20 (Plutux) # "
 #define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Plutux"
diff --git a/include/configs/pr1.h b/include/configs/pr1.h
index e96ed4b4f2..0f57e868a5 100644
--- a/include/configs/pr1.h
+++ b/include/configs/pr1.h
@@ -135,7 +135,6 @@
 #define CONFIG_BOOTCOMMAND	"run nandboot"
 #define CONFIG_BOOTDELAY	2
 #define CONFIG_LOADADDR		0x2000000
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index 20985da9a0..082d51c52b 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -14,8 +14,6 @@
 
 #define CONFIG_SYS_PROMPT	"Universal # "	/* Monitor Command Prompt */
 
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos4210-universal_c210
 
 #define CONFIG_TIZEN			/* TIZEN lib */
 
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index 56c2454dff..c46baf254f 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -79,8 +79,19 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-/* No NOR flash */
+/* NOR flash */
+#define CONFIG_CMD_FLASH
+
+#ifdef CONFIG_CMD_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_BASE		0x10000000
+#define CONFIG_SYS_MAX_FLASH_SECT	131
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#else
 #define CONFIG_SYS_NO_FLASH
+#endif
 
 /*
  * Command line configuration.
@@ -287,8 +298,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS		0
-#define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8400
 
 #endif
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index f5fa4b3ddc..69726432a3 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -38,15 +38,12 @@
 /* Number of bits in a C 'long' on this architecture */
 #define CONFIG_SANDBOX_BITS_PER_LONG	64
 
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_HOSTFILE
 #define CONFIG_OF_LIBFDT
 #define CONFIG_LMB
 #define CONFIG_FIT
 #define CONFIG_FIT_SIGNATURE
 #define CONFIG_RSA
 #define CONFIG_CMD_FDT
-#define CONFIG_DEFAULT_DEVICE_TREE	sandbox
 #define CONFIG_ANDROID_BOOT_IMAGE
 
 #define CONFIG_FS_FAT
@@ -94,7 +91,7 @@
 #define CONFIG_ENV_SIZE		8192
 #define CONFIG_ENV_IS_NOWHERE
 
-/* SPI */
+/* SPI - enable all SPI flash types for testing purposes */
 #define CONFIG_SANDBOX_SPI
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SF_TEST
@@ -102,7 +99,13 @@
 #define CONFIG_SPI_FLASH
 #define CONFIG_OF_SPI
 #define CONFIG_OF_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SPI_FLASH_EON
+#define CONFIG_SPI_FLASH_GIGADEVICE
+#define CONFIG_SPI_FLASH_MACRONIX
 #define CONFIG_SPI_FLASH_SANDBOX
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_SST
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_SPI_FLASH_WINBOND
 
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index fc4f976d8d..04e4f82759 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -19,11 +19,6 @@
 
 #include "tegra20-common.h"
 
-/* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-seaboard
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (SeaBoard) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Seaboard"
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index b8fb77e813..bf9752f874 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -167,8 +167,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS		0
-#define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
 
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index 66fa1799e7..61170941c1 100644
--- a/include/configs/smdk5250.h
+++ b/include/configs/smdk5250.h
@@ -11,8 +11,6 @@
 
 #include <configs/exynos5250-dt.h>
 
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos5250-smdk5250
 
 /* Enable FIT support and comparison */
 #define CONFIG_FIT
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
index 606739b02e..36a156f7a7 100644
--- a/include/configs/smdk5420.h
+++ b/include/configs/smdk5420.h
@@ -15,8 +15,6 @@
 
 #define CONFIG_SMDK5420			/* which is in a SMDK5420 */
 
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos5420-smdk5420
 
 /* select serial console configuration */
 #define CONFIG_SERIAL3		/* use SERIAL 3 */
diff --git a/include/configs/snow.h b/include/configs/snow.h
index 673fa1469b..fbaaa593cc 100644
--- a/include/configs/snow.h
+++ b/include/configs/snow.h
@@ -11,8 +11,6 @@
 
 #include <configs/exynos5250-dt.h>
 
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos5250-snow
 
 /* Enable FIT support and comparison */
 #define CONFIG_FIT
diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h
index a77ba697d0..66730267a3 100644
--- a/include/configs/tcm-bf518.h
+++ b/include/configs/tcm-bf518.h
@@ -116,7 +116,6 @@
 #define CONFIG_UART_CONSOLE	0
 #define CONFIG_BOOTCOMMAND	"run flashboot"
 #define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
index c4c1c579bc..999834351f 100644
--- a/include/configs/tcm-bf537.h
+++ b/include/configs/tcm-bf537.h
@@ -145,7 +145,6 @@
 	"flashboot=flread 20040000 1000000 300000;" \
 	"bootm 0x1000000\0"
 #define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h
index 13baa76f91..51f87dacdb 100644
--- a/include/configs/tec-ng.h
+++ b/include/configs/tec-ng.h
@@ -10,11 +10,6 @@
 
 #include "tegra30-common.h"
 
-/* Enable fdt support for tec-ng. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra30-tec-ng
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT			"Tegra30 (TEC-NG) # "
 #define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Tamonten™ NG Evaluation Carrier"
diff --git a/include/configs/tec.h b/include/configs/tec.h
index 90e7b7ad97..9ea4ff4971 100644
--- a/include/configs/tec.h
+++ b/include/configs/tec.h
@@ -12,11 +12,6 @@
 
 #include "tegra20-common.h"
 
-/* Enable fdt support for TEC. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-tec
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT			"Tegra20 (TEC) # "
 #define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Tamonten Evaluation Carrier"
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index c337e3016e..23e3c8af31 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -69,7 +69,6 @@
 
 /* remove devicetree support */
 #ifdef CONFIG_OF_CONTROL
-#undef CONFIG_OF_CONTROL
 #endif
 
 /* remove I2C support */
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index 8c7310c9a1..b0f199e3f4 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -101,10 +101,10 @@
 		"vram=${vram} " \
 		"root=${mmcroot} " \
 		"rootfstype=${mmcrootfstype}\0" \
-	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
 		"source ${loadaddr}\0" \
-	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+	"loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
 	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
 		"env import -t ${loadaddr} ${filesize}\0" \
 	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 6fa646bb8c..43751e7938 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -16,8 +16,6 @@
 
 #define CONFIG_TRATS
 
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos4210-trats
 
 #define CONFIG_TIZEN			/* TIZEN lib */
 
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 14508650e4..e9a04f7af3 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -15,8 +15,6 @@
 
 #define CONFIG_SYS_PROMPT	"Trats2 # "	/* Monitor Command Prompt */
 
-#undef CONFIG_DEFAULT_DEVICE_TREE
-#define CONFIG_DEFAULT_DEVICE_TREE	exynos4412-trats2
 
 #define CONFIG_TIZEN			/* TIZEN lib */
 
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index f81cfa2e35..7c0064267d 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -11,11 +11,6 @@
 #include <linux/sizes.h>
 #include "tegra20-common.h"
 
-/* Enable fdt support for TrimSlice. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-trimslice
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (TrimSlice) # "
 #define CONFIG_TEGRA_BOARD_STRING	"Compulab Trimslice"
diff --git a/include/configs/tseries.h b/include/configs/tseries.h
index 1dd13fd1b0..9a6207048c 100644
--- a/include/configs/tseries.h
+++ b/include/configs/tseries.h
@@ -222,8 +222,6 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS		0
-#define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
 #undef CONFIG_ENV_IS_NOWHERE
 #define CONFIG_ENV_IS_IN_SPI_FLASH
diff --git a/include/configs/uniphier-common.h b/include/configs/uniphier-common.h
new file mode 100644
index 0000000000..18fe277cad
--- /dev/null
+++ b/include/configs/uniphier-common.h
@@ -0,0 +1,266 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* U-boot - Common settings for UniPhier Family */
+
+#ifndef __CONFIG_UNIPHIER_COMMON_H__
+#define __CONFIG_UNIPHIER_COMMON_H__
+
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) &&	\
+				defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+# error "Both CONFIG_PFC_MICRO_SUPPORT_CARD and CONFIG_DCC_MICRO_SUPPORT_CARD \
+are defined. Select only one of them."
+#endif
+
+/*
+ * Support card address map
+ */
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
+# define CONFIG_SUPPORT_CARD_BASE	0x03f00000
+# define CONFIG_SUPPORT_CARD_ETHER_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00000000)
+# define CONFIG_SUPPORT_CARD_LED_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00090000)
+# define CONFIG_SUPPORT_CARD_UART_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
+#endif
+
+#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+# define CONFIG_SUPPORT_CARD_BASE	0x08000000
+# define CONFIG_SUPPORT_CARD_ETHER_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00000000)
+# define CONFIG_SUPPORT_CARD_LED_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00401630)
+# define CONFIG_SUPPORT_CARD_UART_BASE	(CONFIG_SUPPORT_CARD_BASE + 0x00200000)
+#endif
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_COM1		CONFIG_SUPPORT_CARD_UART_BASE
+#define CONFIG_SYS_NS16550_CLK		12288000
+#define CONFIG_SYS_NS16550_REG_SIZE	-2
+
+#define CONFIG_SMC911X_BASE		CONFIG_SUPPORT_CARD_ETHER_BASE
+#define CONFIG_SMC911X_32_BIT
+
+#define CONFIG_SYS_UNIPHIER_SERIAL_BASE0 0x54006800
+#define CONFIG_SYS_UNIPHIER_SERIAL_BASE1 0x54006900
+#define CONFIG_SYS_UNIPHIER_SERIAL_BASE2 0x54006a00
+#define CONFIG_SYS_UNIPHIER_SERIAL_BASE3 0x54006b00
+
+/*-----------------------------------------------------------------------
+ * MMU and Cache Setting
+ *----------------------------------------------------------------------*/
+
+/* Comment out the following to enable L1 cache */
+/* #define CONFIG_SYS_ICACHE_OFF */
+/* #define CONFIG_SYS_DCACHE_OFF */
+
+/* Comment out the following to enable L2 cache */
+#define CONFIG_UNIPHIER_L2CACHE_ON
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+#define CONFIG_TIMESTAMP
+
+/* FLASH related */
+#define CONFIG_MTD_DEVICE
+
+/*
+ * uncomment the following to disable FLASH related code.
+ */
+/* #define CONFIG_SYS_NO_FLASH */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MONITOR_BASE		0
+#define CONFIG_SYS_FLASH_BASE		0
+
+/*
+ * flash_toggle does not work for out supoort card.
+ * We need to use flash_status_poll.
+ */
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
+
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
+# define CONFIG_SYS_MAX_FLASH_BANKS	1
+# define CONFIG_SYS_FLASH_BANKS_LIST	{0x00000000}
+# define CONFIG_SYS_FLASH_BANKS_SIZES	{0x02000000}
+#endif
+
+#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+# define CONFIG_SYS_MAX_FLASH_BANKS	1
+# define CONFIG_SYS_FLASH_BANKS_LIST	{0x04000000}
+# define CONFIG_SYS_FLASH_BANKS_SIZES	{0x04000000}
+#endif
+
+/* serial console configuration */
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#if !defined(CONFIG_SPL_BUILD)
+#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_USE_ARCH_MEMCPY
+#endif
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_CONS_INDEX		1
+
+/*
+ * For NAND booting the environment is embedded in the U-Boot image. Please take
+ * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
+ */
+/* #define CONFIG_ENV_IS_IN_NAND */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE				0x2000
+#define CONFIG_ENV_OFFSET			0x0
+/* #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
+
+/* Time clock 1MHz */
+#define CONFIG_SYS_TIMER_RATE			1000000
+
+/*
+ * By default, ARP timeout is 5 sec.
+ * The first ARP request does not seem to work.
+ * So we need to retry ARP request anyway.
+ * We want to shrink the interval until the second ARP request.
+ */
+#define CONFIG_ARP_TIMEOUT	500UL  /* 0.5 msec */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_TIME
+#define CONFIG_CMD_NAND		/* NAND flash suppport */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE			1
+#define CONFIG_SYS_NAND_MAX_CHIPS			2
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_NAND_DENALI_ECC_SIZE			1024
+
+#define CONFIG_SYS_NAND_REGS_BASE			0x68100000
+#define CONFIG_SYS_NAND_DATA_BASE			0x68000000
+
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_DATA_BASE + 0x10)
+
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS			0
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01000000)
+
+#define CONFIG_BOOTDELAY			3
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED			1
+#define CONFIG_AUTOBOOT_PROMPT	\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR		"d"
+#define CONFIG_AUTOBOOT_STOP_STR		" "
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_ETHADDR			00:21:83:24:00:00
+#define CONFIG_SERVERIP			192.168.11.1
+#define CONFIG_IPADDR			192.168.11.10
+#define CONFIG_GATEWAYIP		192.168.11.1
+#define CONFIG_NETMASK			255.255.255.0
+
+#define CONFIG_LOADADDR			0x84000000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_BOOTFILE			"fit.itb"
+
+#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
+
+#define CONFIG_BOOTCOMMAND		"run $bootmode"
+
+#define CONFIG_ROOTPATH			"/nfs/root/path"
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs $bootargs root=/dev/nfs rw "			\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
+	"tftpboot; bootm;"
+
+#define CONFIG_BOOTARGS		" user_debug=0x1f init=/sbin/init"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"image_offset=0x00080000\0"		\
+	"image_size=0x00f00000\0"		\
+	"verify=n\0"				\
+	"autostart=yes\0"			\
+	"norboot=run add_default_bootargs;"				\
+		"bootm $image_offset\0"					\
+	"nandboot=run add_default_bootargs;"				\
+		"nand read $loadaddr $image_offset $image_size;"	\
+		"bootm\0"						\
+	"add_default_bootargs=setenv bootargs $bootargs"		\
+		" console=ttyS0,$baudrate\0"				\
+
+/* FIT support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
+
+/* Open Firmware flat tree */
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_HAVE_ARM_SECURE
+
+/* Memory Size & Mapping */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SDRAM0_BASE
+
+#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
+/* Thre is no memory hole */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
+#else
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SDRAM0_SIZE)
+#endif
+
+#define CONFIG_SYS_TEXT_BASE		0x84000000
+
+#if defined(CONFIG_SPL_BUILD)
+#define CONFIG_BOARD_POSTCLK_INIT
+#else
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_SYS_SPL_MALLOC_START	(0x0ff00000)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	(0x00004000)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(0x0ff08000)
+
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NAND_SUPPORT
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT	/* for mem_malloc_init */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS		0x10000
+
+#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
diff --git a/include/configs/vct.h b/include/configs/vct.h
index 5ab4de3274..217ba2fbd9 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -296,7 +296,6 @@ int vct_gpio_get(int pin);
 #undef CONFIG_CMD_BEDBUG
 #undef CONFIG_CMD_CACHE
 #undef CONFIG_CMD_CONSOLE
-#undef CONFIG_CMD_CRC32
 #undef CONFIG_CMD_DHCP
 #undef CONFIG_CMD_EEPROM
 #undef CONFIG_CMD_EEPROM
diff --git a/include/configs/venice2.h b/include/configs/venice2.h
index 6d4e9991a1..6897aa8aa3 100644
--- a/include/configs/venice2.h
+++ b/include/configs/venice2.h
@@ -12,11 +12,6 @@
 
 #include "tegra124-common.h"
 
-/* Enable fdt support for Venice2. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra124-venice2
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT			"Tegra124 (Venice2) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Venice2"
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index edf3720b61..f195f8a6ea 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -11,11 +11,6 @@
 #include <linux/sizes.h>
 #include "tegra20-common.h"
 
-/* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-ventana
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (Ventana) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Ventana"
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index 0897932095..f3af971214 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -51,7 +51,6 @@
 /* Flat Device Tree Definitions */
 #define CONFIG_OF_LIBFDT
 
-#define CONFIG_DEFAULT_DEVICE_TREE	vexpress64
 
 /* SMP Spin Table Definitions */
 #ifdef CONFIG_BASE_FVP
diff --git a/include/configs/vision2.h b/include/configs/vision2.h
index 6891bf8b15..3f35076f9e 100644
--- a/include/configs/vision2.h
+++ b/include/configs/vision2.h
@@ -57,11 +57,11 @@
  * Use gpio 4 pin 25 as chip select for SPI flash
  * This corresponds to gpio 121
  */
-#define CONFIG_SF_DEFAULT_CS	(1 | (121 << 8))
+#define CONFIG_SF_DEFAULT_CS	 1
 #define CONFIG_SF_DEFAULT_MODE   SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED  25000000
 
-#define CONFIG_ENV_SPI_CS	(1 | (121 << 8))
+#define CONFIG_ENV_SPI_CS	CONFIG_SF_DEFAULT_CS
 #define CONFIG_ENV_SPI_BUS      0
 #define CONFIG_ENV_SPI_MAX_HZ	25000000
 #define CONFIG_ENV_SPI_MODE	SPI_MODE_0
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index 9e09f03d52..10e70d28b1 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -11,11 +11,6 @@
 #include <linux/sizes.h>
 #include "tegra20-common.h"
 
-/* Enable fdt support for Whistler. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-whistler
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
 /* High-level configuration options */
 #define V_PROMPT		"Tegra20 (Whistler) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Whistler"
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 875cb43f15..0b4dd665b8 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -227,8 +227,6 @@
 #define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */
 
 /* FDT support */
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 
 /* RSA support */
@@ -273,18 +271,13 @@
 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_FAT_SUPPORT
-#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_OF_SEPARATE)
-# define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME     "u-boot-dtb.img"
-#else
-# define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME     "u-boot.img"
-#endif
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME     "u-boot-dtb.img"
 #endif
 
 /* Disable dcache for SPL just for sure */
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_DCACHE_OFF
 #undef CONFIG_FPGA
-#undef CONFIG_OF_CONTROL
 #endif
 
 /* Address in RAM where the parameters must be copied by SPL. */
@@ -303,9 +296,7 @@
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_BUS	0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x100000
-#define CONFIG_SPL_SPI_CS	0
 #endif
 
 /* for booting directly linux */
diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h
index b0328a2cc1..549a664ef5 100644
--- a/include/configs/zynq_microzed.h
+++ b/include/configs/zynq_microzed.h
@@ -19,7 +19,6 @@
 #define CONFIG_SYS_NO_FLASH
 
 #define CONFIG_ZYNQ_SDHCI0
-#define CONFIG_DEFAULT_DEVICE_TREE	zynq-microzed
 
 #include <configs/zynq-common.h>
 
diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h
index 291a5fef51..b6590547a9 100644
--- a/include/configs/zynq_zc70x.h
+++ b/include/configs/zynq_zc70x.h
@@ -23,7 +23,6 @@
 #define CONFIG_ZYNQ_I2C0
 #define CONFIG_ZYNQ_EEPROM
 #define CONFIG_ZYNQ_BOOT_FREEBSD
-#define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc702
 
 #include <configs/zynq-common.h>
 
diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h
index 8aa96e7121..16b904743f 100644
--- a/include/configs/zynq_zc770.h
+++ b/include/configs/zynq_zc770.h
@@ -20,18 +20,15 @@
 # define CONFIG_ZYNQ_GEM_PHY_ADDR0	7
 # define CONFIG_ZYNQ_SDHCI0
 # define CONFIG_ZYNQ_SPI
-# define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc770-xm010
 
 #elif defined(CONFIG_ZC770_XM012)
 # define CONFIG_ZYNQ_SERIAL_UART1
 # undef CONFIG_SYS_NO_FLASH
-# define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc770-xm012
 
 #elif defined(CONFIG_ZC770_XM013)
 # define CONFIG_ZYNQ_SERIAL_UART0
 # define CONFIG_ZYNQ_GEM1
 # define CONFIG_ZYNQ_GEM_PHY_ADDR1	7
-# define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc770-xm013
 
 #else
 # define CONFIG_ZYNQ_SERIAL_UART0
diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h
index ce17d4060c..946de953e4 100644
--- a/include/configs/zynq_zed.h
+++ b/include/configs/zynq_zed.h
@@ -21,7 +21,6 @@
 #define CONFIG_ZYNQ_USB
 #define CONFIG_ZYNQ_SDHCI0
 #define CONFIG_ZYNQ_BOOT_FREEBSD
-#define CONFIG_DEFAULT_DEVICE_TREE	zynq-zed
 
 #include <configs/zynq-common.h>
 
diff --git a/include/fb_mmc.h b/include/fb_mmc.h
new file mode 100644
index 0000000000..1ad1d1327d
--- /dev/null
+++ b/include/fb_mmc.h
@@ -0,0 +1,8 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+void fb_mmc_flash_write(const char *cmd, void *download_buffer,
+			unsigned int download_bytes, char *response);
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 1bda686a0b..c3d1fbcf35 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -133,6 +133,18 @@ static inline int fdt_status_fail_by_alias(void *fdt, const char *alias)
 	return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_FAIL, 0);
 }
 
+/* Helper to read a big number; size is in cells (not bytes) */
+static inline u64 of_read_number(const fdt32_t *cell, int size)
+{
+	u64 r = 0;
+	while (size--)
+		r = (r << 32) | fdt32_to_cpu(*(cell++));
+	return r;
+}
+
+void of_bus_default_count_cells(void *blob, int parentoffset,
+					int *addrc, int *sizec);
+
 #endif /* ifdef CONFIG_OF_LIBFDT */
 
 #ifdef USE_HOSTCC
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
index 5c49b229da..675557ad1f 100644
--- a/include/fsl_ddr.h
+++ b/include/fsl_ddr.h
@@ -15,6 +15,11 @@
 
 #include <common_timing_params.h>
 
+#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
+/* All controllers are for main memory */
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	CONFIG_NUM_DDR_CONTROLLERS
+#endif
+
 #ifdef CONFIG_SYS_FSL_DDR_LE
 #define ddr_in32(a)	in_le32(a)
 #define ddr_out32(a, v)	out_le32(a, v)
@@ -57,6 +62,13 @@ typedef struct {
 	memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
 	common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
 	fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
+	unsigned int first_ctrl;
+	unsigned int num_ctrls;
+	unsigned long long mem_base;
+	unsigned int dimm_slots_per_ctrl;
+	int (*board_need_mem_reset)(void);
+	void (*board_mem_reset)(void);
+	void (*board_mem_de_reset)(void);
 } fsl_ddr_info_t;
 
 /* Compute steps */
@@ -72,7 +84,6 @@ typedef struct {
 unsigned long long
 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 				       unsigned int size_only);
-
 const char *step_to_string(unsigned int step);
 
 unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts,
@@ -102,7 +113,7 @@ void fsl_ddr_set_lawbar(
 int fsl_ddr_interactive_env_var_exists(void);
 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
-			   unsigned int ctrl_num);
+		     unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index 987119b014..5b03c14c55 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -51,7 +51,6 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
 #define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR2
 #endif
 #elif defined(CONFIG_SYS_FSL_DDR3)
-#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)	/* FIXME */
 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #ifndef CONFIG_FSL_SDRAM_TYPE
 #define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR3
@@ -352,7 +351,6 @@ typedef struct memctl_options_s {
 	unsigned int twot_en;
 	unsigned int threet_en;
 	unsigned int bstopre;
-	unsigned int tcke_clock_pulse_width_ps;	/* tCKE */
 	unsigned int tfaw_window_four_activates_ps;	/* tFAW --  FOUR_ACT */
 
 	/* Rtt impedance */
@@ -379,12 +377,20 @@ typedef struct memctl_options_s {
 	unsigned int trwt;			/* read-to-write turnaround */
 } memctl_options_t;
 
-extern phys_size_t fsl_ddr_sdram(void);
-extern phys_size_t fsl_ddr_sdram_size(void);
+phys_size_t fsl_ddr_sdram(void);
+phys_size_t fsl_ddr_sdram_size(void);
+phys_size_t fsl_other_ddr_sdram(unsigned long long base,
+				unsigned int first_ctrl,
+				unsigned int num_ctrls,
+				unsigned int dimm_slots_per_ctrl,
+				int (*board_need_reset)(void),
+				void (*board_reset)(void),
+				void (*board_de_reset)(void));
 extern int fsl_use_spd(void);
-extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-					unsigned int ctrl_num, int step);
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+			     unsigned int ctrl_num, int step);
 u32 fsl_ddr_get_intl3r(void);
+void print_ddr_info(unsigned int start_ctrl);
 
 static void __board_assert_mem_reset(void)
 {
diff --git a/include/linker_lists.h b/include/linker_lists.h
index 557e6273ad..507d61ba9a 100644
--- a/include/linker_lists.h
+++ b/include/linker_lists.h
@@ -28,11 +28,11 @@
  * together. Assuming _list and _entry are the list and entry names,
  * then the corresponding input section name is
  *
- *   _u_boot_list + _2_ + @_list + _2_ + @_entry
+ *   .u_boot_list_ + 2_ + @_list + _2_ + @_entry
  *
  * and the C variable name is
  *
- *   .u_boot_list_ + 2_ + @_list + _2_ + @_entry
+ *   _u_boot_list + _2_ + @_list + _2_ + @_entry
  *
  * This ensures uniqueness for both input section and C variable name.
  *
diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
index 02ae99e8e6..e057bd2a84 100644
--- a/include/linux/compiler-gcc.h
+++ b/include/linux/compiler-gcc.h
@@ -64,8 +64,12 @@
 #endif
 
 #define __deprecated			__attribute__((deprecated))
+#ifndef __packed
 #define __packed			__attribute__((packed))
+#endif
+#ifndef __weak
 #define __weak				__attribute__((weak))
+#endif
 
 /*
  * it doesn't make sense on ARM (currently the only user of __naked) to trace
@@ -91,8 +95,12 @@
  * would be.
  * [...]
  */
+#ifndef __pure
 #define __pure				__attribute__((pure))
+#endif
+#ifndef __aligned
 #define __aligned(x)			__attribute__((aligned(x)))
+#endif
 #define __printf(a, b)			__attribute__((format(printf, a, b)))
 #define __scanf(a, b)			__attribute__((format(scanf, a, b)))
 #define  noinline			__attribute__((noinline))
@@ -115,4 +123,6 @@
  */
 #define uninitialized_var(x) x = x
 
+#ifndef __always_inline
 #define __always_inline		inline __attribute__((always_inline))
+#endif
diff --git a/include/pci.h b/include/pci.h
index 461f17c058..2ff73653c5 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -659,6 +659,13 @@ extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
 			int cap);
 
+#ifdef CONFIG_PCI_FIXUP_DEV
+extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
+				unsigned short vendor,
+				unsigned short device,
+				unsigned short class);
+#endif
+
 const char * pci_class_str(u8 class);
 int pci_last_busno(void);
 
diff --git a/include/sata.h b/include/sata.h
index c95dc56e94..38f4b4acf6 100644
--- a/include/sata.h
+++ b/include/sata.h
@@ -9,6 +9,7 @@ ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer);
 
 int sata_initialize(void);
 int __sata_initialize(void);
+int sata_port_status(int dev, int port);
 
 extern block_dev_desc_t sata_dev_desc[];
 
diff --git a/include/spi.h b/include/spi.h
index ffd66478b1..b673be270c 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -30,24 +30,24 @@
 #define SPI_XFER_MMAP		0x08	/* Memory Mapped start */
 #define SPI_XFER_MMAP_END	0x10	/* Memory Mapped End */
 #define SPI_XFER_ONCE		(SPI_XFER_BEGIN | SPI_XFER_END)
-#define SPI_XFER_U_PAGE		(1 << 5)
+#define SPI_XFER_U_PAGE	(1 << 5)
 
 /* SPI TX operation modes */
-#define SPI_OPM_TX_QPP		1 << 0
+#define SPI_OPM_TX_QPP		(1 << 0)
 
 /* SPI RX operation modes */
-#define SPI_OPM_RX_AS		1 << 0
-#define SPI_OPM_RX_DOUT		1 << 1
-#define SPI_OPM_RX_DIO		1 << 2
-#define SPI_OPM_RX_QOF		1 << 3
-#define SPI_OPM_RX_QIOF		1 << 4
-#define SPI_OPM_RX_EXTN		SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \
+#define SPI_OPM_RX_AS		(1 << 0)
+#define SPI_OPM_RX_DOUT	(1 << 1)
+#define SPI_OPM_RX_DIO		(1 << 2)
+#define SPI_OPM_RX_QOF		(1 << 3)
+#define SPI_OPM_RX_QIOF	(1 << 4)
+#define SPI_OPM_RX_EXTN	(SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \
 				SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
-				SPI_OPM_RX_QIOF
+				SPI_OPM_RX_QIOF)
 
-/* SPI bus connection options */
-#define SPI_CONN_DUAL_SHARED	1 << 0
-#define SPI_CONN_DUAL_SEPARATED	1 << 1
+/* SPI bus connection options - see enum spi_dual_flash */
+#define SPI_CONN_DUAL_SHARED		(1 << 0)
+#define SPI_CONN_DUAL_SEPARATED	(1 << 1)
 
 /* Header byte that marks the start of the message */
 #define SPI_PREAMBLE_END_BYTE	0xec
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 2db53c74c8..408a5b401c 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -19,6 +19,19 @@
 #include <linux/types.h>
 #include <linux/compiler.h>
 
+#ifndef CONFIG_SF_DEFAULT_SPEED
+# define CONFIG_SF_DEFAULT_SPEED	1000000
+#endif
+#ifndef CONFIG_SF_DEFAULT_MODE
+# define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+#endif
+#ifndef CONFIG_SF_DEFAULT_CS
+# define CONFIG_SF_DEFAULT_CS		0
+#endif
+#ifndef CONFIG_SF_DEFAULT_BUS
+# define CONFIG_SF_DEFAULT_BUS		0
+#endif
+
 /* sf param flags */
 #define SECT_4K		1 << 1
 #define SECT_32K	1 << 2
diff --git a/lib/Kconfig b/lib/Kconfig
new file mode 100644
index 0000000000..88e5da72ec
--- /dev/null
+++ b/lib/Kconfig
@@ -0,0 +1,11 @@
+menu "Library routines"
+
+config CC_OPTIMIZE_LIBS_FOR_SPEED
+	bool "Optimize libraries for speed"
+	help
+	  Enabling this option will pass "-O2" to gcc when compiling
+	  under "lib" directory.
+
+	  If unsure, say N.
+
+endmenu
diff --git a/net/Kconfig b/net/Kconfig
new file mode 100644
index 0000000000..22b9eaac53
--- /dev/null
+++ b/net/Kconfig
@@ -0,0 +1,10 @@
+#
+# Network configuration
+#
+
+menuconfig NET
+	bool "Networking support"
+
+if NET
+
+endif   # if NET
diff --git a/net/dns.c b/net/dns.c
index ff9ddffc9d..dd45320150 100644
--- a/net/dns.c
+++ b/net/dns.c
@@ -202,5 +202,8 @@ DnsStart(void)
 	NetSetTimeout(DNS_TIMEOUT, DnsTimeout);
 	net_set_udp_handler(DnsHandler);
 
+	/* Clear a previous MAC address, the server IP might have changed. */
+	memset(NetServerEther, 0, sizeof(NetServerEther));
+
 	DnsSend();
 }
diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf
index 44c39970f3..ced2b9a6b0 100644
--- a/scripts/Makefile.autoconf
+++ b/scripts/Makefile.autoconf
@@ -74,7 +74,6 @@ define filechk_config_h
 		| sed '/=/ {s/=/	/;q; } ; { s/$$/	1/; }'; \
 	done;								\
 	echo \#define CONFIG_BOARDDIR board/$(if $(VENDOR),$(VENDOR)/)$(BOARD);\
-	echo \#include \<config_cmd_defaults.h\>;			\
 	echo \#include \<config_defaults.h\>;				\
 	echo \#include \<configs/$(CONFIG_SYS_CONFIG_NAME).h\>;		\
 	echo \#include \<asm/config.h\>;				\
diff --git a/scripts/Makefile.clean b/scripts/Makefile.clean
index d6dcd47f6f..88f14e2d8f 100644
--- a/scripts/Makefile.clean
+++ b/scripts/Makefile.clean
@@ -45,8 +45,8 @@ subdir-ymn	:= $(foreach f, $(subdir-ymn), \
 # build a list of files to remove, usually relative to the current
 # directory
 
-__clean-files	:= $(extra-y) $(always)                  \
-		   $(targets) $(clean-files)             \
+__clean-files	:= $(extra-y) $(extra-m) $(extra-)       \
+		   $(always) $(targets) $(clean-files)   \
 		   $(host-progs)                         \
 		   $(hostprogs-y) $(hostprogs-m) $(hostprogs-)
 
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 3fed5e4694..74db2e24fc 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -2148,7 +2148,7 @@ sub process {
 				"please, no space before tabs\n" . $herevet) &&
 			    $fix) {
 				while ($fixed[$linenr - 1] =~
-					   s/(^\+.*) {8,8}+\t/$1\t\t/) {}
+					   s/(^\+.*) {8,8}\t/$1\t\t/) {}
 				while ($fixed[$linenr - 1] =~
 					   s/(^\+.*) +\t/$1\t/) {}
 			}
diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh
index a5790428c8..4a8737f352 100644
--- a/scripts/multiconfig.sh
+++ b/scripts/multiconfig.sh
@@ -118,6 +118,13 @@ do_board_defconfig () {
 	defconfig_path=$srctree/configs/$1
 	tmp_defconfig_path=configs/.tmp_defconfig
 
+	if [ ! -r $defconfig_path ]; then
+		echo >&2 "***"
+		echo >&2 "*** Can't find default configuration \"confis/$1\"!"
+		echo >&2 "***"
+		exit 1
+	fi
+
 	mkdir -p arch configs
 	# defconfig for Normal:
 	#  pick lines without prefixes and lines starting '+' prefix
@@ -245,6 +252,35 @@ do_savedefconfig () {
 	IFS=$save_IFS
 }
 
+# Some sanity checks before running "make <objdir>/<target>",
+# where <objdir> should be either "spl" or "tpl".
+# Doing "make spl/menuconfig" etc. on a non-SPL board makes no sense.
+# It should be allowed only when ".config" exists and "CONFIG_SPL" is enabled.
+#
+# Usage:
+#   check_enabled_sumbimage <objdir>/<target> <objdir>
+check_enabled_subimage () {
+
+	case $2 in
+	spl|tpl) ;;
+	*)
+		echo >&2 "***"
+		echo >&2 "*** \"make $1\" is not supported."
+		echo >&2 "***"
+		exit 1
+		;;
+	esac
+	test -r "$KCONFIG_CONFIG" && get_enabled_subimages | grep -q $2 || {
+		config=CONFIG_$(echo $2 | tr '[a-z]' '[A-Z]')
+
+		echo >&2 "***"
+		echo >&2 "*** Create \"$KCONFIG_CONFIG\" with \"$config\" enabled"
+		echo >&2 "*** before \"make $1\"."
+		echo >&2 "***"
+		exit 1
+	}
+}
+
 # Usage:
 #   do_others <objdir>/<target>
 # The field "<objdir>/" is typically empy, "spl/", "tpl/" for Normal, SPL, TPL,
@@ -258,6 +294,7 @@ do_others () {
 		objdir=
 	else
 		objdir=${1%/*}
+		check_enabled_subimage $1 $objdir
 	fi
 
 	run_make_config $target $objdir
diff --git a/test/cmd_repeat.sh b/test/cmd_repeat.sh
new file mode 100755
index 0000000000..990e79900f
--- /dev/null
+++ b/test/cmd_repeat.sh
@@ -0,0 +1,29 @@
+#!/bin/sh
+
+# Test for U-Boot cli including command repeat
+
+BASE="$(dirname $0)"
+. $BASE/common.sh
+
+run_test() {
+	./${OUTPUT_DIR}/u-boot <<END
+setenv ctrlc_ignore y
+md 0
+
+reset
+END
+}
+check_results() {
+	echo "Check results"
+
+	grep -q 00000100 ${tmp} || fail "Command did not repeat"
+}
+
+echo "Test CLI repeat"
+echo
+tmp="$(tempfile)"
+build_uboot
+run_test >${tmp}
+check_results ${tmp}
+rm ${tmp}
+echo "Test passed"
diff --git a/test/common.sh b/test/common.sh
new file mode 100644
index 0000000000..702d1ed051
--- /dev/null
+++ b/test/common.sh
@@ -0,0 +1,20 @@
+#!/bin/sh
+
+OUTPUT_DIR=sandbox
+
+fail() {
+	echo "Test failed: $1"
+	if [ -n ${tmp} ]; then
+		rm ${tmp}
+	fi
+	exit 1
+}
+
+build_uboot() {
+	echo "Build sandbox"
+	OPTS="O=${OUTPUT_DIR} $1"
+	NUM_CPUS=$(grep -c processor /proc/cpuinfo)
+	echo ${OPTS}
+	make ${OPTS} sandbox_config
+	make ${OPTS} -s -j${NUM_CPUS}
+}
diff --git a/test/trace/test-trace.sh b/test/trace/test-trace.sh
index aa02f09475..3e8651ed60 100755
--- a/test/trace/test-trace.sh
+++ b/test/trace/test-trace.sh
@@ -5,39 +5,25 @@
 
 # Simple test script for tracing with sandbox
 
-OUTPUT_DIR=sandbox
 TRACE_OPT="FTRACE=1"
 
-fail() {
-	echo "Test failed: $1"
-	if [ -n ${tmp} ]; then
-		rm ${tmp}
-	fi
-	exit 1
-}
-
-build_uboot() {
-	echo "Build sandbox"
-	OPTS="O=${OUTPUT_DIR} ${TRACE_OPT}"
-	NUM_CPUS=$(grep -c processor /proc/cpuinfo)
-	make ${OPTS} sandbox_config
-	make ${OPTS} -s -j${NUM_CPUS}
-}
+BASE="$(dirname $0)/.."
+. $BASE/common.sh
 
 run_trace() {
 	echo "Run trace"
 	./${OUTPUT_DIR}/u-boot <<END
-	trace stats
-	hash sha256 0 10000
-	trace pause
-	trace stats
-	hash sha256 0 10000
-	trace stats
-	trace resume
-	hash sha256 0 10000
-	trace pause
-	trace stats
-	reset
+trace stats
+hash sha256 0 10000
+trace pause
+trace stats
+hash sha256 0 10000
+trace stats
+trace resume
+hash sha256 0 10000
+trace pause
+trace stats
+reset
 END
 }
 
@@ -69,7 +55,7 @@ check_results() {
 echo "Simple trace test / sanity check using sandbox"
 echo
 tmp="$(tempfile)"
-build_uboot
+build_uboot "${TRACE_OPT}"
 run_trace >${tmp}
 check_results ${tmp}
 rm ${tmp}
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index e97350f9a0..8b8c826002 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -244,13 +244,13 @@ def DoBuildman(options, args, toolchains=None, make_func=None, boards=None,
         Print(GetActionSummary(options.summary, commits, board_selected,
                                 options))
 
+        # We can't show function sizes without board details at present
+        if options.show_bloat:
+            options.show_detail = True
         builder.SetDisplayOptions(options.show_errors, options.show_sizes,
                                   options.show_detail, options.show_bloat,
                                   options.list_error_boards)
         if options.summary:
-            # We can't show function sizes without board details at present
-            if options.show_bloat:
-                options.show_detail = True
             builder.ShowSummary(commits, board_selected)
         else:
             fail, warned = builder.BuildBoards(commits, board_selected,
diff --git a/tools/buildman/kconfiglib.py b/tools/buildman/kconfiglib.py
index 31fd3c912b..655cf4470f 100644
--- a/tools/buildman/kconfiglib.py
+++ b/tools/buildman/kconfiglib.py
@@ -1,5 +1,5 @@
 #
-# SPDX-License-Identifier:	GPL-2.0+
+# SPDX-License-Identifier:	ISC
 #
 # Author: Ulf Magnusson
 #   https://github.com/ulfalizer/Kconfiglib
diff --git a/tools/env/Makefile b/tools/env/Makefile
index 4927489b16..40164f7a35 100644
--- a/tools/env/Makefile
+++ b/tools/env/Makefile
@@ -21,14 +21,16 @@ HOST_EXTRACFLAGS += -DMTD_OLD
 endif
 
 always := fw_printenv
-hostprogs-y := fw_printenv_unstripped
+hostprogs-y := fw_printenv
 
-fw_printenv_unstripped-objs := fw_env.o fw_env_main.o \
+fw_printenv-objs := fw_env.o fw_env_main.o \
 	crc32.o ctype.o linux_string.o \
 	env_attr.o env_flags.o aes.o
 
-quiet_cmd_strip = STRIP   $@
-      cmd_strip = $(STRIP) -o $@ $<
+quiet_cmd_crosstools_strip = STRIP   $^
+      cmd_crosstools_strip = $(STRIP) $^; touch $@
 
-$(obj)/fw_printenv: $(obj)/fw_printenv_unstripped FORCE
-	$(call if_changed,strip)
+$(obj)/.strip: $(obj)/fw_printenv
+	$(call cmd,crosstools_strip)
+
+always += .strip
diff --git a/tools/genboardscfg.py b/tools/genboardscfg.py
index 654100bf07..23c956bb8e 100755
--- a/tools/genboardscfg.py
+++ b/tools/genboardscfg.py
@@ -328,6 +328,9 @@ class MaintainersDatabase:
         maintainers = []
         status = '-'
         for line in open(file):
+            # Check also commented maintainers
+            if line[:3] == '#M:':
+                line = line[1:]
             tag, rest = line[:2], line[2:].strip()
             if tag == 'M:':
                 maintainers.append(rest)
diff --git a/tools/imximage.c b/tools/imximage.c
index 18dc051c5e..faba23860f 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -568,6 +568,13 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
 	/* Parse dcd configuration file */
 	dcd_len = parse_cfg_file(imxhdr, params->imagename);
 
+	if (imximage_version == IMXIMAGE_V2) {
+		if (imximage_init_loadsize < imximage_ivt_offset +
+			sizeof(imx_header_v2_t))
+				imximage_init_loadsize = imximage_ivt_offset +
+					sizeof(imx_header_v2_t);
+	}
+
 	/* Set the imx header */
 	(*set_imx_hdr)(imxhdr, dcd_len, params->ep, imximage_ivt_offset);
 
diff --git a/tools/imximage.h b/tools/imximage.h
index 01f861e7a5..5b5ad0edf4 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -8,7 +8,7 @@
 #ifndef _IMXIMAGE_H_
 #define _IMXIMAGE_H_
 
-#define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 */
+#define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */
 #define MAX_HW_CFG_SIZE_V1 60  /* Max number of registers imx can set for v1 */
 #define APP_CODE_BARKER	0xB1
 #define DCD_BARKER	0xB17219E9
diff --git a/tools/patman/README b/tools/patman/README
index 5fb508b80d..e466886ed2 100644
--- a/tools/patman/README
+++ b/tools/patman/README
@@ -27,8 +27,8 @@ Series-to: fred.blogs@napier.co.nz
 
 in one of your commits, the series will be sent there.
 
-In Linux this will also call get_maintainer.pl on each of your
-patches automatically.
+In Linux and U-Boot this will also call get_maintainer.pl on each of your
+patches automatically (unless you use -m to disable this).
 
 
 How to use this tool
diff --git a/tools/patman/patman.py b/tools/patman/patman.py
index 2ab6b351d6..6c6473e462 100755
--- a/tools/patman/patman.py
+++ b/tools/patman/patman.py
@@ -32,6 +32,9 @@ parser.add_option('-c', '--count', dest='count', type='int',
 parser.add_option('-i', '--ignore-errors', action='store_true',
        dest='ignore_errors', default=False,
        help='Send patches email even if patch errors are found')
+parser.add_option('-m', '--no-maintainers', action='store_false',
+       dest='add_maintainers', default=True,
+       help="Don't cc the file maintainers automatically")
 parser.add_option('-n', '--dry-run', action='store_true', dest='dry_run',
        default=False, help="Do a dry run (create but don't email patches)")
 parser.add_option('-p', '--project', default=project.DetectProject(),
@@ -142,7 +145,8 @@ else:
         ok = True
 
     cc_file = series.MakeCcFile(options.process_tags, cover_fname,
-                                not options.ignore_bad_tags)
+                                not options.ignore_bad_tags,
+                                options.add_maintainers)
 
     # Email the patches out (giving the user time to check / cancel)
     cmd = ''
diff --git a/tools/patman/series.py b/tools/patman/series.py
index 88c0d877d4..b67f870b7e 100644
--- a/tools/patman/series.py
+++ b/tools/patman/series.py
@@ -201,7 +201,8 @@ class Series(dict):
             str = 'Change log exists, but no version is set'
             print col.Color(col.RED, str)
 
-    def MakeCcFile(self, process_tags, cover_fname, raise_on_error):
+    def MakeCcFile(self, process_tags, cover_fname, raise_on_error,
+                   add_maintainers):
         """Make a cc file for us to use for per-commit Cc automation
 
         Also stores in self._generated_cc to make ShowActions() faster.
@@ -211,6 +212,7 @@ class Series(dict):
             cover_fname: If non-None the name of the cover letter.
             raise_on_error: True to raise an error when an alias fails to match,
                 False to just print a message.
+            add_maintainers: Call the get_maintainers to CC maintainers
         Return:
             Filename of temp file created
         """
@@ -225,7 +227,8 @@ class Series(dict):
                                                raise_on_error=raise_on_error)
             list += gitutil.BuildEmailList(commit.cc_list,
                                            raise_on_error=raise_on_error)
-            list += get_maintainer.GetMaintainer(commit.patch)
+	    if add_maintainers:
+                list += get_maintainer.GetMaintainer(commit.patch)
             all_ccs += list
             print >>fd, commit.patch, ', '.join(list)
             self._generated_cc[commit.patch] = list
diff --git a/tools/reformat.py b/tools/reformat.py
deleted file mode 100755
index 61306d0235..0000000000
--- a/tools/reformat.py
+++ /dev/null
@@ -1,132 +0,0 @@
-#! /usr/bin/python
-########################################################################
-#
-# reorder and reformat a file in columns
-#
-# this utility takes lines from its standard input and reproduces them,
-# partially reordered and reformatted, on its standard output.
-#
-# It has the same effect as a 'sort | column -t', with the exception
-# that empty lines, as well as lines which start with a '#' sign, are
-# not affected, i.e. they keep their position and formatting, and act
-# as separators, i.e. the parts before and after them are each sorted
-# separately (but overall field widths are computed across the whole
-# input).
-#
-# Options:
-#   -i:
-#   --ignore-case:
-#	Do not consider case when sorting.
-#   -d:
-#   --default:
-#	What to chage empty fields to.
-#    -s <N>:
-#    --split=<N>:
-#       Treat only the first N whitespace sequences as separators.
-#       line content after the Nth separator will count as only one
-#       field even if it contains whitespace.
-#       Example : '-s 2' causes input 'a b c d e' to be split into
-#       three fields, 'a', 'b', and 'c d e'.
-#
-# boards.cfg requires -ids 6.
-#
-########################################################################
-
-import sys, getopt, locale
-
-# ensure we sort using the C locale.
-
-locale.setlocale(locale.LC_ALL, 'C')
-
-# check options
-
-maxsplit = 0
-ignore_case = 0
-default_field =''
-
-try:
-	opts, args = getopt.getopt(sys.argv[1:], "id:s:",
-		["ignore-case","default","split="])
-except getopt.GetoptError as err:
-	print str(err) # will print something like "option -a not recognized"
-	sys.exit(2)
-
-for o, a in opts:
-	if o in ("-s", "--split"):
-		maxsplit = eval(a)
-	elif o in ("-i", "--ignore-case"):
-		ignore_case = 1
-	elif o in ("-d", "--default"):
-		default_field = a
-	else:
-		assert False, "unhandled option"
-
-# collect all lines from standard input and, for the ones which must be
-# reformatted and sorted, count their fields and compute each field's
-# maximum size
-
-input_lines = []
-field_width = []
-
-for line in sys.stdin:
-	# remove final end of line
-	input_line = line.strip('\n')
-	if (len(input_line)>0) and (input_line[0] != '#'):
-		# sortable line: split into fields
-		fields = input_line.split(None,maxsplit)
-		# if there are new fields, top up field_widths
-		for f in range(len(field_width), len(fields)):
-			field_width.append(0)
-		# compute the maximum witdh of each field
-		for f in range(len(fields)):
-			field_width[f] = max(field_width[f],len(fields[f]))
-	# collect the line for next stage
-	input_lines.append(input_line)
-
-# run through collected input lines, collect the ones which must be
-# reformatted and sorted, and whenever a non-reformattable, non-sortable
-# line is met, sort the collected lines before it and append them to the
-# output lines, then add the non-sortable line too.
-
-output_lines = []
-sortable_lines = []
-for input_line in input_lines:
-	if (len(input_line)>0) and (input_line[0] != '#'):
-		# this line should be reformatted and sorted
-		input_fields = input_line.split(None,maxsplit)
-		output_fields = [];
-		# reformat each field to this field's column width
-		for f in range(len(input_fields)):
-			output_field = input_fields[f];
-			output_fields.append(output_field.ljust(field_width[f]))
-		# any missing field is set to default if it exists
-		if default_field != '':
-			for f in range(len(input_fields),len(field_width)):
-				output_fields.append(default_field.ljust(field_width[f]))
-		# join fields using two spaces, like column -t would
-		output_line = '  '.join(output_fields);
-		# collect line for later
-		sortable_lines.append(output_line)
-	else:
-		# this line is non-sortable
-		# sort collected sortable lines
-		if ignore_case!=0:
-			sortable_lines.sort(key=lambda x: str.lower(locale.strxfrm(x)))
-		else:
-			sortable_lines.sort(key=lambda x: locale.strxfrm(x))
-		# append sortable lines to the final output
-		output_lines.extend(sortable_lines)
-		sortable_lines = []
-		# append non-sortable line to the final output
-		output_lines.append(input_line)
-# maybe we had sortable lines pending, so append them to the final output
-if ignore_case!=0:
-	sortable_lines.sort(key=lambda x: str.lower(locale.strxfrm(x)))
-else:
-	sortable_lines.sort(key=lambda x: locale.strxfrm(x))
-output_lines.extend(sortable_lines)
-
-# run through output lines and print them, except rightmost whitespace
-
-for output_line in output_lines:
-	print output_line.rstrip()