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ddr: imx93: Add 625M bypass clock support
Add 625M bypass clock that may be used DRAM 625M bypass mode support. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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2 changed files with 6 additions and 0 deletions
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@ -648,6 +648,9 @@ void dram_pll_init(ulong pll_val)
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void dram_enable_bypass(ulong clk_val)
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void dram_enable_bypass(ulong clk_val)
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{
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{
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switch (clk_val) {
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switch (clk_val) {
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case MHZ(625):
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ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD2, 1);
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break;
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case MHZ(400):
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case MHZ(400):
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ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2);
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ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2);
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break;
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break;
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@ -148,6 +148,9 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
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dram_pll_init(MHZ(167));
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dram_pll_init(MHZ(167));
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dram_disable_bypass();
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dram_disable_bypass();
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break;
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break;
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case 625:
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dram_enable_bypass(MHZ(625));
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break;
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case 400:
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case 400:
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dram_enable_bypass(MHZ(400));
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dram_enable_bypass(MHZ(400));
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break;
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break;
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